®
ISL6620, ISL6620A
Data Sheet April 25, 2008
VR11.1 Compatible Synchronous
Rectified Buck MOSFET Drivers
The ISL6620, ISL6620A is a high frequency MOSFET driver
designed to drive upper and lower power N-Channel
MOSFET s in a synchrono us rectified buck converter topology.
The advanced PWM protocol of ISL6620, ISL6620A is
specifically designed to work with Intersil VR11.1 controllers
and combined with N-Channel MOSFETs, form a complete
core-voltage regulator solution for advanced microprocessors.
When ISL6620, ISL6620A detects a PSI
Intersil VR11.1 controller, it activates Diode Emulation (DE)
operation; otherwise, it operates in normal Continuous
Conduction Mode (CCM) PWM mode.
The IC is biased by a single low voltage supply (5V),
minimizing driving losses in high MOSFET gate capacitance
and high switching frequency applications. Each driver is
capable of driving a 3nF load with less than 10ns rise/fall time.
Bootstrapping of the upper gate driver is implemented via an
internal low forward drop diode, reducing implementatio n cost,
complexity , and allowi ng the use of higher p erformance, cost
effective N-Channel MOSFETs.
To further enhan ce light load efficiency, ISL6620, ISL6620A
enables diode emulation operation during PSI
allows Discontinuous Conduction Mode (DCM) by detecting
when the inductor current reaches zero and subsequently
turning off the low side MOSFET to prevent it from sinking
current.
An advanced adaptive shoot-through protection is integrated
to prevent both the upper and lower MOSFETs from
conducting simultaneously and to minimize dead time. The
ISL6620, ISL6620A has a 20kΩ integrated high-side
gate-to-source resistor to prevent self turn-on due to high
input bus dV/dt.
protocol sent by an
mode. This
FN6494.0
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-Through Protection
• 36V Internal Bootstrap Schottky Diode
• Advanced PWM Protocol (Patent Pending) to Support PSI
Mode, Diode Emulation, Three-State Operation
• Diode Emulation For Enhanced Light Load Efficiency
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency
- 4A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• VCC Undervoltage Protection
• Enable Input and Power-On Reset
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• DFN Package:
- Compliant to JEDEC PUB95 MO-220
DFN - Dual Flat No Leads - Package Outline
- Near Chip Scale Package Footprint, which Improves
PCB Efficiency and has a Thinner Profile
• Pb-Free (RoHS Compliant)
Applications
• High Light Load Efficiency Voltage Regulators
• Core Regulators for Advanced Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck
Regulators” for Power Train Design, Layout Guidelines,
and Feedback Compensation Design
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
ISL6620, ISL6620A
Ordering Information
PART NUMBER
(Note)
ISL6620CBZ* 6620 CBZ 0 to +70 8 Ld SOIC M8.15
ISL6620CRZ* 620Z 0 to +70 10 Ld 3x3 DF N L10.3x3
ISL6620IBZ* 6620 IBZ -40
ISL6620IRZ* 620I -40
ISL6620ACBZ* 6620A CBZ 0 to +70 8 Ld SOIC M8.15
ISL6620ACRZ* 620A 0 to +70 10 Ld 3 x 3 DF N L10.3x3
ISL6620AIBZ* 6620A IBZ -40
ISL6620AIRZ* 20AI -40
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
PART
MARKING
TEMP. RANGE
(°C)
to +85 8 Ld SOIC M8.15
to +85 10 Ld 3x 3 D FN L10.3x3
to +85 8 Ld SOIC M8.15
to +85 10 Ld 3x 3 D FN L10.3x3
PACKAGE
(Pb-free) PKG. DWG. #
Pinouts
UGATE
BOOT
PWM
GND
Block Diagrams
ISL6620, ISL6620A
(8 LD SOIC)
TOP VIEW
1
2
3
4
VCC
PWM
EN
VCC
4.25k
4k
8
7
6
5
PHASE
EN
VCC
LGATE
CONTROL
LOGIC
ISL6620, ISL6620A
*R
BOOT
SHOOT-
THROUGH
PROTECTION
VCC
UGATE
BOOT
NC
PWM
GND
ISL6620, ISL6620A
(10 LD 3x3 DFN)
TOP VIEW
1
2
3
4
5
PAD
BOOT
UGATE
PHASE
LGATE
10
9
8
7
6
PHASE
EN
NC
VCC
LGATE
*INTEGRATED 3Ω RESISTOR (R
2
) AVAILABLE ONLY IN ISL6620A
BOOT
GND
FN6494.0
April 25, 2008
Typical Application Circuit
ISL6620, ISL6620A
VTT
VR_RDY
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI
VR_FAN
VR_HOT
VIN
+5V
FB
VDIFF
VSEN
RGND
EN_VTT
EN_PWR
GND
IMON
TCOMP
+5V
COMP
ISL6334
ISL6334
TM
OFS FS SS
VCC
+5V
DAC
REF
PWM1
ISEN1-
ISEN1+
PWM2
ISEN2-
ISEN2+
PWM3
ISEN3-
ISEN3+
PWM4
ISEN4-
ISEN4+
+5V
+5V
+5V
+5V
EN
VCC
PWM
VCTRL
VCC
PWM
VCTRL
VCC
PWM
VCTRL
ISL6620,
ISL6620A
DRIVER
ISL6596
DRIVER
ISL6596
DRIVER
BOOT
UGATE
PHASE
LGATE
GND
BOOT
UGATE
PHASE
LGATE
GND
BOOT
UGATE
PHASE
LGATE
GND
BOOT
VIN
VIN
VIN
µP
LOAD
VIN
NTC
VCC
ISL6596
DRIVER
PWM
3
UGATE
PHASE
LGATE
GND
FN6494.0
April 25, 2008
ISL6620, ISL6620A
Absolute Maximum Ratings Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (V
BOOT Voltage (V
BOOT To PHASE Voltage (V
, V
EN
PWM
BOOT-GND
) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
). . . -0.3V to 25V (DC) or 36V (<200ns)
BOOT-PHASE
). . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC)
GND -8V (<20ns Pulse Width, 10µJ) to 30V (<100ns)
UGATE Voltage . . . . . . . . . . . . . . . . V
V
- 5V (<20ns Pulse Width, 10µJ) to V
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
PHASE
- 0.3V (DC) to V
PHASE
BOOT
BOOT
GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
is measured with the component mounted on a high effective thermal conductivity test board in free air.
1. θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
2. θ
JA
Tech Brief TB379.
3. For θ
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Thermal Resistance θ
(°C/W) θJC (°C/W)
JA
SOIC Package (Note 1) . . . . . . . . . . . . 100 N/A
DFN Package (Notes 2, 3). . . . . . . . . . 48 7
Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range
ISL6620IBZ, ISL6620IRZ, ISL6620AIBZ, ISL6620AIRZ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
ISL6620CBZ, ISL6620CRZ, ISL6620ACBZ, ISL6620ACRZ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
Electrical Specifications Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VCC Supply Current
No Load Switching Supply Current IVCC f_PWM = 300kHz, V_VCC = 5V 1.27 mA
Standby Supply Current IVCC PWM 0V to 2.5V transition, EN = High 1.85 mA
PWM 0V to 2.5V transition, EN = Low 1.15 mA
POWER-ON RESET AND ENABLE
VCC Rising POR Threshold 3.2 3.8 4.4 V
VCC Falling POR Threshold 3.0 3.4 4.0 V
VCC POR Hysteresis 130 300 530 mV
EN High Threshold 1.40 1.65 1.90 V
EN Low Threshold 1.20 1.35 1.55 V
PWM INPUT (See TIMING DIAGRAM" on page 6)
Input Current IPWM VPWM = 5V 500 µA
VPWM = 0V -430 µA
PWM Rising Threshold (Note 4) VCC = 5V 3.4 V
PWM Falling Threshold (Note 4) VCC = 5V 1.6 V
Three-State Lower Gate Falling Threshold VCC = 5V 1.6 V
Three-State Lower Gate Rising Threshold VCC = 5V 1.1 V
Three-State Upper Gate Rising Threshold VCC = 5V 3.2 V
Three-state Upper Gate Falling Threshold VCC = 5V 2.8 V
UGATE Rise Time (Note 4) t_RU VCC = 5V, 3nF load, 10% to 90% 8 ns
4
FN6494.0
April 25, 2008
ISL6620, ISL6620A
Electrical Specifications Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
LGATE Rise Time (Note 4) t_RL VCC = 5V, 3nF load, 10% to 90% 8 ns
UGATE Fall Time (Note 4) t_FU VCC = 5V, 3nF load, 10% to 90% 8 ns
LGATE Fall Time (Note 4) t_FL VCC = 5V, 3nF load, 10% to 90% 4 ns
UGATE Turn-On Propagation Delay (Note 4) t_PDHU VCC = 5V, 3nF load, adaptive 40 ns
LGATE Turn-On Propagation Delay (Note 4) t_PDHL VCC = 5V, 3nF load, adaptive 23 ns
UGATE Turn-Off Propagation Delay (Note 4) t_PDLU VCC = 5V, 3nF load 18 ns
LGATE Turn-Off Propagation Delay (Note 4) t_PDLL VCC = 5V, 3nF load 25 ns
Minimum Lgate on time at Diode emulation t_LG_ON_DM VCC = 5V 230 330 450 ns
OUTPUT (Note 4)
Upper Drive Source Current I_U_Source VCC = 5V, 3nF load 2 A
Upper Drive Source Impedance R_U_SOURCE 20mA source current 1 Ω
Upper Drive Sink Current I_U_SINK VCC = 5V, 3nF load 2 A
Upper Drive Sink Impedance R_U_SINK 20mA sink current 1 Ω
Lower Drive Source Current I_L_SOURCE VCC = 5V, 3nF load 2 A
Lower Drive Source Impedance R_L_SOURCE 20mA source current 1 Ω
Lower Drive Sink Current I_L_SINK VCC = 5V, 3nF load 4 A
Lower Drive Sink Impedance R_L_SINK 20mA sink current 0.4 Ω
NOTE:
4. Limits should be considered typical and are not production tested.
Functional Pin Description
PACKAGE PIN #
1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
- 3, 8 NC No connect.
3 4 PWM The PWM signal is the control input for the driver. The PWM signal can ent er three dist in ct sta tes during operation .
4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power-ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 VCC Connect this pin to 5V bias supply. This pin supplies power to the upper gate and lower gate drive. Place a high
7 9 EN Enable input pin. Connect this pin high to enable driver and low to disable driver.
8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
- 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
PIN
SYMBOL FUNCTIONSOIC DFN
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
See “Advanced PWM Protocol (Patent Pending)” on page6 for further det ails. Con nect this pin to th e PWM outp ut
of the controller.
quality low ESR ceramic capacitor from this pin to GND.
a return path for the upper gate drive.
5
FN6494.0
April 25, 2008
Description
PWM
t
PDHU
t
PDLU
ISL6620, ISL6620A
2.5V
t
TSSHD
t
RU
UGATE
LGATE
t
PDLL
1V
1V
t
RL
t
PDHL
FIGURE 1. TIMING DIAGRAM
Operation and Adaptive Shoot-through Protection
Designed for high speed switching, the ISL6620, ISL6620A
MOSFET driver controls both high-side and low-side
N-Channel FETs from one externally provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propag ation
delay [t
[t
] are provided in the “Electrical S peci fica tions” t ab le on
FL
page 4. Adaptive shoot-through circuitry monitors the LGATE
voltage and turns on the upper gate following a short delay
time [t
upper gate drive then begins to rise [t
MOSFET turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET . A short
propagation delay [t
begins to fall [t
monitors the UGATE-PHASE voltage and turns on the lower
MOSFET a short delay time [t
gate voltage drops below 1V. The lower gate then rises [t
turning on the lower MOSFET . These methods prevent both the
lower and upper MOSFETs from conducting simultaneously
(shoot-through), while adapting the dead time to the gate
charge characteristics of the MOSFETs being used.
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower MOSFET
conducts for a longer time during a switching period. The
lower gate driver is therefore sized much larger to meet this
application requirement. The 0.4Ω ON-resistance and 4A sink
current capability enable the lower gate driver to absorb the
current injected into the lower gate through the drain-to-gate
capacitor of the lower MOSFET and help prevent
], the lower gate begins to fall. T y pical fall times
PDLL
] after the LGATE voltage drops below ~1V. The
PDHU
] is encountered before the upper gate
PDLU
]. The adaptive shoot-through circuitry
FU
PDHL
] and the upper
RU
], after the upper MOSFET’s
RL
],
t
RU
t
PTS
t
TSSHD
t
FL
t
FU
t
PTS
shoot-through caused by the self turn-on of the lower
MOSFET due to high dV/dt of the switching node.
Advanced PWM Protocol (Patent Pending)
The advanced PWM protocol of ISL6620, ISL6620A is
specifically designed to work with Intersil VR11.1 controllers.
When ISL6620, ISL6620A detects a PSI
protocol sent by an
Intersil VR11.1 controller, it turns on diode emulation
operation; otherwise, it remains in normal CCM PWM mode.
The controller communicates the tri-state signal to the driver
by transitioning the PWM signal from 0V to 2V. The driver
recognizes Diode Emulation mode and after 330ns
(typically) evaluates the PHASE voltage to detect negative
current, thus turning off LGA TE. With no further PWM pulses
from the controller, both UGA T E and LGATE are low and the
output can shut down. This feature helps prevent a negative
transient on the output voltage when the output is shut down,
eliminating the Schottky diode that is used in some systems
for protecting the load from reversed output voltage events.
Otherwise, the PWM rising and falling thresholds outlined in
the “Electrical Specifications” on page 4 determine when the
lower and upper gates are enabled.
Note that the LGATE will not turn off until the diode emulation
minimum LGA TE ON-time of 350 ns is expired for a PWM lo w
to tri-level (2.5V) transition.
Diode Emulation
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6620, ISL6620 A detects the zero current crossing of the
output inductor and turns off LGATE. This prevents the low
side MOSFET from sinking current and ensures that
discontinuous conduction mode (DCM) is achieved. The
LGATE has a minimum ON-time of 350ns in DCM mode.
6
FN6494.0
April 25, 2008
ISL6620, ISL6620A
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is moni tored. Once
the rising VCC voltage exceeds 3.8V (typically), operation of
the driver is enabled and the PWM input signal takes control
of the gate drives. If VCC drops below the falling thre sho ld of
3.5V (typically), operation of the driver is disabled.
Internal Bootstrap Device
ISL6620, ISL6620A features an internal bootstrap Schottky
diode. Simply adding an external capacitor across the BOOT
and PHASE pins completes the bootstrap circuit. The
bootstrap function is also designed to prevent the bootstrap
capacitor from overcharging due to the large negative swing
at the trailing-edge of the PHASE node. This reduces
voltage stress on the BOOT to PHASE pins.
1.6
1.4
1.2
1.0
(µF)
0.8
0.6
BOOT_CAP
C
0.4
0.2
20nC
0.0
Q
= 100nC
GATE
50nC
0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
ΔV
BOOT_CAP
(V)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
The bootstrap capacitor must have a maximum voltage
rating well above the maximum voltage intended for VCC. Its
capacitance value can be estimated using Equation 1:
Q
GATE
C
BOOT_CAP
Q
GATE
where Q
at V
GS1
control MOSFETs. The ΔV
--------------------------------------
≥
ΔV
BOOT_CAP
QG1VCC•
-------------------------------
V
is the amount of gate charge per upper MOSFET
G1
GS1
•=
N
Q1
gate-source voltage and NQ1 is the number of
BOOT_CAP
term is defined as the
(EQ. 1)
allowable droop in the rail of the upper gate drive. Select
results are exemplified in Figure 2.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
layout resistance, and the selected MOSFET’s internal gate
resistance and total gate charge (Q
dissipation in the driver for a desired application is critical to
ensure safe operation. Exceeding the maximum allowable
power dissipation level may push the IC beyond the maximum
recommended operating junction temperature. The DFN
package is more suitable for high freq uency applications. See
“Layout Considerations” on page 8 for thermal impedance
), the output drive impedance, the
SW
). Calculating the power
G
improvement suggestions. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated using Equations 2 and 3, respectively:
P
Qg_TOTPQg_Q1PQg_Q2IQ
•
GS1
•
GS2
2
2
+
G1
QG1UVCC
P
Qg_Q1
P
Qg_Q2
⎛⎞
I
⎜⎟
DR
⎝⎠
---------------------------------------
V
QG2LVCC
--------------------------------------
V
QG1UVCC NQ1••
------------------------------------------------------
V
GS1
where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET data sheet; I
VCC•++=
• NQ1•=
F
SW
• NQ2•=
F
SW
Q
LVCC NQ2••
G2
-----------------------------------------------------
V
GS2
and QG2) is defined at a
and V
GS1
Q
GS2
is the driver’s total
quiescent current with no load at both drive outputs; N
and N
are number of upper and lower MOSFETs,
Q2
(EQ. 2)
+•=
F
SWIQ
(EQ. 3)
) in the
Q1
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I
Q*
VCC
product is the quiescent power of the driver without a load.
Qg_Q1
2
P
Qg_Q2
---------------------
2
GI2
N
Q2
(EQ. 4)
P
DRPDR_UPPDR_LOWIQ
R
⎛⎞
HI1
P
DR_UP
P
DR_LOW
R
EXT1RG1
--------------------------------------
⎜⎟
R
+
⎝⎠
HI1REXT1
R
⎛⎞
--------------------------------------
⎜⎟
R
⎝⎠
HI2REXT2
R
GI1
-------------
+= R
N
Q1
+
HI2
+
VCC•++=
R
LO1
----------------------------------------
R
+
LO1REXT1
R
LO2
----------------------------------------
+
R
+
LO2REXT2
EXT2RG2
P
---------------------
•=
•=
R
-------------
+=
The total gate drive power losses are dissip ated among the
resistive components along the transition path, as outlined in
Equation 4. The drive resistance dissipates a portion of the
total gate drive power losses, the rest will be dissipated by the
external gate resistors (R
resistors (R
GI1
and R
and RG2) and the internal gate
G1
) of MOSFETs. Figures 3 and 4 show
GI2
the typical upper and lower gate drives turn-on current paths.
UVCC
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
BOOT
R
PHASE
R
HI1
LO1
D
C
GD
G
R
G1R
L1
C
GS
C
DS
Q1
S
7
FN6494.0
April 25, 2008
ISL6620, ISL6620A
LVCC
D
C
GD
R
HI2
R
LO2
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
G
R
G2R
L2
C
GS
S
Q2
C
DS
Application Information
MOSFET and Driver Selection
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding the device’s absolute
maximum ratings. The negative ringing at the edges of the
PHASE node could increase the bootstrap capacitor voltage
through the internal bootstrap diode, and in some cases, it
may overstress the upper MOSFET driver. Careful layout,
proper selection of MOSFET s and p ackaging, as well as the
driver can minimize such unwanted stress.
The selection of D
a much better match (for the reasons discussed) for the
ISL6620A. Low-profile MOSFETs, such as Direct FETs and
multi-source leads devices (SO-8, LFP AK, PowerP AK), have
low parasitic lead inductances and can be driven by either
ISL6620 or ISL6620A (assuming proper layout design). The
ISL6620, missing the 3Ω integrated BOOT resistor, typically
yields slightly higher efficiency than the ISL6620A.
Layout Considerations
FA good layout helps reduce the ringing on the switching
node (PHASE) and significantly lower the stress applied to
the output drives. The following advice is meant to lead to an
optimized layout:
• Keep decoupling loops (VCC-GND and BOOT-PHASE) as
short as possible.
• Minimize trace inductance, especially on low-impedance
lines. All power traces (UGA TE, PHASE, LGATE, GND,
VCC) should be short and wide, as much as possible.
• Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
• Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
2
-PAK, or D-PAK packaged MOSFETs, is
In addition, connecting the thermal pad of the DFN package
to the power ground through a via, or placing a low noise
copper plane underneath the SOIC part is recommended for
high switching frequency, high current applications. This is to
improve heat dissipation and allow the part to achieve its
full thermal potential.
Upper MOSFET Self Turn-on Effects at Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to self
coupling via the internal C
upper MOSFET could momentarily rise up to a level greater
than the threshold voltage of the device, potentially turning
on the upper switch. Therefore, if such a situation could
conceivably be encountered, it is a common practice to
place a resistor (R
UGPH
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C
GD/CGS
threshold of the upper MOSFET. A higher dV/dt, a lower
C
DS/CGS
ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ resistor is sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated using Equation 5,
which assumes a fixed linear input ramp and neglects the
clamping effect of the body diode of the upper drive and the
bootstrap capacitor. Other parasitic components, such as lead
inductances and PCB capacitances, are also not taken into
account. Figure 5 provides a visual reference for this
phenomenon and its potential solution.
dV
V
GS_MILLER
RR
UGPHRGI
UVCC
ISL6620, ISL6620A
FIGURE 5. GATE TO SOURCE RESISTOR T O REDUCE
-------
RC
⋅⋅=
dt
+=
DU
DL
UPPER MOSFET MILLER COUPLING
of the MOSFET , the gate of the
GD
) across the gate and source of the
ratio, as well as the gate-source
V–
--------------------------------- -
dV
-------
⋅
dt
G
UGPH
DS
RC⋅
iss
C
issCGDCGS
C
GD
R
GI
C
GS
(EQ. 5)
+=
VIN
D
C
DS
Q
UPPER
S
⎛⎞
⎜⎟
⎜⎟
1e
–
rss
⎜⎟
⎜⎟
⎝⎠
C
=
rssCGD
BOOT
C
BOOT
UGATE
R
PHASE
8
FN6494.0
April 25, 2008
ISL6620, ISL6620A
Dual Flat No-Lead Plastic Package (DFN)
INDEX
SEATING
(DATUM B)
6
INDEX
AREA
(DATUM A)
NX (b)
5
SECTION "C-C"
6
AREA
C
PLANE
NX L
8
A
12
D
TOP VIEW
SIDE VIEW
8
7
D2
D2/2
N-1N
e
(Nd-1)Xe
REF.
BOTTOM VIEW
(A1)
2X
A3
NX b
5
0.415
0.15
C
E
B
A
NX
E2
E2/2
0.10 MC
0.200
NX b
C
A
0.152XB
0.10 C
C
0.08
k
AB
NX L
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
C
SYMBOL
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A3 0.20 REF -
b 0.18 0.23 0.28 5,8
D 3.00 BSC -
D2 1.95 2.00 2.05 7,8
E 3.00 BSC -
E2 1.55 1.60 1.65 7,8
e 0.50 BSC -
k0.25 - - L0.300.35 0.40 8
N102
Nd 5 3
Rev. 3 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
C
L
L
e
CC
FOR ODD TERMINAL/SIDE
TERMINAL TIP
9
FN6494.0
April 25, 2008
ISL6620, ISL6620A
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
L
h x 45°
α
e
B
0.25(0.010) C AM BS
M
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
A1
C
0.10(0.004)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 1 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN6494.0
April 25, 2008
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