intersil ISL6612A, ISL6613A intersil

®

www.BDTIC.com/Intersil

ISL6612A, ISL6613A

Data Sheet July 27, 2006

Advanced Synchronous Rectified Buck
MOSFET Drivers with Pre-POR OVP

The ISL6612A and ISL6613A are high frequency MOSFET
drivers specifically designed to drive upper and lower power
N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with HIP63xx or
ISL65xx Multi-Phase Buck PWM controllers and N-Channel
MOSFET s form complete core-voltage regulator solutions for
advanced microprocessors.

The ISL6612A drives the upper gate to 12V, while the lower
gate can be independently driven over a range from 5V to
12V. The ISL6613A drives both upper and lower gates over
a range of 5V to 12V. This drive-voltage provides the
flexibility necessary to optimize applications involving trade­offs between gate charge and conduction losses.

An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. These products add an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at
which the PHASE node is connected to the gate of the low
side MOSFET (LGATE). The output voltage of the converter
is then limited by the threshold of the low side MOSFET,
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial startup.

These drivers also feature a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.

FN9159.6

Features

• Pin-to-pin Compatible with HIP6601 SOIC family

• Dual MOSFET Drives for Synchronous Rectified Bridge

• Advanced Adaptive Zero Shoot-Through Protection

- Body Diode Detection

- Auto-zero of r

• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency

• 36V Internal Bootstrap Schottky Diode

• Bootstrap Capacitor Overcharging Prevention

• Supports High Switching Frequency (up to 2MHz)

- 3A Sinking Current Capability

- Fast Rise/Fall Times and Low Propagation Delays

• Three-State PWM Input for Output Stage Shutdown

• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement

• Pre-POR Overvoltage Protection

• VCC Undervoltage Protection

• Expandable Bottom Copper Pad for Enhanced Heat
Sinking

• Dual Flat No-Lead (DFN) Package

- Near Chip-Scale Package Footprint; Improves PCB

Efficiency and Thinner in Profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Conduction Offset Effect

DS(ON)

Applications

• Core Regulators for Intel® and AMD® Microprocessors

• High Current DC/DC Converters

• High Frequency and High Efficiency VRM and VRD

Related Literature

• Techn ical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

• Techn ical Brief TB417 for Power Train Design, Layout
Guidelines, and Feedback Compensation Design

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2005, 2006. All Rights Reserved

ISL6612A, ISL6613A

www.BDTIC.com/Intersil

Ordering Information

TEMP.

PART NUMBER PART MARKING

ISL6612ACB ISL6612ACB 0 to 85 8 Ld SOIC
ISL6612ACB-T ISL6612ACB 8 Ld SOIC Tape and Reel
ISL6612ACBZ (Note) 6612ACBZ 0 to 85 8 Ld SOIC (Pb-free)
ISL6612ACBZ-T (Note) 6612ACBZ 8 Ld SOIC Tape and Reel (Pb-free)
ISL6612ACBZA (Note) 6612ACBZ 0 to 85 8 Ld SOIC (Pb-free)
ISL6612ACBZA-T (Note) 6612ACBZ 8 Ld SOIC Tape and Reel (Pb-free)
ISL6612ACR 12AC 0 to 85 10 Ld 3x3 DFN
ISL6612ACR-T 12AC 10 Ld 3x3 DFN Tape and Reel
ISL6612ACRZ (Note) 12AZ 0 to 85 10 Ld 3x3 DF N ( Pb - f r e e )
ISL6612ACRZ-T (Note) 12AZ 10 Ld 3 x 3 DF N Tape an d Re e l ( P b -f r e e )
ISL6612AECB 6612AECB 0 to 85 8 Ld EPSOIC
ISL6612AECB-T 6612AECB 8 Ld EPSOIC Tape and Reel
ISL6612AECBZ (Note) 6612AECBZ 0 to 85 8 Ld EPSOIC (Pb-free)
ISL6612AECBZ-T (Note) 6612AECBZ 8 Ld EPSOIC Tape and Reel (Pb-free)
ISL6612AEIB 6612AEIB -40 to +85 8 Ld EPSOIC
ISL6612AEIB-T 6612AEIB 8 Ld EPSOIC Tape and Reel
ISL6612AEIBZ (Note) 6612AEIBZ -40 to +85 8 Ld EPSOIC (Pb-free)
ISL6612AEIBZ-T (Note) 6612AEIBZ 8 Ld EPSOIC Tape and Reel (Pb-free)
ISL6612AIB ISL6612AIB -40 to +85 8 Ld SOIC
ISL6612AIB-T ISL6612AIB 8 Ld SOIC Tape and Reel
ISL6612AIBZ (Note) 6612AIBZ -40 to +85 8 Ld SOIC (Pb-free)
ISL6612AIBZ-T (Note) 6612AIBZ 8 Ld SOIC Tape and Reel (Pb-free)
ISL6612AIR 12AI -40 to +85 10 Ld 3x3 DFN
ISL6612AIR-T 12AI 10 Ld 3x3 DFN Tape and Reel
ISL6612AIRZ (Note) 2AIZ -40 to +85 10 Ld 3x3 DFN (Pb-free)
ISL6612AIRZ-T (Note) 2AIZ 10 Ld 3x3 DFN Tape and Reel (Pb-free)
ISL6613ACB ISL6613ACB 0 to 85 8 Ld SOIC
ISL6613ACB-T ISL6613ACB 8 Ld SOIC Tape and Reel
ISL6613ACBZ (Note) 6613ACBZ 0 to 85 8 Ld SOIC (Pb-free)
ISL6613ACBZ-T (Note) 6613ACBZ 8 Ld SOIC Tape and Reel (Pb-free)
ISL6613ACR 13AC 0 to 85 10 Ld 3x3 DFN
ISL6613ACR-T 13AC 10 Ld 3x3 DFN Tape and Reel
ISL6613ACRZ (Note) 13AZ 0 to 85 10 Ld 3x3 DF N ( Pb - f r e e )
ISL6613ACRZ-T (Note) 13AZ 10 Ld 3 x 3 DF N Tape an d Re e l ( P b -f r e e )
ISL6613AECB 6613AECB 0 to 85 8 Ld EPSOIC
ISL6613AECB-T 6613AECB 8 Ld EPSOIC Tape and Reel
ISL6613AECBZ (Note) 6613AECBZ 0 to 85 8 Ld EPSOIC (Pb-free)
ISL6613AECBZ-T (Note) 6613AECBZ 8 Ld EPSOIC Tape and Reel (Pb-free)
ISL6613AEIB 6613AEIB -40 to +85 8 Ld EPSOIC
ISL6613AEIB-T 6613AEIB 8 Ld EPSOIC Tape and Reel

RANGE (°C) PACK AGE

PKG.

DWG. #

M8.15
M8.15
M8.15
M8.15
M8.15

M8.15
L10.3x3
L10.3x3
L10.3x3
L10.3x3
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B

M8.15

M8.15

M8.15

M8.15
L10.3x3
L10.3x3
L10.3x3
L10.3x3

M8.15

M8.15

M8.15

M8.15
L10.3x3
L10.3x3
L10.3x3
L10.3x3
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B

2

FN9159.6

July 27, 2006

ISL6612A, ISL6613A

www.BDTIC.com/Intersil

Ordering Information (Continued)

TEMP.

PART NUMBER PART MARKING

RANGE (°C) PACK AGE

ISL6613AEIBZ (Note) 6613AEIBZ -40 to +85 8 Ld EPSOIC (Pb-free)
ISL6613AEIBZ-T (Note) 6613AEIBZ 8 Ld EPSOIC Tape and Reel (Pb-free)
ISL6613AIB ISL6613AIB -40 to +85 8 Ld SOIC
ISL6613AIB-T ISL6613AIB 8 Ld SOIC Tape and Reel
ISL6613AIBZ (Note) 6613AIBZ -40 to +85 8 Ld SOIC (Pb-free)
ISL6613AIBZ-T (Note) 6613AIBZ 8 Ld SOIC Tape and Reel (Pb-free)
ISL6613AIR 13AI -40 to +85 10 Ld 3x3 DFN
ISL6613AIR-T 13AI 10 Ld 3x3 DFN Tape and Reel
ISL6613AIRZ (Note) 3AIZ -40 to +85 10 Ld 3x3 DFN (Pb-free)
ISL6613AIRZ-T (Note) 3AIZ 10 Ld 3x3 DFN Tape and Reel (Pb-free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Check website for availability.

PKG.

DWG. #

M8.15B
M8.15B

M8.15

M8.15

M8.15

M8.15
L10.3x3
L10.3x3
L10.3x3
L10.3x3

Pinouts

ISL6612ACB, ISL6612AIB, ISL6613ACB, ISL6613AIB (SOIC)

ISL6612AECB, ISL6612AEIB, ISL6613AECB, ISL6613AEIB

(EPSOIC)

TOP VIEW

UGATE

BOOT

PWM

GND

1
2

GND

3
4

8
7
6
5

PHASE
PVCC
VCC
LGATE

ISL6612ACR, ISL6612AIR, ISL6613ACR, ISL6613AIR

(10 LD 3X3 DFN)

TOP VIEW

UGATE

BOOT

N/C

PWM

GND

1
2

GND

3
4
5

10

9
8
7
6

PHASE
PVCC

N/C
VCC

LGATE

Block Diagram

VCC

PWM

+5V

3

10K

8K

UVCC

Pre-POR OVP

FEATURES

POR/

CONTROL

LOGIC

ISL6612A AND ISL6613A

SHOOT-

THROUGH

PROTECTION

PAD

FOR DFN AND EPSOIC-DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.

(LVCC)

BOOT

UGATE

PHASE

PVCC

UVCC = VCC FOR ISL6612A
UVCC = PVCC FOR ISL6613A

LGATE

GND

FN9159.6

July 27, 2006

ISL6612A, ISL6613A

www.BDTIC.com/Intersil

Typical Application - 3 Channel Converter Using ISL65xx and ISL6612A Gate Drivers

VSEN

PGOOD

VFB

VCC

+5V

COMP

PWM1
PWM2
PWM3

+5V TO 12V

PVCC

PWM

+5V TO 12V

PVCC

PWM

VCC

ISL6612A

GND

VCC

ISL6612A

BOOT

UGATE

PHASE

LGATE

BOOT

UGATE

PHASE

LGATE

+12V

+12V

+V

CORE

VID

FS

MAIN

CONTROL

ISL65xx

GND

ISEN1
ISEN2
ISEN3

GND

+5V TO 12V

VCC

PVCC

ISL6612A

PWM

GND

+12V

BOOT

UGATE

PHASE

LGATE

4

FN9159.6

July 27, 2006

ISL6612A, ISL6613A

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V

BOOT Voltage (V
Input Voltage (V

UGATE. . . . . . . . . . . . . . . . . . . V

V

BOOT-GND

PWM

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V

GND - 5V (<100ns Pulse Width, 2µJ) to V

PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V

GND - 8V (<400ns, 20µJ) to 30V (<200ns, V

ESD Rating

). . . . . . . . . . . . . . . . . . . . . . . . . . . 36V

). . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V

PHASE

- 0.3VDC to V

to V

DC

BOOT-GND

BOOT

BOOT

PVCC

PVCC

to 15V

DC

+ 0.3V

+ 0.3V

+ 0.3V

+ 0.3V

DC

<36V)

Thermal Resistance θ

SOIC Package (Note 1). . . . . . . . . . . . 100 N/A

EPSOIC Package (Notes 2, 3) . . . . . . 50 7

DFN Package (Notes 2, 3). . . . . . . . . . 48 7

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

Human Body Model . . . . . . . . . . . . . . . . . . . .Class I JEDEC STD

Recommended Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -40°C to 85°C

Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%

Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . .5V to 12V ±10%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air.

1. θ

JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See T ech

2. θ

JA

Brief TB379.

3. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

(°C/W) θJC (°C/W)

JA

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Bias Supply Current I

VCC

ISL6612A, f
ISL6613A, f

I

VCC

ISL6612A, f
ISL6613A, f

Gate Drive Bias Current I

PVCC

ISL6612A, f
ISL6613A, f

I

PVCC

ISL6612A, f
ISL6613A, f

POWER-ON RESET AND ENABLE

VCC Rising Threshold T
VCC Rising Threshold T
VCC Falling Threshold T
VCC Falling Threshold T

= 0°C to 85°C 9.35 9.80 10.00 V

A

= -40°C to 85°C 8.35 9.80 10.00 V

A

= 0°C to 85°C 7.35 7.60 8.00 V

A

= -40°C to 85°C 6.35 7.60 8.00 V

A

PWM INPUT (See Timing Diagram on Page 7)

Input Current I

PWM

V

= 5V - 450 - µA

PWM

= 0V - -400 - µA

V

PWM

PWM Rising Threshold VCC = 12V - 3.00 - V
PWM Falling Threshold VCC = 12V - 2.0 0 - V
Typical Three-State Shutdown Window VCC = 12V 1.80 - 2.40 V
Three-State Lower Gate Falling Threshold VCC = 12V - 1.50 - V
Three-State Lower Gate Rising Threshold VCC = 12V - 1.00 - V

= 300kHz, V

PWM

= 300kHz, V

PWM

= 1MHz, V

PWM

= 1MHz, V

PWM

= 300kHz, V

PWM

= 300kHz, V

PWM

= 1MHz, V

PWM

= 1MHz, V

PWM

=12V - 7.2 - mA

VCC

=12V - 4.5 - mA

VCC

= 12V - 11 - mA

VCC

= 12V - 5 - mA

VCC

= 12V - 2.5 - mA

PVCC

= 12V - 5.2 - mA

PVCC

= 12V - 7 - mA

PVCC

= 12V - 13 - mA

PVCC

5

FN9159.6

July 27, 2006

ISL6612A, ISL6613A

www.BDTIC.com/Intersil

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Three-State Upper Gate Rising Threshold VCC = 12V - 3.20 - V
Three-State Upper Gate Falling Threshold VCC = 12V - 2.60 - V
Shutdown Holdoff Time t
UGATE Rise Time t
LGATE Rise Time t
UGATE Fall Time t
LGATE Fall Time t
UGATE Turn-On Propagation Delay (Note 4) t
LGATE Turn-On Propagation Delay (Note 4) t
UGATE Turn-Off Propagation Delay (Note 4) t
LGATE Turn-Off Propagation Delay (Note 4) t
LG/UG Three-State Propagation Delay (Note 4) t

OUTPUT (Note 4)

Upper Drive Source Current I
Upper Drive Source Impedance R
Upper Drive Sink Current I
Upper Drive Transition Sink Impedance R
Upper Drive DC Sink Impedance R
Lower Drive Source Current I
Lower Drive Source Impedance R
Lower Drive Sink Current I
Lower Drive Sink Impedance R

NOTE:

4. Guaranteed by design. Not 100% tested in production.

U_SOURCEVPVCC

U_SOURCE

U_SINK_TR
U_SINK_DC

L_SOURCEVPVCC

L_SOURCE

TSSHD

RU
RL
FU

FL
PDHU
PDHL
PDLU

PDLL

PDTS

U_SINK

L_SINK

L_SINK

V

= 12V, 3nF Load, 10% to 90% - 26 - ns

PVCC

V

= 12V, 3nF Load, 10% to 90% - 18 - ns

PVCC

V

= 12V, 3nF Load, 90% to 10% - 18 - ns

PVCC

V

= 12V, 3nF Load, 90% to 10% - 12 - ns

PVCC

V

= 12V, 3nF Load, Adaptive - 10 - ns

PVCC

V

= 12V, 3nF Load, Adaptive - 10 - ns

PVCC

V

= 12V, 3nF Load - 10 - ns

PVCC

V

= 12V, 3nF Load - 10 - ns

PVCC

V

= 12V, 3nF Load - 10 - ns

PVCC

= 12V, 3nF Load - 1.25 - A
150mA Source Current 1.25 2.0 3.0 Ω
V

= 12V, 3nF Load - 2 - A

PVCC

70ns With Respect To PWM Falling - 1.3 2.2 Ω
150mA Source Current 0.9 1.65 3.0 Ω

= 12V, 3nF Load - 2 - A
150mA Source Current 0.85 1.25 2.2 Ω
V

= 12V, 3nF Load - 3 - A

PVCC

150mA Sink Current 0.60 0.80 1.35 Ω

- 245 - ns

Functional Pin Description

PACKAGE PIN #

1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the

- 3, 8 N/C No Connection.

3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see

4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 VCC Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
7 9 PVCC This pin supplies power to both upper and lower gate drives in ISL6613A; only the lower gate drive in ISL6612A.

8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides

9 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.

PIN

SYMBOL FUNCTIONSOIC DFN

PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in choosing the capacitor value.

the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the
controller.

Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.

a return path for the upper gate drive.

6

FN9159.6

July 27, 2006

Description

www.BDTIC.com/Intersil

ISL6612A, ISL6613A

PWM

t

PDLU

t

FU

t

RL

FIGURE 1. TIMING DIAGRAM

UGATE

LGATE

t

PDLL

t

PDHU

t

RU

t

FL

t

PDHL

Operation

Designed for versatility and speed, the ISL6612A and
ISL6613A MOSFET drivers control both high-side and low­side N-Channel FETs of a half-bridge power train from one
externally provided PWM signal.

Prior to VCC exceeding its POR level, the Pre-POR
overvoltage protection function is activated during initial startup;
the upper gate (UGATE) is held low and the lower gate
(LGATE), controlled by the Pre-POR overvoltage protection
circuits, is connected to the PHASE. Once the VCC voltage
surpasses the VCC Rising Threshold (See Electrical
Specifications), the PWM signal takes control of gate
transitions. A rising edge on PWM initiates the turn-off of the
lower MOSFET (see Timing Diagram). Af ter a short
propagation delay [t
fall times [t

] are provided in the Electrical Specifications

FL

section. Adaptive shoot-through circuitry monitors the PHASE
voltage and determines the upper gate delay time [t
prevents both the lower and upper MOSFETs from conducting
simultaneously . Once this delay period is complete, the upper
gate drive begins to rise [t

A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
gate begins to fall [t
circuitry determines the lower gate delay time, t
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See next se c ti o n f o r
details). The lower gate then rises [t
MOSFET.

], the lower gate begins to fall. Typical

PDLL

PDHU

] and the upper MOSFET turns on.

RU

] is encountered before the upper

PDLU

]. Again, the adaptive shoot-through

FU

PDHL

], turning on the lower

RL

]. This

. The

1.5V<PWM<3.2V

t

TSSHD

Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)

These drivers incorporate a unique adaptive deadtime control
technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFET s’
body-diode conduction, and to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.

During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.2V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the r
drop in the phase voltage preventing from false detection of the

-0.2V phase level during r
of zero current, the UGATE is released after 35ns delay of the
LGATE dropping below 0.5V. During the phase detection, the
disturbance of LGATE’s falling transition on the PHASE node is
blanked out to prevent falsely tripping. Once the PHASE is
high, the advanced adaptive shoot-through circuitry monitors
the PHASE and UGA TE volt ages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V , the LGATE is released to turn on.

Three-State PWM Input

A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling

t

PDTS

1.0V<PWM<2.6V

t

TSSHD

conduction period. In the case

DS(ON

t

PDTS

DS(ON)

7

FN9159.6

July 27, 2006

ISL6612A, ISL6613A

www.BDTIC.com/Intersil

thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.

This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.

In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.

Power-On Reset (POR) Function

During initial startup, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 9.8V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 7.6V (typically), operation of the driver is
disabled.

Pre-POR Overvoltage Protection

Prior to VCC exceeding its POR level, the upper gate is held
low and the lower gate is controlled by the overvoltage
protection circuits during initial startup. The PHASE is
connected to the gate of the low side MOSFET (LGATE),
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial startup. For
complete protection, the low side MOSFET should have a
gate threshold well below the maximum voltage rating of the
load/microprocessor.

When VCC drops below its POR level, both gates pull low
and the Pre-POR overvoltage protection circuits are not
activated until VCC resets.

Internal Bootstrap Device

Both drivers feature an internal bootstrap schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.

The bootstrap capacitor must have a maximum voltage
rating above UVCC + 5V and its capacitance value can be
chosen from the following equation:

Q

GATE

C

BOOT_CAP

Q

GATE

--------------------------------------

≥

∆V

BOOT_CAP

QG1UVCC•

------------------------------------

V

GS1

(EQ. 1)

•=

N

Q1

where Q
at V
control MOSFETs. The ∆V

is the amount of gate charge per upper MOSFET

G1

gate-source voltage and NQ1 is the number of

GS1

BOOT_CAP

term is defined as the

allowable droop in the rail of the upper gate drive.
As an example, suppose two IRLR7821 FET s are chosen as

the upper MOSFETs. The gate charge, Q
sheet is 10nC at 4.5V (V
Q

is calculated to be 53nC for UVCC (i.e. PVCC in

GATE

) gate-source voltage. Then the

GS

, from the data

G

ISL6613A, VCC in ISL6612A) = 12V. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.267µF is required.

1.6

1.4

1.2

1.

(µF)

0.8

0.6

BOOT_CAP

C

0.4

0.2
20nC

0.0

FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

Q

50nC

VOLTAGE

= 100nC

GATE

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
∆V

BOOT_CAP

(V)

Gate Drive Voltage Versatility

The ISL6612A and ISL6613A provide the user flexibility in
choosing the gate drive voltage for efficiency optimization.
The ISL6612A upper gate drive is fixed to VCC [+12V], but
the lower drive rail can range from 12V down to 5V
depending on what voltage is applied to PVCC. The
ISL6613A ties the upper and lower drive rails together.
Simply applying a voltage from 5V up to 12V on PVCC sets
both gate drive rail voltages simultaneously.

Power Dissipation

Package power dissipation i s mai nl y a fu nction of the
switching frequency (F
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
125°C. The maximum allowable IC power dissipation for the
SO8 package is approximately 800mW at room temperature,
while the power dissipation capacity in the EPSOIC and DFN
packages, with an exposed heat escape pad, is more than
2W and 1.5W, respectively. Both EPSOIC and DFN

), the output drive impedance, the

SW

8

FN9159.6

July 27, 2006

ISL6612A, ISL6613A

www.BDTIC.com/Intersil

packages are more suitable for high frequency applications.
See Layout Considerations paragraph for thermal transfer
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation
is used to ensure safe operation at the desired frequency for
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.

the selected MOSFETs. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively,

F

SWIQ

(EQ. 2)

+•=

(EQ. 3)

P

Qg_TOTPQg_Q1PQg_Q2IQ

QG1UVCC

•

P

Qg_Q1

P

Qg_Q2

⎛⎞

I

⎜⎟

DR

⎝⎠

---------------------------------------

V

GS1

QG2LVCC

•

--------------------------------------

V

GS2

QG1UVCC NQ1••

------------------------------------------------------

V

GS1

2

VCC•++=

2

• NQ1•=

F

SW

• NQ2•=

F

SW

LVCC NQ2••

Q

G2

-----------------------------------------------------+

V

GS2

LVCC

BOOT

R

PHASE

R

HI2

R

LO2

D

C

GD

R

HI1

LO1

G

R

GI1

R

G1

C

GS

S

C

GD

G

R

GI2

R

G2

C

GS

S

C

DS

Q1

D

C

DS

Q2

UVCC

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; I
quiescent current with no load at both drive outputs; N
and N

are number of upper and lower MOSFETs,

Q2

and QG2) is defined at a

G1

and V

GS1

Q

GS2

is the driver’s total

) in the

Q1

respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I

Q*

VCC
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.

The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
(R

and R

GI1

and RG2) and the internal gate resistors

G1

) of MOSFETs. Figures 3 and 4 show the

GI2

typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:

P

DRPDR_UPPDR_LOWIQ

R

⎛⎞

HI1

P

DR_UP

--------------------------------------

⎜⎟

R

+

⎝⎠

HI1REXT1

VCC•++=

R

LO1

----------------------------------------+

R

+

LO1REXT1

P

Qg_Q1

---------------------

•=

(EQ. 4)

2

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

Layout Considerations

For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.

Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.

P

DR_LOW

R

EXT1RG1

R

⎛⎞

HI2

--------------------------------------

⎜⎟

R

+

⎝⎠

HI2REXT2

R

GI1

-------------+=

N

Q1

R

LO2

----------------------------------------+

R

+

LO2REXT2

R

EXT2RG2

P

Qg_Q2

---------------------

•=

R

GI2

-------------+=

N

Q2

2

9

FN9159.6

July 27, 2006

ISL6612A, ISL6613A

www.BDTIC.com/Intersil

Dual Flat No-Lead Plastic Package (DFN)

INDEX

SEATING

(DATUM B)

6

INDEX

AREA

(DATUM A)

NX (b)

5

SECTION "C-C"

6

AREA

C

PLANE

NX L

8

A

12

D

TOP VIEW

SIDE VIEW

8

7

D2

D2/2

N-1N
e

(Nd-1)Xe

REF.

BOTTOM VIEW

(A1)

2X

A3

NX b
5

0.415

0.15

C

E

B

A

NX

E2

E2/2

0.10 MC

0.200

NX b

C

A

0.152XB

0.10 C

0.08

C

k

AB

NX L

L10.3x3

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

C

SYMBOL

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A3 0.20 REF -

b 0.18 0.23 0.28 5,8

D 3.00 BSC -

D2 1.95 2.00 2.05 7,8

E 3.00 BSC -

E2 1.55 1.60 1.65 7,8

e 0.50 BSC -

k0.25 - - ­L0.300.35 0.40 8

N102

Nd 5 3

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

C

L

L

e

CC

FOR ODD TERMINAL/SIDE

TERMINAL TIP

NOTESMIN NOMINAL MAX

Rev. 3 6/04

10

FN9159.6

July 27, 2006

ISL6612A, ISL6613A

www.BDTIC.com/Intersil

Small Outline Exposed Pad Plastic Packages (EPSOIC)

N

INDEX
AREA

123

TOP VIEW

-A­D

e

B

0.25(0.010) C AM BS
SIDE VIEW

123

N

P

BOTTOM VIEW

H

E

-B-

SEATING PLANE

A

-C-

A1

M

P1

0.25(0.010) BM M

L

h x 45

α

0.10(0.004)

M8.15B

8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.056 0.066 1.43 1.68 -

A1 0.001 0.005 0.03 0.13 -

B 0.0138 0.0192 0.35 0.49 9
C 0.0075 0.0098 0.19 0.25 ­D 0.189 0.196 4.80 4.98 3
E 0.150 0.157 3.31 3.39 4

o

C

e 0.050 BSC 1.27 BSC ­H 0.230 0.244 5.84 6.20 ­h 0.010 0.016 0.25 0.41 5
L 0.016 0.035 0.41 0.64 6
N8 87

α

P - 0.094 - 2.387 11

P1 - 0.094 - 2.387 11

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.

11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 3 6/05

11

FN9159.6

July 27, 2006

ISL6612A, ISL6613A

www.BDTIC.com/Intersil

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

12

FN9159.6

July 27, 2006