®
ISL6611A
Data Sheet March 19, 2009 FN6881.0
Phase Doubler with Integrated Drivers
and Phase Shedding Function
The ISL6611A utilizes Intersil’s proprietary Phase Doubler
scheme to modulate two-phase power trains with single
PWM input. It doubles the number of phases that Intersil’s
ISL63xx multiphase controllers can support. At the same
time, the PWM line can be pulled high to disable the
corresponding phase or higher phase(s) when the enable
pin (EN_PH) is pulled low. This simplifies the phase
shedding implementation. For layout simplicity and
improving system performance, the device integrates two 5V
drivers (ISL6609) and current balance function.
The ISL6611A is designed to minimize the number of analog
signals interfacing between the controller and drivers in high
phase count and scalable applications. The common COMP
signal, which is usually seen with conventional cascaded
configuration, is not required; this improves noise immunity
and simplifies the layout. Furthermore, the ISL6611A
provides low part count and a low cost advantage over the
conventional cascaded technique.
The IC is biased by a single low voltage supply (5V),
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications.
Bootstrapping of the upper gate driver is implemented via an
internal low forward drop diode, reducing implementation
cost, complexity, and allowing the use of higher
performance, cost effective N-Channel MOSFETs. Adaptive
shoot-through protection is integrated to prevent both
MOSFETs from conducting simultaneously.
The ISL6611A features 4A typical sink current for the lower
gate driver, enhancing the lower MOSFET gate hold-down
capability during PHASE node rising edge, preventing power
loss caused by the self turn-on of the lower MOSFET due to
the high dV/dt of the switching node.
The ISL6611A also features an input that recognizes a
high-impedance state, working together with Intersil
multiphase PWM controllers to prevent negative transients
on the controlled output voltage when operation is
suspended. This feature eliminates the need for the Schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
Features
• Proprietary Phase Doubler Scheme with Phase Shedding
Function (Patent Pending)
- Enhanced Light to Full Load Efficiency
• Patented Current Balancing with r
and Adjustable Gain
• Quad MOSFET Drives for Two Synchronous Rectified
Bridge with Single PWM Input
• Channel Synchronization and Interleaving Options
• Adaptive Zero Shoot-Through Protection
•0.4Ω On-Resistance and 4A Sink Current Capability
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention (ISL6611A)
• Supports High Switching Frequency (Up to 1MHz)
- Fast Output Rise and Fall
• Tri-State PWM Input for Output Stage Shutdown
• Phase Enable Input and PWM Forced High Output to
Interface with Intersil’s Controller for Phase Shedding
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline
- Near Chip-Scale Package Footprint; Improves PCB
Utilization, Thinner Profile
- Pb-Free (RoHS Compliant)
Current Sensing
DS(ON)
Applications
• High Current Low Voltage DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
• High Phase Count and Phase Shedding Applications
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
In addition, the ISL6611A’s bootstrap function is designed to
prevent the BOOT capacitor from overcharging, should
excessively large negative swings occur at the transitions of
the PHASE node.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
ISL6611A
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
ISL6611ACRZ* 66 11ACRZ 0 to +70 16 Ld 4x4 QFN L16.4x4
ISL6611AIRZ* 66 11AIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
Pinout
ISL6611A
(16 LD QFN)
TOP VIEW
SYNC
PWM1
VCC
PHASEA
15
16 14 13
GND
LGATEA
PVCC
IGAIN
1
2
3
4
17
GND
6578
PGND
LGATEB
EN_PH
12
11
10
9
PHASEB
UGATEA
BOOTA
BOOTB
UGATEB
2
FN6881.0
March 19, 2009
Block Diagram
VCC
PVCC
ISL6611A
R
BOOT
BOOTA
UGATEA
PWM
EN_PH
SYNC
IGAIN
4.9k
CURRENT
BALANCE BLOCK
PHASEA
PHASEB
4.6k
PROTECTION
CONTROL
LOGIC
GND
INTEGRATED 3Ω RESISTOR (R
PAD
PVCC
PROTECTION
MUST BE SOLDERED TO THE CIRCUIT’S GROUND
SHOOT-
THROUGH
PGND
SHOOT-
THROUGH
PGND
R
BOOT
) IN ISL6611A
BOOT
PVCC
PHASEA
LGATEA
PGND
BOOTB
UGATEB
PHASEB
PVCC
LGATEB
CHANNEL A
CHANNEL B
3
FN6881.0
March 19, 2009
Functional Pin Descriptions
ISL6611A
PACKAGE
PIN #
1 GND Bias and reference ground. All signals are referenced to this node. It is also the return of the sample and hold of the
2 LGATEA Lower gate drive output of Channel A. Connect to gate of the low-side power N-Channel MOSFET.
3 PVCC This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from
4 IGAIN A resistor from this pin to GND sets the current balance gain. See “Current Balance and Maximum Frequency” on
5 PGND Power ground return of both low gate drivers. It is also the return of the phase node clamp circuits.
6 LGATEB Lower gate drive output of Channel B. Connect to gate of the low-side power N-Channel MOSFET.
7 EN_PH Driver Enable Input. A signal high input enables the driver at the PWM rising edge, a signal low input pulls PWM pin to
8 PHASEB Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel B. This pin
9 UGATEB Upper gate drive output of Channel B. Connect to gate of high-side power N-Channel MOSFET.
10 BOOTB Floating bootstrap supply pin for the upper gate drive of Channel B. Connect the bootstrap capacitor between this pin
11 BOOTA Floating bootstrap supply pin for the upper gate drive of Channel A. Connect the bootstrap capacitor between this pin
12 UGATEA Upper gate drive output of Channel A. Connect to gate of high-side power N-Channel MOSFET.
13 PHASEA Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel A. This pin
14 VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic
15 PWM The PWM input signal triggers the J-K flip flop and alternates its input to channel A and B. Both channels are effectively
16 SYNC A signal high synchronizes both channels with no phase shifted. A signal low interleaves both channels with 180°
17 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
PIN
SYMBOL FUNCTION
r
current sensing circuits. Place a high quality low ESR ceramic capacitor from this pin to VCC.
DS(ON)
this pin to PGND.
page 11 for more details.
VCC at the PWM falling edge and then enters tri-state.
provides a return path for the upper gate drive.
and the PHASEB pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See“Bootstrap
Considerations” on page 9 for guidance in choosing the capacitor value.
and the PHASEA pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Bootstrap
Considerations” on page 9 for guidance in choosing the capacitor value.
provides a return path for the upper gate drive.
capacitor from this pin to GND.
modulated. The PWM signal can enter three distinct states during operation, see “Tri-State PWM Input” on page 9 for
further details. Connect this pin to the PWM output of the controller. The pin is pulled to VCC when EN_PH is low and
the PWM input starts transitioning low.
out-of-phase.
4
FN6881.0
March 19, 2009
ISL6611A
Typical Application I (2-Phase Controller for 4-Phase Operation)
+5V
+5V
+5V
SYNC
FB
COMP
VCC AND PVCC
EN_PH
SYNC
BOOTA
UGATEA
PHASEA
LGATEA
+12V
VR_RDY
VID
VSEN
V
CC
EN
FS
MAIN
CONTROL
ISL63xx
PWM1
ISEN1-
ISEN1+
PWM2
EN_PH
ISL6611A
PWM
IGAIN
GND AND PGND
+5V
VCC AND PVCC
EN_PH
SYNC
ISL6611A
PWM
BOOTB
UGATEB
PHASEB
LGATEB
BOOTA
UGATEA
PHASEA
LGATEA
BOOTB
UGATEB
PHASEB
+12V
+12V
+12V
+V
CORE
GND
5
ISEN2-
ISEN2+
IGAIN
GND AND PGND
LGATEB
FN6881.0
March 19, 2009
ISL6611A
Typical Application II (4-Phase Controller to 8-Phase Operation)
+5V
VCC & PVCC
EN_PH
SYNC
PWM
ISL6611A
IGAIN
GND & PGND
BOOTA
UGATEA
PHASEA
LGATEA
BOOTB
UGATEB
PHASEB
LGATEB
+12V
+12V
+5V
FB
VSEN
V
CC
COMP
PWM1
SYNC
+5V
+V
CORE
VR_RDY
VID
EN
FS
MAIN
CONTROL
ISL63xx
ISEN1-
ISEN1+
PWM2
ISEN2-
ISEN2+
PWM3
EN_PH2
EN_PH3
+5V
VCC & PVCC
EN_PH
SYNC
PWM
ISL6611A
IGAIN
GND & PGND
+5V
VCC & PVCC
EN_PH
SYNC
PWM
ISL6611A
IGAIN
GND & PGND
BOOTA
UGATEA
PHASEA
LGATEA
BOOTB
UGATEB
PHASEB
LGATEB
BOOTA
UGATEA
PHASEA
LGATEA
BOOTB
UGATEB
PHASEB
LGATEB
+12V
+12V
+12V
+12V
GND
6
ISEN3-
ISEN3+
PWM4
ISEN4-
ISEN4+
EN_PH4
+5V
VCC & PVCC
EN_PH
SYNC
PWM
ISL6611A
IGAIN
GND & PGND
BOOTA
UGATEA
PHASEA
LGATEA
BOOTB
UGATEB
PHASEB
LGATEB
+12V
+12V
FN6881.0
March 19, 2009
ISL6611A
Absolute Maximum Ratings Thermal Information
Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . -0.3V to 6.7V
Input Voltage (V
BOOT Voltage (V
BOOT To PHASE Voltage (V
, V
EN_PH
BOOT-GND
PWM, VSYNC
) . . . . . -0.3V to VCC + 0.3V
). . . -0.3V to 27V (DC) or 36V (<200ns)
BOOT-PHASE
). . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 27V (DC)
GND -8V (<20ns Pulse Width, 10µJ) to 30V (<100ns)
UGATE Voltage . . . . . . . . . . . . . . . . V
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
V
- 5V (<20ns Pulse Width, 10µJ) to V
PHASE
- 0.3V (DC) to V
PHASE
BOOT
BOOT
GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty
NOTES:
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
1. θ
JA
Tech Brief TB379.
2. For θ
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications These specifications apply for recommended ambient temperature, unless otherwise noted. Parameters with
MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
SUPPLY CURRENT (Note 3)
Bias Supply Current I
VCC+PVCC
BOOTSTRAP DIODE
Forward Voltage V
POWER-ON RESET
POR Rising -3.44.2V
POR Falling 2.5 3.0 - V
Hysteresis - 400 - mV
EN_PH INPUT
EN_PH Minimum LOW Threshold --0.8V
EN_PH Maximum HIGH Threshold 2.0 - - V
SYNC INPUT
SYNC Minimum LOW Threshold --0.8V
SYNC Maximum HIGH Threshold 2.0 - - V
PWM pin floating, V
EN_PH = 5V
PWM pin floating, V
EN_PH = 0V
= 600kHz, V
F
PWM
EN_PH = 5V; SYNC = 0V
F
= 300kHz, V
PWM
EN_PH = 5V; SYNC = 5V
Forward bias current = 2mA
F
T
= 0°C to +70°C
A
Forward bias current = 2mA
T
= -40°C to +85°C
A
Thermal Resistance (Typical) θ
(°C/W) θJC(°C/W)
JA
QFN Package (Notes 1, 2). . . . . . . . 44 7
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature
ISL6611ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6611AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
VCC
VCC
VCC
VCC
= V
= V
= V
= V
PVCC
PVCC
PVCC
PVCC
= 5V,
= 5V,
= 5V,
= 5V,
-1.25- mA
-1.20- mA
-2.20- mA
-2.50- mA
0.30 0.60 0.70 V
0.30 0.60 0.75 V
7
FN6881.0
March 19, 2009
ISL6611A
Electrical Specifications These specifications apply for recommended ambient temperature, unless otherwise noted. Parameters with
MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Minimum SYNC Pulse --40ns
Synchronization Delay -50-ns
Interleaving Mode Phase Shift SYNC = 5V, PWM = 300kHz, 10% Width - 180 - °
Synchronization Mode Phase Shift SYNC = 0V, PWM = 300kHz, 10% Width - 0 - °
PWM INPUT
Sinking Impedance R
Source Impedance R
Tri-State Rising Threshold V
Tri-State Falling Threshold V
PWM_SNK
PWM_SRC
VCC
VCC
= V
= V
= 5V (250mV Hysteresis) 1.00 1.20 1.40 V
PVCC
= 5V (300mV Hysteresis) 3.10 3.40 3.70 V
PVCC
PWM Pulled High Threshold EN_PH = LOW, Ramping PWM low - 3.4 - V
SWITCHING TIME (Note 3, See Figure 1 on Page 9)
UGATE Rise Time t
LGATE Rise Time t
UGATE Fall Time t
LGATE Fall Time t
UGATE Turn-Off Propagation Delay t
LGATE Turn-Off Propagation Delay t
UGATE Turn-On Propagation Delay t
LGATE Turn-On Propagation Delay t
Tri-state to UG/LG Rising Propagation Delay t
Tri-State Shutdown Holdoff Time t
RU
RL
FU
FL
PDLU
PDLL
PDHU
PDHL
PTS
TSSHD
3nF Load - 8.0 - ns
3nF Load - 8.0 - ns
3nF Load - 8.0 - ns
3nF Load - 4.0 - ns
Unloaded, Excluding Balance Extension - 40 - ns
Unloaded, Excluding Balance Extension - 40 - ns
Outputs Unloaded - 25 - ns
Outputs Unloaded - 20 - ns
Outputs Unloaded - 25 - ns
Excluding Propagation Delay (t
PDLU, tPDLL
OUTPUT (Note 3)
Upper Drive Source Resistance R
Upper Drive Sink Resistance R
Lower Drive Source Resistance R
Lower Drive Sink Resistance R
UG_SRC
UG_SNK
LG_SRC
LG_SNK
50mA Source Current - 1.0 - Ω
50mA Sink Current - 1.0 - Ω
50mA Source Current - 1.0 - Ω
50mA Sink Current - 0.4 - Ω
NOTE:
3. Limits established by characterization and are not production tested.
-8.5-kΩ
-10-kΩ
) - 25 - ns
8
FN6881.0
March 19, 2009
Timing Diagram
PWM
t
PDHU
t
PDLU
2.5V
ISL6611A
t
TSSHD
t
RU
UGATE
LGATE
t
PDLL
1V
t
PDHL
1V
t
RL
FIGURE 1. TIMING DIAGRAM
Operation and Adaptive Shoot-Through Protection
Designed for high speed switching, the ISL6611A MOSFET
driver controls two-phase power trains’ high-side and low-side
N-Channel FET s from one externally provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Figure 1). After a short propagation delay
[t
], the lower gate begins to fall. Typical fall times [tFL]
PDLL
are provided in the “Electrical Specifications” on page 8.
Adaptive shoot-through circuitry monitors the LGATE voltage
and turns on the upper gate following a short delay time
[t
] after the LGATE voltage drops below ~1V. The
PDHU
upper gate drive then begins to rise [t
MOSFET turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. The upper
gate begins to fall [t
] after a propagation delay [t
FU
which is modulated by the current balance circuits. The
adaptive shoot-through circuitry monitors the UGATE-PHASE
voltage and turns on the lower MOSFET a short delay time,
t
, after the upper MOSFET’s gate voltage drop s below
PDHL
1V . The l ower gate then rises [t
RL
MOSFET. These methods prevent both the lower and upper
MOSFETs from conducting simultaneously (shoot-through),
while adapting the dead time to the gate charge
characteristics of the MOSFETs being used.
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower
MOSFET conducts for a longer time during a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement. The 0.4Ω
] and the upper
RU
PDLU
], turning on the lower
],
t
RU
t
PTS
t
TSSHD
t
FL
t
FU
t
PTS
ON-resistance and 4A sink current capability enable the
lower gate driver to absorb the current injected into the lower
gate through the drain-to-gate capacitor (C
) of the lower
GD
MOSFET and help prevent shoot through caused by the self
turn-on of the lower MOSFET due to high dV/dt of the
switching node.
Tri-State PWM Input
A unique feature of the ISL6611A is the adaptable tri-state
PWM input. Once the PWM signal enters the shutdown
window, either MOSFET previously conducting is turned off.
If the PWM signal remains within the shutdown window for
longer than 25ns of the previously conducting MOSFET, the
output drivers are disabled and both MOSFET gates are
pulled and held low. The shutdown state is removed when
the PWM signal moves outside the shutdown window. The
PWM Tri-state rising and falling thresholds outlined in the
“Electrical Specifications” on page 8 determine when the
lower and upper gates are enabled. During normal operation
in a typical application, the PWM rise and fall times through
the shutdown window should not exceed either output’s turnoff propagation delay plus the MOSFET gate discharge time
to ~1V . Abnormally long PWM signal transition times through
the shutdown window will simply introduce additional dead
time between turn off and turn on of the synchronous
bridge’s MOSFETs. For optimal performance, no more than
100pF parasitic capacitive load should be present on the
PWM line of ISL6611A (assuming an Intersil PWM controller
is used).
Bootstrap Considerations
This driver features an internal bootstrap diode. Simply
adding an external capacitor across the BOOT and PHASE
9
FN6881.0
March 19, 2009
ISL6611A
pins completes the bootstrap circuit. The ISL6611A’s internal
bootstrap resistor is designed to reduce the overcharging of
the bootstrap capacitor when exposed to excessively large
negative voltage swing at the PHASE node. Typically, such
large negative excursions occur in high current applications
that use D
2
-PAK and D-PAK MOSFETs or excessive layout
parasitic inductance. Equation 1 helps select a proper
bootstrap capacitor size:
Q
GATE
C
BOOT_CAP
Q
GATE
where Q
at V
GS1
control MOSFETs. The ΔV
--------------------------------------
≥
ΔV
BOOT_CAP
QG1PVCC•
----------------------------------- -
V
GS1
is the amount of gate charge per upper MOSFET
G1
•=
N
Q1
gate-source voltage and NQ1 is the number of
BOOT_CAP
term is defined as the
(EQ. 1)
allowable droop in the rail of the upper gate drive.
As an example, suppose two HAT2168 FETs are chosen as
the upper MOSFETs. The gate charge, Q
sheet is 12nC at 5V (V
Q
is calculated to be 26.4nC at 5.5V PVCC level. We
GATE
) gate-source voltage. Then the
GS
, from the data
G
will assume a 100mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.264µF is required. The next larger standard value
capacitance is 0.33µF. A good quality ceramic capacitor is
recommended.
2.0
1.8
1.6
1.4
1.2
(µF)
1.0
0.8
BOOT_CAP
C
0.6
0.4
0.2
20nC
0.0
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
Q
50nC
VOLTAGE
= 100nC
GATE
0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
ΔV
(V)
BOOT
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
), the output drive impedance, the
SW
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the 4x4 QFN package, with an exposed heat escape pad, is
around 2W. See “Layout Considerations” on page 12 for
thermal transfer improvement suggestions. When designing
the driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
desired frequency for the selected MOSFET s. The tot al gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively,
P
Qg_TOT
P
Qg_Q1
P
Qg_Q2
I
DR
2P
QG1PVCC
•
---------------------------------------
V
QG2PVCC
•
---------------------------------------
V
Q
•
⎛⎞
G1NQ1
----------------------------- -
2
• F
⎜⎟
V
⎝⎠
GS1
where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; I
quiescent current with no load at both drive outputs; N
and N
are number of upper and lower MOSFETs,
Q2
+()• IQVCC•+=
Qg_Q1PQg_Q2
2
• NQ1•=
F
GS1
GS2
SW
2
• NQ2•=
F
SW
Q
•
G2NQ2
----------------------------- -
+
V
GS2
G1
+•=
SWIQ
and QG2) is defined at a
and V
GS1
is the driver’s total
Q
GS2
) in the
(EQ. 2)
(EQ. 3)
Q1
respectively. The factor 2 is the number of active channels.
The I
product is the quiescent power of the driver
Q VCC
without capacitive load.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
and RG2, should be a short to avoid
G1
interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R
GI1
and R
GI2
) of
MOSFET s. Figures 3 and 4 show the typical upper and lower
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as Equation 4:
P
2P
DR
P
DR_UP
P
DR_LOW
R
EXT2RG1
⎛⎞
--------------------------------------
⎜⎟
R
⎝⎠
+()• IQVCC•+=
DR_UPPDR_LOW
R
HI1
+
HI1REXT1
R
⎛⎞
HI2
--------------------------------------
⎜⎟
R
+
⎝⎠
HI2REXT2
R
GI1
-------------
+=
N
Q1
R
LO1
----------------------------------------
+
R
+
LO1REXT1
R
LO2
----------------------------------------
+
R
+
LO2REXT2
R
EXT2RG2
P
Qg_Q1
---------------------
•=
P
---------------------
•=
R
-------------
+=
N
(EQ. 4)
2
Qg_Q2
2
GI2
Q2
10
FN6881.0
March 19, 2009
ISL6611A
PVCC
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R
R
LO2
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
HI2
BOOT
D
C
GD
R
HI1
R
LO1
UGATE
PHASE
LGATE
GND
G
R
GI1
R
G1
C
GS
S
D
C
GD
G
R
GI2
R
G2
C
GS
C
DS
Q2
S
EN_PH Operation
EN_PH
PWM
Q1
this channel should remain ON to protect the system from an
overvoltage event even when the controller is disabled.
SYNC Operation
C
DS
The ISL6611A can be set to interleaving mode or
synchronous mode by pulling the SYNC pin to GND or VCC,
respectively. A synchronous pulse can be sent to the phase
doubler during the load application to improve the voltage
droop and current balance while it still can maintain
interleaving operation at DC load conditions. However, an
excessive ringback can occur; hence, the synchronous
mode operation could have drawbacks. Figure 6 shows how
to generate a synchronous pulse only when an transient
load is applied. The comparator should be a fast comparator
with a minimum delay.
49.9kΩ
20kΩ
+
-
2k
Ω
COMP
FIGURE 6. TYPICAL SYNC PULSE GENERATOR
1.0 nF
VCC
0 Ω
1kΩ
SYNC
DNP
Current Balance and Maximum Frequency
The ISL6611A utilizes r
both channels, while the sample and hold circuits refer to
GND pin. The phase current sensing resistors are
integrated, while the current gain can be scaled by the
impedance on the IGAIN pin, as shown in Table 1. In most
applications, the default option should just work fine.
sensing technique to balance
DS(ON)
UGATE
LGATE
FIGURE 5. TYPICAL EN_PH OPERATION TIMING DIAGRAM
The ISL661 1A disables the phase doubl er operation when the
EN_PH pin is pulled to ground and after it sees the PWM
falling edge. The PWM pin is pulled to VCC at the PWM falling
edge. With the PWM line pulled high, the controller wi ll disable
the corresponding phase and the higher number phases.
When the EN_PH is pulled high, the phase doubler will pull
the PWM line to tri-state and then will be enabled at the
leading edge of PWM input. Prior to a leading edge of PWM, if
the PWM is low, both LGATEA and LGATEB remain in tristate unless the corresponding phase node (PHASEA,
PHASEB) is higher than 80% of VCC. This provides additional
protection if the doubler is enabled while the high-side
MOSFET is shorted. However, this feature limit s the
pre-charged output voltage to less than 80% of VCC. Note
that the first doubler should always tie its EN_PH pin high
since Intersil controllers do not allow PWM1 pulled high and
TABLE 1. CURRENT GAIN SELECTION
IMPEDANCE TO GND CURRENT GAIN
OPEN DEFAULT
0Ω DEFAULT/2
49.9kΩ DEFAULT/5
In addition to balancing the effective UGATE pulse width of
phase A and phase B via standard r
current sensing
DS(ON)
technique, a fast path is also added to swap both channels’
firing order when one phase carries much higher current
than the other phase. This improves the current balance
between phase A and phase B during high frequency load
transient events.
Each phase starts to sample current 200ns (t
LGATE falls and lasts for 400ns (t
) or ends at the rising
SAMP
edge of PWM if the available sampling time (t
< 400ns. The available sampling time (t
upon the blanking time (t
), the duty cycle (D), the
BLANK
AVSAMP
rising and falling time of low-side gate drive (t
total propagation delay (t
switching frequency (F
= t
PD
. As the switching frequency and
SW)
PDLL
+ t
PDLU
) after
BLANK
AVSAMP
) depends
, tLF), the
LR
), and the
) is
the duty cycle increase, the available sampling time could be
11
FN6881.0
March 19, 2009
ISL6611A
< 400ns. For a good current balance, it is recommended to
keep at least 200ns sampling time, if not the full 400ns.
Equations 5 and 6 show the maximum frequency of each
channel in interleaving mode and synchronous mode,
respectively. Assume 80ns each for t
each for t
AVSAMP
, t
BLANK
, the maximum channel frequency
, tLR, tLF and 200ns
PD
can be set to no more than 500kHz at interleaving mode and
1MHz at synchronous mode, respectively, for an application
with a maximum duty cycle of 20%. The maximum duty cycle
occurs at the maximum output voltage (overvoltage trip level
as needed) and at the minimum input voltage (undervoltage
trip level as needed). The efficiency of the voltage regulator
is also a factor in the theoretical approximation. Figure 7
shows the relationship between the maximum channel
frequency and the maximum duty cycle in the previous
assumed conditions.
For interleaving mode (SYNC = “0”),
F
MAX()
SW
DMAX()
≈
---------------------------------------------------------------------------------------------------------------
≈
t
AVSAMPtPDtLRtLFtBLANK
VOUT MAX()
-------------------------------------
VIN MIN()η⋅
12DMAX()⋅–
++++()2⋅
(EQ. 5)
For synchronous mode (SYNC = “1”),
MAX()
F
SW
10k
1k
(Hz)
SW
F
100
FIGURE 7. MAXIMUM CHANNEL SWITCHING FREQUENCY
-------------------------------------------------------------------------------------------------------
≈
t
AVSAMPtPDtLRtLFtBLANK
0 20406080100
vs MAXIMUM DUTY CYCLE IN ASSUMED
CONDITIONS
Note that the PWM controller should be set to 2 x F
1DMAX()–
++++()
(EQ. 6)
SYNCHRONOUS
INTERLEAVING
DUTY CYCLE (%)
for
SW
interleaving mode and the same switching frequency for the
synchronous mode.
Application Information
MOSFET and Driver Selection
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding absolute maximum rating
of the devices. The negative ringing at the edges of the
PHASE node could increase the bootstrap capacitor voltage
through the internal bootstrap diode, and in some cases, it
may overstress the upper MOSFET driver. Careful layout,
proper selection of MOSFETs and packaging, as well as the
proper driver can go a long way toward minimizing such
unwanted stress.
PVCC
FIGURE 8. PHASE RESISTOR TO MINIMIZE SERIOUS
NEGATIVE PHASE SPIKE IF NEEDED
The selection of D
a much better match (for the reasons discussed) for the
ISL6611A with a phase resistor (R
Low-profile MOSFET s, such as Direct FETs and multi-source
leads devices (SO-8, LFPAK, PowerPAK), have low parasitic
lead inductances and can be driven by ISL6611A (assuming
proper layout design) without the phase resistor (R
Layout Considerations
A good layout helps reduce the ringing on the switching
node (PHASE) and significantly lower the stress applied to
the output drives. The following advice is meant to lead to an
optimized layout and performance:
• Keep decoupling loops (VCC-GND, PVCC-PGND and
BOOT-PHASE) short and wide, at least 25 mils. Avoid
using vias on decoupling components other than their
ground terminals, which should be on a copper plane with
at least two vias.
• Minimize trace inductance, especially on low-impedance
lines. All power traces (UGATE, PHASE, LGATE, PGND,
PVCC, VCC, GND) should be short and wide, at least
25 mils. Try to place power traces on a single layer,
otherwise, two vias on interconnection are preferred
where possible. For no connection (NC) pins on the QFN
BOOT
D
R
HI1
R
LO1
UGATE
PHASE
2
-PAK, or D-PAK packaged MOSFETs, is
G
R
= 1Ω TO 2Ω
PH
), as shown in Figure 8.
PH
Q1
S
PH
).
12
FN6881.0
March 19, 2009
S
)
ISL6611A
part, connect it to the adjacent net (LGATE2/PHASE2) can
reduce trace inductance.
• Shorten all gate drive loops (UGATE-PHASE and
LGATE-PGND) and route them closely spaced.
• Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
• Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
• Avoid routing relatively high impedance nodes (such as
PWM and ENABLE lines) close to high dV/dt UGATE and
PHASE nodes.
In addition, connecting the thermal pad of the QFN package
to the power ground through multiple vias, or placing a low
noise copper plane (such as power ground) underneath the
SOIC part is recommended. This is to improve heat
dissipation and allow the part to achieve its full thermal
potential.
Upper MOSFET Self Turn-On Effects At Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to the
self-coupling via the internal C
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET . This could potentially turn
on the upper switch and result in damaging in-rush energy.
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is common practice to place
a resistor (R
) across the gate and source of the upper
UGPH
MOSFET to suppress the Miller coupling effect. The value of
the resistor depends mainly on the input voltage’s rate of
rise, the C
GD/CGS
ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
of the MOSFET, the
GD
C
DS/CGS
ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ typically sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with the
equations in Equation 7, which assume a fixed linear input
ramp and neglect the clamping effect of the body diode of
the upper drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purposes only. Thus,
the actual coupling effect should be examined using a very
high impedance (10MΩ or greater) probe to ensure a safe
design margin.
V–
⎛⎞
dV
V
GS_MILLER
RR
UGPHRGI
VCC
ISL6611A
FIGURE 9. GATE TO SOURCE RESISTOR T O REDUCE
-------
⋅⋅=
dt
+=
DU
DL
UPPER MOSFET MILLER COUPLING
⎜⎟
⎜⎟
1e
RC
–
rss
⎜⎟
⎜⎟
⎝⎠
C
=
rssCGD
BOOT
C
BOOT
UGATE
UGPH
R
PHASE
DS
--------------------------------- -
dV
-------
RC⋅
⋅
dt
C
GD
G
R
GI
iss
C
issCGDCG
VIN
C
GS
Q
S
(EQ. 7
+=
D
C
UPPER
DS
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6881.0
March 19, 2009
Package Outline Drawing
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 02/08
4.00
6
PIN 1
INDEX AREA
ISL6611A
A
B
4X 1.95
0.65
12X
13
12
16
6
PIN #1 INDEX AREA
1
(4X)
( 3 . 6 TYP )
0.15
( 2 . 10 )
TOP VIEW
4.00
16X 0 . 60
( 16X 0 . 28 )
( 16 X 0 . 8 )
+0.15
-0.10
1.00 MAX
( 12X 0 . 65 )
2 . 10 ± 0 . 15
9
8
BOTTOM VIEW
SIDE VIEW
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
5
5
0.10 CM
4
0.28 +0.07 / -0.05
4
A B
SEE DETAIL "X"
0.10
BASE PLANE
SEATING PLANE
C
C
0.08 C
TYPICAL RECOMMENDED LAND PATTERN
14
DETAIL "X"
NOTES:
Dimensions are in millimeters.1.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
2.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
Dimension b applies to the metallized terminal and is measured
4.
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
The configuration of the pin #1 identifier is optional, but must be
6.
located within the zone indicated. The pin #1 identifier ma y be
either a mold or mark feature.
FN6881.0
March 19, 2009
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