intersil ISL6611A DATA SHEET

ISL6611A

Data Sheet March 19, 2009 FN6881.0

Phase Doubler with Integrated Drivers and Phase Shedding Function

The ISL6611A utilizes Intersil’s proprietary Phase Doubler scheme to modulate two-phase power trains with single PWM input. It doubles the number of phases that Intersil’s ISL63xx multiphase controllers can support. At the same time, the PWM line can be pulled high to disable the corresponding phase or higher phase(s) when the enable pin (EN_PH) is pulled low. This simplifies the phase shedding implementation. For layout simplicity and improving system performance, the device integrates two 5V drivers (ISL6609) and current balance function.

The ISL6611A is designed to minimize the number of analog signals interfacing between the controller and drivers in high phase count and scalable applications. The common COMP signal, which is usually seen with conventional cascaded configuration, is not required; this improves noise immunity and simplifies the layout. Furthermore, the ISL6611A provides low part count and a low cost advantage over the conventional cascaded technique.

The IC is biased by a single low voltage supply (5V), minimizing driver switching losses in high MOSFET gate capacitance and high switching frequency applications. Bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously.

The ISL6611A features 4A typical sink current for the lower gate driver, enhancing the lower MOSFET gate hold-down capability during PHASE node rising edge, preventing power loss caused by the self turn-on of the lower MOSFET due to the high dV/dt of the switching node.

The ISL6611A also features an input that recognizes a high-impedance state, working together with Intersil multiphase PWM controllers to prevent negative transients on the controlled output voltage when operation is suspended. This feature eliminates the need for the Schottky diode that may be utilized in a power system to protect the load from negative output voltage damage.

Features

• Proprietary Phase Doubler Scheme with Phase Shedding Function (Patent Pending)

- Enhanced Light to Full Load Efficiency

• Patented Current Balancing with r and Adjustable Gain

• Quad MOSFET Drives for Two Synchronous Rectified Bridge with Single PWM Input

• Channel Synchronization and Interleaving Options

• Adaptive Zero Shoot-Through Protection

•0.4Ω On-Resistance and 4A Sink Current Capability

• 36V Internal Bootstrap Schottky Diode

• Bootstrap Capacitor Overcharging Prevention (ISL6611A)

• Supports High Switching Frequency (Up to 1MHz)

- Fast Output Rise and Fall

• Tri-State PWM Input for Output Stage Shutdown

• Phase Enable Input and PWM Forced High Output to Interface with Intersil’s Controller for Phase Shedding

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat

No Leads-Product Outline

- Near Chip-Scale Package Footprint; Improves PCB

Utilization, Thinner Profile

- Pb-Free (RoHS Compliant)

Current Sensing

DS(ON)

Applications

• High Current Low Voltage DC/DC Converters

• High Frequency and High Efficiency VRM and VRD

• High Phase Count and Phase Shedding Applications

Related Literature

• Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”

In addition, the ISL6611A’s bootstrap function is designed to prevent the BOOT capacitor from overcharging, should excessively large negative swings occur at the transitions of the PHASE node.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6611A

Ordering Information

PART

NUMBER

(Note)

PART

MARKING

ISL6611ACRZ* 66 11ACRZ 0 to +70 16 Ld 4x4 QFN L16.4x4 ISL6611AIRZ* 66 11AIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

TEMP.

RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

Pinout

ISL6611A

(16 LD QFN)

TOP VIEW

SYNC

PWM1

VCC

PHASEA

16 14 13

GND

LGATEA

PVCC

IGAIN

GND

6578

PGND

LGATEB

EN_PH

PHASEB

UGATEA

BOOTA

BOOTB

UGATEB

FN6881.0

March 19, 2009

Block Diagram

VCC

PVCC

ISL6611A

BOOT

BOOTA

UGATEA

PWM

EN_PH

SYNC

IGAIN

4.9k

CURRENT

BALANCE BLOCK

PHASEA

PHASEB

4.6k

PROTECTION

CONTROL

LOGIC

GND

INTEGRATED 3Ω RESISTOR (R

PAD

PVCC

PROTECTION

MUST BE SOLDERED TO THE CIRCUIT’S GROUND

SHOOT-

THROUGH

PGND

SHOOT-

THROUGH

PGND

BOOT

) IN ISL6611A

BOOT

PVCC

PHASEA

LGATEA

PGND

BOOTB

UGATEB

PHASEB

PVCC

LGATEB

CHANNEL A

CHANNEL B

FN6881.0

March 19, 2009

Functional Pin Descriptions

ISL6611A

PACKAGE

PIN #

1 GND Bias and reference ground. All signals are referenced to this node. It is also the return of the sample and hold of the

2 LGATEA Lower gate drive output of Channel A. Connect to gate of the low-side power N-Channel MOSFET. 3 PVCC This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from

4 IGAIN A resistor from this pin to GND sets the current balance gain. See “Current Balance and Maximum Frequency” on

5 PGND Power ground return of both low gate drivers. It is also the return of the phase node clamp circuits. 6 LGATEB Lower gate drive output of Channel B. Connect to gate of the low-side power N-Channel MOSFET. 7 EN_PH Driver Enable Input. A signal high input enables the driver at the PWM rising edge, a signal low input pulls PWM pin to

8 PHASEB Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel B. This pin

9 UGATEB Upper gate drive output of Channel B. Connect to gate of high-side power N-Channel MOSFET.

10 BOOTB Floating bootstrap supply pin for the upper gate drive of Channel B. Connect the bootstrap capacitor between this pin

11 BOOTA Floating bootstrap supply pin for the upper gate drive of Channel A. Connect the bootstrap capacitor between this pin

12 UGATEA Upper gate drive output of Channel A. Connect to gate of high-side power N-Channel MOSFET. 13 PHASEA Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel A. This pin

14 VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic

15 PWM The PWM input signal triggers the J-K flip flop and alternates its input to channel A and B. Both channels are effectively

16 SYNC A signal high synchronizes both channels with no phase shifted. A signal low interleaves both channels with 180°

17 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.

SYMBOL FUNCTION

current sensing circuits. Place a high quality low ESR ceramic capacitor from this pin to VCC.

DS(ON)

this pin to PGND.

page 11 for more details.

VCC at the PWM falling edge and then enters tri-state.

provides a return path for the upper gate drive.

and the PHASEB pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See“Bootstrap Considerations” on page 9 for guidance in choosing the capacitor value.

and the PHASEA pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Bootstrap Considerations” on page 9 for guidance in choosing the capacitor value.

provides a return path for the upper gate drive.

capacitor from this pin to GND.

modulated. The PWM signal can enter three distinct states during operation, see “Tri-State PWM Input” on page 9 for further details. Connect this pin to the PWM output of the controller. The pin is pulled to VCC when EN_PH is low and the PWM input starts transitioning low.

out-of-phase.

FN6881.0

March 19, 2009

ISL6611A

Typical Application I (2-Phase Controller for 4-Phase Operation)

+5V

SYNC

COMP

VCC AND PVCC

EN_PH SYNC

BOOTA

UGATEA PHASEA

LGATEA

+12V

VR_RDY

VID

VSEN V

MAIN

CONTROL

ISL63xx

PWM1

ISEN1-

ISEN1+

PWM2

EN_PH

ISL6611A

PWM

IGAIN

GND AND PGND

+5V

VCC AND PVCC

EN_PH SYNC

ISL6611A

PWM

BOOTB

UGATEB PHASEB

LGATEB

BOOTA

UGATEA PHASEA

LGATEA

BOOTB

UGATEB PHASEB

+12V

CORE

GND

ISEN2-

ISEN2+

IGAIN

GND AND PGND

LGATEB

FN6881.0

March 19, 2009

+ 9 hidden pages