®
ISL6610, ISL6610A
Data Sheet November 22, 2006
Dual Synchronous Rectified MOSFET
Drivers
The ISL6610, ISL6610A integrates two ISL6609, ISL6609A
drivers with enable function removed and is optimized to
drive two independent power channels in a synchronousrectified buck converter topology. These drivers, combined
with an Intersil ISL63xx or ISL65xx multiphase PWM
controller, form a complete high efficiency voltage regulator
at high switching frequency.
The IC is biased by a single low voltage supply (5V),
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications.
Each driver is capable of driving a 3nF load with less than
10ns rise/fall time. Bootstrapping of the upper gate driver is
implemented via an internal low forward drop diode,
reducing implementation cost, complexity, and allowing the
use of higher performance, cost effective N-Channel
MOSFETs. Adaptive shoot-through protection is integrated
to prevent both MOSFETs from conducting simultaneously.
The ISL6610, ISL6610A features 4A typical sink current for
the lower gate driver, enhancing the lower MOSFET gate
hold-down capability during PHASE node rising edge,
preventing power loss caused by the self turn-on of the lower
MOSFET due to the high dV/dt of the switching node.
The ISL6610, ISL6610A also features an input that
recognizes a high-impedance state, working together with
Intersil multiphase PWM controllers to prevent negative
transients on the controlled output voltage when operation is
suspended. This feature eliminates the need for the schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
In addition, the ISL6610As bootstrap function is designed to
prevent the BOOT capacitor from overcharging, should
excessively large negative swings occur at the transitions of
the PHASE node.
Applications
• Core Voltage Supplies for Intel® and AMD®
Microprocessors
• High Frequency Low Profile High Efficiency DC/DC
Converters
• High Current Low Voltage DC/DC Converters
• Synchronous Rectification for Isolated Power Supplies
FN6395.0
Features
• 5V Quad N-Channel MOSFET Drives for Two
Synchronous Rectified Bridges
• Pin-to-pin Compatible with ISL6614 (12V Drive)
• Adaptive Shoot-Through Protection
•0.4Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast Output Rise and Fall
- Low Tri-State Hold-Off Time
• BOOT Capacitor Overcharge Prevention (ISL6610A)
•Low V
• Power-On Reset
• QFN Package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Internal Bootstrap Diode
F
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline
- Near Chip-Scale Package Footprint; Improves PCB
Utilization, Thinner Profile
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Ordering Information
PART
NUMBER
(Note)
ISL6610CBZ 6610CBZ 0 to +70 14 Ld SOIC M14.15
ISL6610CRZ 66 10CRZ 0 to +70 16 Ld 4x4 QFN L16.4x4
ISL6610IBZ 6610IBZ -40 to +85 14 Ld SOIC M14.15
ISL6610IRZ 66 10IRZ -40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6610ACBZ 6610ACBZ 0 to +70 14 Ld SOIC M14.15
ISL6610ACRZ 66 10ACRZ 0 to +70 16 Ld 4x4 QFN L16.4x4
ISL6610AIBZ 6610AIBZ -40 to +85 14 Ld SOIC M14.15
ISL6610AIRZ 66 10AIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
1
AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
Pinouts
ISL6610, ISL6610A
(14 LD SOIC)
TOP VIEW
ISL6610, ISL6610A
ISL6610, ISL6610A
(16 LD QFN)
TOP VIEW
PWM1
PWM2
GND
LGATE1
PVCC
PGND
LGATE2
Block Diagram
VCC
PWM1
1
1
2
2
3
4
5
6
14
13
12
11
10
9
87
VCC
PHASE1
UGATE1
BOOT1
BOOT2
UGATE2
PHASE2
GND
LGATE1
PVCC
PGND
PWM2
PWM1
15
16 14 13
1
2
3
4
GND
6578
NC1
LGATE2
17
VCC
PHASE1
NC2
PHASE2
12
11
10
9
UGATE1
BOOT1
BOOT2
UGATE2
ISL6610, ISL6610A
R
SHOOT-
BOOT
PVCC
BOOT1
UGATE1
PHASE1
CHANNEL 1
PVCC
4.9K
THROUGH
PROTECTION
PWM2
GND
VCC
4.6K
4.9K
4.6K
CONTROL
LOGIC
INTEGRATED 3Ω RESISTOR (R
PVCC
PAD
2
LGATE1
PGND
SHOOT-
THROUGH
PROTECTION
PGND
R
BOOT
PGND
BOOT2
UGATE2
PHASE2
PVCC
LGATE2
CHANNEL 2
FOR ISL6610CR/10ACR, THE PAD ON THE BOTTOM SIDE OF
THE QFN PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
) AVAILABLE ONLY IN ISL6610A
BOOT
FN6395.0
November 22, 2006
ISL6610, ISL6610A
Typical Application - Multiphase Converter Using ISL6610 Gate Drivers
PGOOD
EN
VID
FB
VSEN
FS/DIS
COMP
MAIN
CONTROL
ISL65xx
GND
V
CC
ISEN1
PWM1
PWM2
ISEN2
ISEN3
PWM3
PWM4
ISEN4
+5V
+5V
VCC
PWM1
PWM2
+5V
VCC
DUAL
DRIVER
ISL6610
BOOT1
UGATE1
PHASE1
LGATE1
PVCC
BOOT2
UGATE2
PHASE2
NC2
LGATE2
NC1
PGNDGND
BOOT1
UGATE1
PHASE1
+5V
+12V
+12V
+12V
+V
CORE
LGATE1
DUAL
DRIVER
ISL6610
PWM1
PWM2
PVCC
+5V
BOOT2
UGATE2
PHASE2
LGATE2
PGNDGND
3
+12V
FN6395.0
November 22, 2006
ISL6610, ISL6610A
Absolute Maximum Ratings Thermal Information
Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (V
BOOT Voltage (V
BOOT To PHASE Voltage (V
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC)
UGATE Voltage . . . . . . . . . . . . . . . . V
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
HBM ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
+150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Constantly operated at 150°C may shorten the life of the part.
NOTES:
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
1. θ
JA
2. θ
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
JA
, “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
3. θ
JC
, V
EN
BOOT-GND
GND -8V (<20ns Pulse Width, 10μJ) to 30V (<100ns)
V
GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V
) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
PWM
). . . -0.3V to 25V (DC) or 36V (<200ns)
BOOT-PHASE
- 5V (<20ns Pulse Width, 10μJ) to V
PHASE
). . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
- 0.3V (DC) to V
PHASE
BOOT
BOOT
Thermal Resistance (Typical) θ
SOIC Package (Note 1) . . . . . . . . . . . . 90 N/A
QFN Package (Notes 2 and 3). . . . . . . 46 8.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
(°C/W) θJC(°C/W)
JA
Electrical Specifications These specifications apply for T
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
SUPPLY CURRENT
Bias Supply Current I
BOOTSTRAP DIODE
Forward Voltage V
POWER-ON RESET
POR Rising -3.44.2V
POR Falling 2.6 3.0 - V
Hysteresis - 400 - mV
PWM INPUT
Sinking Impedance R
Source Impedance R
Tri-State Rising Threshold V
Tri-State Falling Threshold V
Tri-State Shutdown Holdoff Time t
SWITCHING TIME (Note 4, See Figure 1)
UGATE Rise Time t
LGATE Rise Time t
UGATE Fall Time t
LGATE Fall Time t
UGATE Turn-Off Propagation Delay t
LGATE Turn-Off Propagation Delay t
VCC+PVCC
F
PWM_SNK
PWM_SRC
TSSHD
RU
RL
FU
FL
PDLU
PDLL
= -40°C to +85°C, unless otherwise noted
A
PWM pin floating, V
= 300kHz, V
F
PWM
Forward bias current = 2mA
= 0°C to +70°C
T
A
Forward bias current = 2mA
T
= -40°C to +85°C
A
= V
VCC
= V
VCC
3nF Load - 8.0 - ns
3nF Load - 8.0 - ns
3nF Load - 8.0 - ns
3nF Load - 4.0 - ns
Outputs Unloaded - 18 - ns
Outputs Unloaded - 25 - ns
= 5V (250mV Hysteresis) 1.00 1.20 1.40 V
PVCC
= 5V(300mV Hysteresis) 3.10 3.41 3.70 V
PVCC
VCC
VCC
= V
= V
= 5V - 240 - μA
PVCC
= 5V - 1.6 - mA
PVCC
0.30 0.60 0.70 V
0.30 0.60 0.75 V
-4.6-kΩ
-4.9-kΩ
-80-ns
4
FN6395.0
November 22, 2006