intersil ISL6594D DATA SHEET

®

www.BDTIC.com/Intersil

ISL6594D

Data Sheet December 3, 2007

Advanced Synchronous Rectified Buck
MOSFET Drivers with Protection Features

The ISL6594D is high frequency MOSFET driver specifically
designed to drive upper and lower power N-Channel
MOSFETs in a synchronous rectified buck converter
topology. This driver combined with the ISL6594D Digital
Multi-Phase Buck PWM controller and N-Channel MOSFET s
forms a complete core-voltage regulator solution for
advanced microprocessors.

The ISL6594D drives both upper and lower gates over a range
of 4.5V to 13.2V. This drive-voltage provides the flexibility
necessary to optimize applications involving trade-offs between
gate charge and conduction losses.

An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. The ISL6594D includes an overvoltage protection
feature operational before VCC exceeds its turn-on
threshold, at which the PHASE node is connected to the
gate of the low side MOSFET (LGATE). The output voltage
of the converter is then limited by the threshold of the low
side MOSFET, which provides some protection to the
microprocessor if the upper MOSFET(s) is shorted.

The ISL6594D also features an input that recognizes a
high-impedance state, working together with Intersil multi­phase PWM controllers to prevent negative transients on the
controlled output voltage when operation is suspended. This
feature eliminates the need for the Schottky diode that may
be utilized in a power system to protect the load from
negative output voltage damage.

Ordering Information

PART NUMBER

(Note)

ISL6594DCBZ 6594 DCBZ 0 to +85 8 Ld SOIC M8.15
ISL6594DCBZ-T* 6594 DCBZ 0 to +85 8 Ld SOIC

ISL6594DCRZ 94DZ 0 to +85 10 Ld 3x3 DFN L10.3x3
ISL6594DCRZ-T* 94DZ 0 to +85 10 Ld 3x3 DFN

*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ

special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

TEMP.

RANGE (°C)

PA CKAGE

(Pb-free)

Tape and Reel

Tape and Reel

PKG.

DWG. #

M8.15

L10.3x3

FN9282.1

Features

• Dual MOSFET Drives for Synchronous Rectified Bridge

• Pin-to-pin Compatible with ISL6596

• Advanced Adaptive Zero Shoot-Through Protection

- Body Diode Detection

- Auto-zero of r

• Adjustable Gate Voltage for Optimal Efficiency

• 36V Internal Bootstrap Schottky Diode

• Bootstrap Capacitor Overcharging Prevention

• Supports High Switching Frequency (up to 2MHz)

- 3A Sinking Current Capability

- Fast Rise/Fall Times and Low Propagation Delays

• Optimized for 3.3V PWM Input

• Three-State PWM Input for Output Stage Shutdown

• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement

• Pre-POR Overvoltage Protection

• VCC Undervoltage Protection

• Expandable Bottom Copper Pad for Enhanced Heat
Sinking

• Dual Flat No-Lead (DFN) Package

- Near Chip-Scale Package Footprint; Improves PCB

Efficiency and Thinner in Profile

• Pb-Free (RoHS Compliant)

Conduction Offset Effect

DS(ON)

Applications

• Optimized for POL DC/DC Converters for IBA Systems

• Core Regulators for Intel® and AMD® Microprocessors

• High Current DC/DC Converters

• High Frequency and High Efficiency VRM and VRD

Related Literature

Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved

ISL6594D

www.BDTIC.com/Intersil

Pinouts

UGATE

BOOT

PWM

GND

Block Diagram

ISL6594DCB

(8 LD SOIC)

TOP VIEW

1
2
3
4

VCC

PWM

+5V

13.6k

6.4k

8

PHASE

7

PVCC
VCC

6

LGATE

5

UVCC

Pre-POR OVP

FEATURES

POR/

CONTROL

LOGIC

ISL6594D

SHOOT-

THROUGH

PROTECTION

UGATE

(LVCC)

BOOT

N/C

PWM

GND

ISL6594DCR

(10 LD 3x3 DFN)

TOP VIEW

1
2

GND

3
4
5

BOOT

UGATE

PHASE

PVCC

UVCC = PVCC FOR ISL6594D

LGATE

10

9
8
7
6

PHASE
PVCC

N/C
VCC

LGATE

PAD

GND

FOR DFN DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.

2

FN9282.1

December 3, 2007

Typical Application - 4 Channel Converter Using ISL6592 and ISL6594D Gate Drivers

www.BDTIC.com/Intersil

+12V

+5V

3

+3.3V

VDD

ISL6592

VID4
VID3
VID2
VID1

FROM µP

TO µP

FAULT

OUTPUTS

2

C I/F

December 3, 2007

FN9282.1

I

BUS

VID0
VID5
LL0
LL1
OUTEN

VCC_PWRGD

RESET_N

FAULT1

FAULT2

SDA

SCL
SADDR

V12_SEN

GND

OUT1

OUT2

ISEN1

OUT3
OUT4

ISEN2

OUT5

OUT6

ISEN3

OUT7

OUT8

ISEN4

OUT9

OUT10

ISEN5

ISEN5

OUT11

OUT12

ISEN6

TEMP_SEN

CAL_CUR_EN

CAL_CUR_SEN

VSENP
VSENN

1

UGATE

2

BOOT

3

PWM

4

GND

1

UGATE

2

BOOT

3

PWM

4

GND

1

UGATE

2

BOOT

3

PWM

4

GND

1

UGATE

2

BOOT

3

PWM

4

GND

ISL6594D

PHASE

PVCC

LGATE

ISL6594D

PHASE

PVCC

LGATE

ISL6594D

PHASE

PVCC

LGATE

ISL6594D

PHASE

PVCC

LGATE

VCC

VCC

VCC

VCC

8

7

6

5

8

7

6

5

ISL6594D

Vout

8

7

6

5

RTN

8

7

6

5

RTHERM

ISL6594D

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V

BOOT Voltage (V
Input Voltage (V

UGATE. . . . . . . . . . . . . . . . . . . V

V

BOOT-GND

PWM

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

LGATE. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V

GND - 5V (<100ns Pulse Width, 2µJ) to V

PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V

GND - 8V (<400ns, 20µJ) to 30V (<200ns, V

ESD Rating

). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V

) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V

PHASE

- 0.3VDC to V

to V

DC

BOOT-GND

BOOT
BOOT
PVCC
PVCC

to 15V

DC

+ 0.3V
+ 0.3V
+ 0.3V
+ 0.3V

DC

<36V))

Human Body Model . . . . . . . . . . . . . . . . . . . .Class I JEDEC STD

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

Thermal Resistance θ

SOIC Package (Note 1) . . . . . . . . . . . . 100 N/A

DFN Package (Notes 2, 3). . . . . . . . . . 48 7

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +85°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C

Supply Voltage, V

Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%

. . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V

CC

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air.

1. θ

JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

2. θ

JA

Tech Brief TB379.

3. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Bias Supply Current I

Gate Drive Bias Current I

VCC

I

VCC

PVCC

I

PVCC

POWER-ON RESET AND ENABLE

VCC Rising Threshold 6.1 6.4 6.7 V
VCC Falling Threshold 4.7 5.0 5.3 V

PWM INPUT (See Timing Diagram on page 6)

Input Current I

PWM

PWM Rising Threshold (Note 4) V
PWM Falling Threshold (Note 4) V
Typical Three-State Shutdown Window V
Three-State Lower Gate Falling Threshold V
Three-State Lower Gate Rising Threshold V
Three-State Upper Gate Rising Threshold V
Three-State Upper Gate Falling Threshold V
Shutdown Hold-off Time t
UGATE Rise Time (Note 4) t
LGATE Rise Time (Note 4) t
UGATE Fall Time (Note 4) t
LGATE Fall Time (Note 4) t
UGATE Turn-On Propagation Delay (Note 4) t

TSSHD

RU
RL
FU

FL

PDHU

ISL6594D, f
ISL6594D, f
ISL6594D, f

ISL6594D, f

V

= 3.3V - 400 - µA

PWM

V

= 0V - -350 - µA

PWM

= 12V - 1.70 - V

CC

= 12V - 1.30 - V

CC

= 12V 1.23 - 1.82 V

CC

= 12V - 1.18 - V

CC

= 12V - 0.76 - V

CC

= 12V - 2.36 - V

CC

= 12V - 1.96 - V

CC

V

= 12V, 3nF Load, 10% to 90% - 26 - ns

PVCC

V

= 12V, 3nF Load, 10% to 90% - 18 - ns

PVCC

V

= 12V, 3nF Load, 90% to 10% - 18 - ns

PVCC

V

= 12V, 3nF Load, 90% to 10% - 12 - ns

PVCC

V

= 12V, 3nF Load, Adaptive - 10 - ns

PVCC

= 300kHz, V

PWM

= 1MHz, V

PWM

= 300kHz, V

PWM

= 1MHz, V

PWM

= 12V - 4.5 - mA

VCC

= 12V - 5 - mA

VCC

= 12V - 7.5 - mA

PVCC

= 12V - 8.5 - mA

PVCC

- 245 - ns

(°C/W) θJC (°C/W)

JA

4

FN9282.1

December 3, 2007