®
www.BDTIC.com/Intersil
ISL6594A, ISL6594B
Data Sheet December 3, 2007
Advanced Synchronous Rectified Buck
MOSFET Drivers with Protection Features
The ISL6594A and ISL6594B are high frequency MOSFET
drivers specifically designed to drive upper and lower power
N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with the
ISL6592 Digital Multi-Phase Buck PWM controller and
N-Channel MOSFETs form a complete core-voltage
regulator solution for advanced microprocessors.
The ISL6594A drives the upper gate to 12V, while the lower
gate can be independently driven over a range from 5V to
12V. The ISL6594B drives both upper and lower gates over
a range of 5V to 12V. This drive-voltage provides the
flexibility necessary to optimize applications involving
trade-offs between gate charge and conduction losses.
An adaptive zero shoot-through protection is integrated to
prevent both the upper and lower MOSFETs from conducting
simultaneously and to minimize the dead time. These
products add an overvoltage protection feature operational
before VCC exceeds its turn-on threshold, at which the
PHASE node is connected to the gate of the low side
MOSFET (LGATE). The output voltage of the converter is
then limited by the threshold of the low side MOSFET , which
provides some protection to the microprocessor if the upper
MOSFET(s) is shorted during initial start-up.
These drivers also feature a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
FN9157.5
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications with
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free Available (RoHS Compliant)
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 for Power Train Design, Layout
Guidelines, and Feedback Compensation Design
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6594A, ISL6594B
www.BDTIC.com/Intersil
Ordering Information
PART
NUMBER
ISL6594ACB* ISL65 94ACB 0 to +85 8 Ld SOIC M8.15
ISL6594ACBZ* (Note) 6594 ACBZ 0 to +85 8 Ld SOIC (Pb-free) M8.15
ISL6594ACR* 94AC 0 to +85 10 Ld 3x3 DFN L10.3x3
ISL6594ACRZ* (Note) 94AZ 0 to +85 10 Ld 3x3 DFN (Pb-free) L10.3x3
ISL6594BCB* ISL65 94BCB 0 to +85 8 Ld SOIC M8.15
ISL6594BCBZ* (Note) 6594 BCBZ 0 to +85 8 Ld SOIC (Pb-free) M8.15
ISL6594BCR* 94BC 0 to +85 10 Ld 3x3 DFN L10.3x3
ISL6594BCRZ* (Note) 94BZ 0 to +85 10 Ld 3x3 DFN (Pb-free) L10.3x3
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
PART
MARKING
TEMP.
RANGE (°C) PA CKAGE
PKG.
DWG. #
Pinouts
ISL6594ACB, ISL6594BCB
UGATE
BOOT
PWM
GND
Block Diagram
(8 LD SOIC)
TOP VIEW
1
2
3
4
VCC
PWM
+5V
13.6k
6.4k
8
PHASE
7
PVCC
VCC
6
LGATE
5
UVCC
PRE-POR OVP
FEATURES
POR/
CONTROL
LOGIC
ISL6594A AND ISL6594B
SHOOT-
THROUGH
PROTECTION
ISL6594ACR, ISL6594BCR
(10 LD 3x3 DFN)
TOP VIEW
UGATE
(LVCC)
BOOT
N/C
PWM
GND
1
2
3
4
5
BOOT
UGATE
PHASE
PVCC
LGATE
PHASE
10
PVCC
9
N/C
8
7
VCC
LGATE
6
UVCC = VCC FOR ISL6594A
UVCC = PVCC FOR ISL6594B
PAD
FOR DFN -DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
2
GND
FN9157.5
December 3, 2007
Typical Application - 4-Channel Converter Using ISL6592 and ISL6594A Gate Drivers
www.BDTIC.com/Intersil
+12V
+5V
3
+3.3V
VDD
ISL6592
VID4
VID3
VID2
VID1
FROM µP
TO µP
FAULT
OUTPUTS
2
C I/F
December 3, 2007
FN9157.5
I
BUS
VID0
VID5
LL0
LL1
OUTEN
VCC_PWRGD
RESET_N
FAULT1
FAULT2
SDA
SCL
SADDR
V12_SEN
GND
OUT1
OUT2
ISEN1
OUT3
OUT4
ISEN2
OUT5
OUT6
ISEN3
OUT7
OUT8
ISEN4
OUT9
OUT10
ISEN5
ISEN5
OUT11
OUT12
ISEN6
TEMP_SEN
CAL_CUR_EN
CAL_CUR_SEN
VSENP
VSENN
1
UGATE
2
BOOT
3
PWM
4
GND
1
UGATE
2
BOOT
3
PWM
4
GND
1
UGATE
2
BOOT
3
PWM
4
GND
1
UGATE
2
BOOT
3
PWM
4
GND
ISL6594
PHASE
LGATE
ISL6594
PHASE
LGATE
ISL6594
PHASE
LGATE
ISL6594
PHASE
LGATE
PVCC
VCC
PVCC
VCC
PVCC
VCC
PVCC
VCC
8
7
6
5
8
7
6
5
VOUT
8
7
6
5
RTN
8
7
6
5
RTHERM
ISL6594A, ISL6594B
ISL6594A, ISL6594B
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (V
Input Voltage (V
UGATE. . . . . . . . . . . . . . . . . . . V
V
PHASE
LGATE. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to V
PHASE. . . . . . . . . . . . . . . GND - 0.3V
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
BOOT
) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V
PWM
- 3.5V (<100ns Pulse Width, 2µJ) to V
PHASE
- 0.3VDC to V
DC
to 15VDC (V
DC
to V
BOOT
BOOT
PVCC
PVCC
PVCC
+ 0.3V
+ 0.3V
+ 0.3V
+ 0.3V
= 12V)
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT - GND < 36V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . .Class I JEDEC STD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Thermal Resistance θ
SOIC Package (Note 1) . . . . . . . . . . . . 100 N/A
DFN Package (Notes 2, 3). . . . . . . . . . 48 7
Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, V
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V ±10%
CC
NOTES:
is measured with the component mounted on a high effective thermal conductivity test board in free air.
1. θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
2. θ
JA
Tech Brief TB379.
3. For θ
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Bias Supply Current I
Gate Drive Bias Current I
VCC
I
VCC
PVCC
I
PVCC
(Note 4)
POWER-ON RESET AND ENABLE
VCC Rising Threshold 9.35 9.8 10.0 V
VCC Falling Threshold 7.35 7.6 8.0 V
PWM INPUT (See Timing Diagram on page 6)
Input Current I
PWM
PWM Rising Threshold (Note 4) V
PWM Falling Threshold (Note 4) V
Typical Three-State Shutdown Window V
Three-State Lower Gate Falling Threshold V
Three-State Lower Gate Rising Threshold V
Three-State Upper Gate Rising Threshold V
Three-State Upper Gate Falling Threshold V
Shutdown Hold-off Time t
UGATE Rise Time t
TSSHD
RU
ISL6594A, f
ISL6594B, f
ISL6594A, f
ISL6594B, f
ISL6594A, f
ISL6594B, f
ISL6594A, f
ISL6594B, f
V
= 3.3V - 505 - µ A
PWM
= 0V - -460 - µA
V
PWM
= 12V - 1.70 - V
CC
= 12V - 1.30 - V
CC
= 12V 1.23 - 1.82 V
CC
= 12V - 1.18 - V
CC
= 12V - 0.76 - V
CC
= 12V - 2.36 - V
CC
= 12V - 1.96 - V
CC
= 300kHz, V
PWM
= 300kHz, V
PWM
= 1MHz, V
PWM
= 1MHz, V
PWM
= 300kHz, V
PWM
= 300kHz, V
PWM
= 1MHz, V
PWM
= 1MHz, V
PWM
= 12V - 8 - mA
VCC
= 12V - 4.5 - mA
VCC
= 12V - 10.5 - mA
VCC
= 12V - 5 - mA
VCC
= 12V - 4 - mA
PVCC
= 12V - 7.5 - mA
PVCC
= 12V - 5 - mA
PVCC
= 12V - 8.5 - mA
PVCC
- 245 - ns
V
= 12V, 3nF Load, 10% to 90% - 26 - ns
PVCC
(°C/W) θJC (°C/W)
JA
4
FN9157.5
December 3, 2007
ISL6594A, ISL6594B
www.BDTIC.com/Intersil
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
LGATE Rise Time t
UGATE Fall Time (Note 4) t
LGATE Fall Time (Note 4) t
UGATE Turn-On Propagation Delay (Note 4) t
LGATE Turn-On Propagation Delay (Note 4) t
UGATE Turn-Off Propagation Delay (Note 4) t
LGATE Turn-Off Propagation Delay (Note 4) t
LG/UG Three-State Propagation Delay (Note 4) t
OUTPUT
Upper Drive Source Current (Note 4) I
Upper Drive Source Impedance R
Upper Drive Sink Current (Note 4) I
Upper Drive Sink Impedance R
Lower Drive Source Current (Note 4) I
Lower Drive Source Impedance R
Lower Drive Sink Current (Note 4) I
Lower Drive Sink Impedance R
NOTE:
4. Limits should be considered typical and are not production tested.
RL
FU
FL
PDHU
PDHL
PDLU
PDLL
PDTS
U_SOURCEVPVCC
U_SOURCE
U_SINK
U_SINK
L_SOURCEVPVCC
L_SOURCE
L_SINK
L_SINK
V
= 12V, 3nF Load, 10% to 90% - 18 - ns
PVCC
V
= 12V, 3nF Load, 90% to 10% - 18 - ns
PVCC
V
= 12V, 3nF Load, 90% to 10% - 12 - ns
PVCC
V
= 12V, 3nF Load, Adaptive - 10 - ns
PVCC
V
= 12V, 3nF Load, Adaptive - 10 - ns
PVCC
V
= 12V, 3nF Load - 10 - ns
PVCC
V
= 12V, 3nF Load - 10 - ns
PVCC
V
= 12V, 3nF Load - 10 - ns
PVCC
= 12V, 3nF Load - 1.25 - A
150mA Source Current 1.4 2.0 3.0 Ω
V
= 12V, 3nF Load - 2 - A
PVCC
150mA Sink Current 0.9 1.65 3.0 Ω
= 12V, 3nF Load - 2 - A
150mA Source Current 0.85 1.3 2.2 Ω
V
= 12V, 3nF Load - 3 - A
PVCC
150mA Sink Current 0.60 0.94 1.35 Ω
Functional Pin Description
PACKAGE PIN #
1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
- 3, 8 N/C No Connection.
3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 VCC Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
7 9 PVCC This pin supplies power to both upper and lower gate drives in ISL6594B; only the lower gate drive in ISL6594A.
8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET . This pin provides
9 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
PIN
SYMBOL FUNCTIONSOIC DFN
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
“Three-St ate PWM Input” on p age6 for further details. Connect this pin to the PWM output of the controller.
Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
a return path for the upper gate drive.
5
FN9157.5
December 3, 2007
Description
www.BDTIC.com/Intersil
ISL6594A, ISL6594B
PWM
t
PDLU
t
FU
t
RL
FIGURE 1. TIMING DIAGRAM
UGATE
LGATE
t
PDLL
t
PDHU
t
RU
t
FL
t
PDHL
Operation
Designed for versatility and speed, the ISL6594A and
ISL6594B MOSFET drivers control both high-side and low-side
N-Channel FETs of a half-bridge power train from one
externally provided PWM signal.
Prior to VCC exceeding its POR level, the Pre-POR
overvoltage protection function is activated during initial
start-up; the upper gate (UGATE) is held low and the lower
gate (LGATE), controlled by the Pre-POR overvoltage
protection circuits, is connected to the PHASE. Once the
VCC voltage surpasses the VCC Rising Threshold (See
“Electrical Specifications” on page 4), the PWM signal takes
control of gate transitions. A rising edge on PWM initiates
the turn-off of the lower MOSFET (see “Timing Diagram” on
page 6 ) . After a short propagation delay [t
gate begins to fall. Typical fall times [t
FL
“Electrical Specifications” on page 4. Adaptive shoot-through
circuitry monitors the LGATE voltage and determines the
upper gate delay time [t
]. This prevents both the lower
PDHU
and upper MOSFETs from conducting simultaneously. Once
this delay period is complete, the upper gate drive begins to
rise [t
] and the upper MOSFET turns on.
RU
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
gate begins to fall [t
] is encountered before the upper
PDLU
]. Again, the adaptive shoot-through
FU
circuitry determines the lower gate delay time, t
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See next section for
details). The lower gate then rises [t
], turning on the lower
RL
MOSFET.
], the lower
PDLL
] are provided in
. The
PDHL
1.18V < PWM < 2.36V
t
TSSHD
Adaptive Zero Shoot-Through Deadtime Control
These drivers incorporate an adaptive deadtime control
technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFETs’
body-diode conduction, and to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other
has turned off.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it drops below 1.75V, at which time the
UGATE is released to rise after 20ns of propagation delay.
Once the PHASE is high, the adaptive shoot-through
circuitry monitors the PHASE and UGATE voltages during a
PWM falling edge and the subsequent UGATE turn-off. If
either the UGATE falls to less than 1.75V above the PHASE
or the PHASE falls to less than +0.8V, the LGATE is
released to turn on.
Three-State PWM Input
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set hold off time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the “Electrical Specifications” on
page 4 determine when the lower and upper gates are
enabled.
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
t
PDTS
0.76V < PWM < 1.96V
t
TSSHD
t
PDTS
6
FN9157.5
December 3, 2007
ISL6594A, ISL6594B
www.BDTIC.com/Intersil
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 9.8V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 7.6V (typically), operation of the driver is
disabled.
Pre-POR Overvoltage Protection
For the ISL6594A, prior to VCC exceeding its POR level, the
upper gate is held low. For the ISL6594B, the upper gate
driver is powered from PVCC and will be held low when a
voltage of 2.75V or higher is present on PVCC as VCC
surpasses its POR threshold. For both devices, the lower
gate is controlled by the overvoltage protection circuits
during initial start-up. The PHASE is connected to the gate of
the low side MOSFET (LGATE), which provides some
protection to the microprocessor if the upper MOSFET(s) is
shorted during initial start-up. For complete protection, the
low side MOSFET should have a gate threshold well below
the maximum voltage rating of the load/microprocessor.
When VCC drops below its POR level, both gates pull low
and the Pre-POR overvoltage protection circuits are not
activated until VCC resets.
Internal Bootstrap Device
Both drivers feature an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above UVCC + 5V and its capacitance value can be
chosen from Equation 1:
Q
GATE
C
BOOT_CAP
Q
GATE
where Q
at V
GS1
control MOSFETs. The ΔV
allowable droop in the rail of the upper gate drive.
--------------------------------------
≥
ΔV
BOOT_CAP
QG1UVCC•
------------------------------------
V
GS1
is the amount of gate charge per upper MOSFET
G1
•=
N
Q1
gate-source voltage and NQ1 is the number of
BOOT_CAP
term is defined as the
(EQ. 1)
As an example, suppose two IRLR7821 FET s are chosen as
the upper MOSFETs. The gate charge, Q
sheet is 10nC at 4.5V (V
Q
is calculated to be 53nC for UVCC (i.e. PVCC in
GATE
) gate-source voltage. Then the
GS
, from the data
G
ISL6594B, VCC in ISL6594A) = 12V. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.267μF is required.
1.6
1.4
1.2
1.0
(µF)
0.8
0.6
BOOT_CAP
C
0.4
0.2
20nC
0.0
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
Q
50nC
VOLTAGE
= 100nC
GATE
0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
ΔV
BOOT_CAP
(V)
Gate Drive Voltage Versatility
The ISL6594A and ISL6594B provide the user flexibility in
choosing the gate drive voltage for efficiency optimization.
The ISL6594A upper gate drive is fixed to VCC [+12V], but
the lower drive rail can range from 12V down to 5V
depending on what voltage is applied to PVCC. The
ISL6594B ties the upper and lower drive rails together.
Simply applying a voltage from 5V up to 12V on PVCC sets
both gate drive rail voltages simultaneously.
Power Dissipation
Package power dissipation i s mai nl y a fu nction of the
switching frequency (f
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the SO8 package is approximately 800mW at room
temperature, while the power dissipation capacity in the DFN
package with an exposed heat escape pad is more than
1.5W. The DFN package is more suitable for high frequency
applications. See “Layout Considerations” on page 8 for
thermal transfer improvement suggestions. When designing
the driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
), the output drive impedance, the
SW
7
FN9157.5
December 3, 2007
ISL6594A, ISL6594B
www.BDTIC.com/Intersil
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively:
P
Qg_TOTPQg_Q1PQg_Q2IQ
QG1UVCC
•
P
Qg_Q1
P
Qg_Q2
⎛⎞
I
⎜⎟
DR
⎝⎠
where the gate charge (Q
---------------------------------------
V
GS1
QG2LVCC
•
--------------------------------------
V
GS2
QG1UVCC NQ1••
------------------------------------------------------
V
GS1
2
+
G1
particular gate to source voltage (V
corresponding MOSFET datasheet; I
VCC•++=
2
f
• NQ1•=
SW
f
• NQ2•=
SW
LVCC NQ2••
Q
G2
-----------------------------------------------------
V
GS2
and QG2) is defined at a
and V
GS1
Q
GS2
is the driver’s total
quiescent current with no load at both drive outputs; N
and N
are number of upper and lower MOSFETs,
Q2
(EQ. 2)
+•=
f
SWIQ
(EQ. 3)
) in the
Q1
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I
Q*
VCC
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
(R
and R
GI1
and RG2) and the internal gate resistors
G1
) of MOSFETs. Figures 3 and 4 show the
GI2
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as shown in Equation 4:
P
DRPDR_UPPDR_LOWIQ
R
⎛⎞
HI1
P
DR_UP
P
DR_LOW
R
EXT1RG1
--------------------------------------
⎜⎟
R
+
⎝⎠
HI1REXT1
R
⎛⎞
HI2
--------------------------------------
⎜⎟
R
+
⎝⎠
HI2REXT2
R
GI1
-------------
+=
N
Q1
VCC•++=
R
LO1
----------------------------------------
+
R
+
LO1REXT1
R
LO2
----------------------------------------
+
R
+
LO2REXT2
R
EXT2RG2
P
Qg_Q1
---------------------
•=
P
---------------------
•=
R
-------------
+=
N
(EQ. 4)
2
Qg_Q2
2
GI2
Q2
UVCC
BOOT
PHASE
D
C
GD
R
HI1
R
LO1
G
R
GI1
R
G1
C
GS
S
Q1
C
DS
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
LVCC
D
C
GD
R
HI2
R
LO2
G
R
GI2
R
G2
C
GS
S
Q2
C
DS
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
8
FN9157.5
December 3, 2007
ISL6594A, ISL6594B
www.BDTIC.com/Intersil
Dual Flat No-Lead Plastic Package (DFN)
INDEX
SEATING
(DATUM B)
6
INDEX
AREA
(DATUM A)
NX (b)
5
SECTION "C-C"
6
AREA
C
PLANE
NX L
8
A
D
TOP VIEW
SIDE VIEW
7
D2
12
BOTTOM VIEW
D2/2
N-1N
e
(Nd-1)Xe
REF.
(A1)
2X
0.15
A
C
0.152XB
C
E
B
0.10 C
A
0.08
C
A3
8
k
NX
E2
E2/2
NX b
5
0.10 MC
0.415
C
0.200
NX b
AB
NX L
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A3 0.20 REF -
b 0.18 0.23 0.28 5,8
D 3.00 BSC -
D2 1.95 2.00 2.05 7,8
E 3.00 BSC -
E2 1.55 1.60 1.65 7,8
e 0.50 BSC -
k0.25 - - L0.300.35 0.40 8
N102
Nd 5 3
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
C
L
L
e
CC
FOR ODD TERMINAL/SIDE
TERMINAL TIP
NOTESMIN NOMINAL MAX
Rev. 3 6/04
9
FN9157.5
December 3, 2007
ISL6594A, ISL6594B
www.BDTIC.com/Intersil
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
L
h x 45°
α
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M
A1
C
0.10(0.004)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
α
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 1 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN9157.5
December 3, 2007
Loading...