intersil ISL6590 DATA SHEET

ISL6590

Data Sheet April 2003

Digital Multi-Phase PWM Controller for Core-Voltage Regulation

Processors that operate above a GHz require fast, intelligent power systems. The Intersil ISL6590 controller offers intelligent digital, multi-phase control that provides high bandwidth, optimal control frequency response, noise immunity and active transient response control algorithms. The design is fully scalable for controlling up to six phases, each featuring the Intersil ISL6580 intelligent power stage.

The user can configure and monitor the power system via the Asynchronous Serial Interface (ASI). The ISL6590 controller flexibility can be extended with the addition of an external EEPROM for updating key circuit operating parameters in the control loop and overall system design. The digital architecture reduces the design time for engineers with the use of our software. The software allows the designer the freedom to choose output stage components and still achieve optimized system performance.

The ISL6590 digital controller communicates with the ISL6580 integrated power stages via 100% digital signaling. Serial communication allows for separation of the controller and the power stage, providing placement and layout freedom to the power stage. The digital controller implements phase balancing to ensure even distribution of phase currents. The ISL6590 controller configures the ISL6580 power stage current limit, VID reference, nonoverlap period, Active Transient Response (ATR) trigger levels and maximum temperature limit. The digital controller also monitors the ISL6580 power stage peak currents, overtemperature fault, input under voltage, output over/under voltage to ensure proper operation of the power supply.

Pinout

ISL6590 (QFN)

TOP VIEW

FN9061

Features

• Open Architecture features software programmable control loop compensation enabling optimal system performance

- User accessible asynchronous serial interface

• Intel VR10

- 6-bit Dynamic VID™

- Output voltage regulation range of 0.8375V to 1.600Vdc

• 250kHz to 1MHz switching frequency

• 100% digital control and signaling

• Active Transient Response (ATR) control algorithms for minimized voltage droop and overshoot

• Controls up to six ISL6580 intelligent power stages (20A per phase, 120A total system current)

• Programmable Adaptive voltage positioning (AVP) load line

• Configurable control loop parameters (with optional external EEPROM)

• Programmable MOSFET dead time control

• High speed voltage and current control loops

• PWRGD and OUTEN

• Serial interface to ISL6580 power stages for system monitoring and configuration

• 64 Ld 9x9 QFN package

• QFN Package Option

- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad

Flat No Leads - Product Outline

- QFN Near Chip Scale Package Footprint; Improves

PCB Efficiency, Thinner in Profile.

Ordering Information

OUTEN

VID [0] VID [1] VID [2] VID [3] VID [4] VID [5]

VDD_CORE

PWRGD VDD_IO

MCLK

MDO

MCS

NDRIVE1

PWM1

PART NUMBER TEMP. (oC) PACKAGE PKG. NO.

ISL6590DR 0 to 85 64 Ld 9x9 QFN L64.9x9-S

PLL_FILTER

PLL_ANALOG_VDD

PLL_ANALOG_VSS

PLL_DIGITAL_VSS

OSC_IN

OSC_OUT

ARX

ATX

VDD_IO

SCLK

SDATA

TEST4

TEST3

PLL_DIGITAL_VDD

VDD_CORE

MDI

IDIG1

IDIG2

VDD_CORE

NDRIVE3

IDIG3

PWM3

VDD_IO

NDRIVE4

NDRIVE2

PWM2

ATRH

TEST 2

ATRL SOC ERR VDD_IO SYS_CLK VDD_IO NC NC VDD_CORE NC NC IDIG6 PWM6 NDRIVE6

TEST1

3217

IDIG4

IDIG5

PWM5

PWM4

NDRIVE5

EXT_RESETB

CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

All other trademarks mentioned are the property of their respective owners. Dynamic VID™ is a trademark of Intersil Americas Inc.

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Typical Application Circuit

ISL6590

3.3 V

5-12 V 12 V

3.3 V

V DD_IO V DD_CORE

VID[0:5]

PWRGD

OUTEN

ARX ATX

1.8 V

SCLK

SDATA

SYSCLK

PWM

NDRIV E

ISL6590

ATRH ATRL

OSC_IN OSC_OUT

ERR

SOC

IDIG

2.5 V

VDD VDRIVEVCC

VREF

ATRH ATRL

ISL6580

ERR SOC

SCLK SDATA CLK

PWM IDIG NDRIV E

3.3 V

VDD VDRIVEVCC

VREF

ATRH ATRL

ISENSE

5-12 V

ISL6580

ERR SOC SCLK SDATA CLK

ISENS E

VSENP

VSENN

VSW

NGA TE

PGND

GND

12 V

VSENP

VSENN

VSW

NGA TE

REGULATION

CHANNEL

Vout

RTN

PWM

IDIG

NDRIV E

TEST1 TEST2

TEST3 TEST4

MDO

MDI

EEPROM

MCS

MCL K

PWM

IDIG

NDRIV E

GND

CONTROLLER

INTE RFACE BUS

PWM IDIG NDRIV E

5-12 V 12 V

3.3 V

VDD VD RI VEVCC

VREF

ATRH

ATRL

ISL6580

ERR SOC SCLK SDATA CLK

PWM IDIG

NDRIV E

PGND

GND

VSENP

VSENN

ISENS E

VSW

NGA TE

PGND

GND

ATR CHANNEL

UV/OV CHANNEL

ISL6590

Absolute Maximum Ratings

Supply Voltage

(VDD_IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.63V

(VDD_Core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.98V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV

Recommended Operating Conditions

Supply Voltage

(VDD_IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V ±5%

(VDD_Core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V ±5%

(Analog PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V ±5%

(Digital PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V ±5%

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .0

CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.

C to 85oC

Thermal Information

Thermal Resistance (oC/W)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

JA-0 LFPM AIR

JA-100 LFPM AIR

JA-200 LFPM AIR

JA-400 LFPM AIR

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Maximum Storage Temperature Range . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .125

Maximum Storage Temperature Range . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300

. . . . . . . . . . . . . . . . . . . 29.0

. . . . . . . . . . . . . . . . . 26.6

. . . . . . . . . . . . . . . . . 25.0

. . . . . . . . . . . . . . . . . 23.2

C to 150oC

o o

NOTE:

is measured with the component mounted on a “High Effective” Thermal Conductivity Board with “Direct Attach” features. (See Tech Brief

1. θ

TB379 for details.)

Electrical Specifications Operating Conditions: V

DDIO

= 3.3V, V

DDCORE

= 1.8V, TA = 25oC, Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

INPUTS

Outen, VID[0:5], V Outen, VID[0:-5], V

MDI, IDIG[1-6], ATRL, ATRH, SOC, ERR V

EXT_RESETB, V EXT_RESETB, V ARX, V

ARX, V

OSC_IN, V OSC_IN, V

IH IL

3.3V no internal pull-up/down resistors 0.8 - - V

3.3V no internal pull-up/down resistors - - 0.4 V

3.3V internal pull-down resistor 2.0 - - V

3.3V internal pull-down resistor - - 0.8 V

3.3V internal pull-up resistor 2.0 - - V

3.3V internal pull-up resistor - - 0.8 V

3.3V internal pull-up resistor 2.0 - - V

3.3V internal pull-up resistor - - 0.8 V No internal pull-up/down resistors 2.0 - - V No internal pull-up/down resistors - - 0.8 V

OUTPUTS

MCLK, MDO, MCS, NDRIVE[0:5], PWM[0:5], ATX, V

SYS_CLK, V SYS_CLK, V SCLK, V SCLK, V

OH OL

SDATA, V SDATA, V SDATA, V SDATA, V PWRGD, V PWRGD, V OSC_OUT, V OSC_OUT, V

OL OH OL

OH OL IH IL

OH OL

No internal pull-up/down resistors, 8mA drive 2.4 - - V

No internal pull-up/down resistors, 8mA drive - - 0.4 V

No internal pull-up/down resistors, 20mA drive 2.4 - - V No internal pull-up/down resistors, 20mA drive - - 0.4 V No internal pull-up/down resistors, 16mA drive 2.4 - - V No internal pull-up/down resistors, 16mA drive - - 0.4 V

3.3V pull-up resistor, 16mA drive 2.4 - - V

3.3V pull-up resistor, 16mA drive - - 0.4 V

3.3V pull-up resistor 2.0 - - V

3.3V pull-up resistor - - 0.8 V Open drain, 6mA drive 2.4 - - V Open drain, 6mA drive - - 0.4 V No internal pull-up/down resistors, 10mA drive 2.4 - - V No internal pull-up/down resistors, 10mA drive - - 0.4 V

C C

ISL6590

Electrical Specifications Operating Conditions: V

DDIO

= 3.3V, V

DDCORE

= 1.8V, TA = 25oC, Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

POWER-ON RESET AND ENABLE

POR Threshold V

Rising 1.4 - - V

ddio

Falling - - 2.55 V

ddio

ddcore Rising

ddcore Falling

0.7 - - V

--1.4V

OUTEN Threshold OUTEN Rising -0.71- V

OUTEN Falling -0.64- V

OSCILLATOR

Adjustment Range 0.250 - 1 MHz Max Duty Cycle 24 TBD - %

NOTE:

1. Reserved for note.

Block Diagram

Ext_Reset

ATX

ARX

OUTEN

PWRGD

VID[5:0]

POR

Asynchronous

Serial Interface

State

Control and

Fault

Moni tor

Memory Bus

MUX

Feedback

Control

PWM Driver

Current

Loop

Voltage

Loop

PWM [6:1]

NDRIVE [6: 1]

ATRH

ATRL

IDIG[6:1]

MDI

MCLK

MCS

MDO

OSC_OUT

OSC_IN

PLL_FILTER

Clock

Distribution

Non-Volatile

SPI EEPOM

Interface

State

Machine

Control/

Status

Registers

MHz Memory

Mapped

Registers

FIGURE 1. ISL6590 BLOCK DIAGRAM

AVP

Backside Serial

Bus

SOC

ERR

SCLK

SDATA

SYS_CLK

ISL6590

Pin Descriptions

PIN NO. PIN NAME TYPE PIN DESCRIPTION

1 OUTEN Input Output enable high input signal used to command the regulator on and a low input signal turns

the regulator off. 2-7 VID[0:5] Input Voltage identification (6 bit). Programs Vout regulation voltage. 8, 21, 39, 57 VDD_CORE Power IC internal core supply voltage (1.8 VDC logic). 9 PWRGD Output Power Good high output signal to indicate the regulator output voltage is within the specified

10, 25, 42, 44, 54

11 MCLK Output

12 MDO Output 13 MDI Input 14 MCS Output 15, 18, 22,

26, 30, 34 16, 19, 23,

27, 31, 35 17, 20, 24,

28, 32, 36

29 EXT_Reset Input Voltage identification (6 bit). Programs Vout regulation voltage. 33, 48, 50,

51 37, 38, 40,

41 43 SYSCLK Input/Output System clock which runs at a 133.3MHz rate used to clock the ISL6580. This is generated by the

45 ERR Input Serial data transmitted at a 66MHz (or SYSCLK/2) rate. This 6 bit voltage error is feedback into

46 SOC Input Start of Conversion signal initiated by the ISL6580’s Voltage A/D to create the ERR signal. 47 ATRL Input Active Transient Response Low input signal from the ISL6580 indicating a voltage overshoot on

49 ATRH Input Active Transient Response High input signal from the ISL6580 indicating a voltage droop on the

52 SDATA Input/Output Controller serial interface for communication, monitoring, and configuration data between the

53 SCLK Output Serial digital bus clock supplied for the 16.67MHz clocking that accompanies SDATA via the

55 ATX Output Asynchronous Serial Interface Transmit 56 ARX Input Asynchronous Serial Interface Receive 58 OSC_OUT Output Only used if part is using a crystal to generate the system clock. 59 OSC_IN Input Requires a 33.33MHz oscillator or crystal which is used to generate system clock. 60 PLL_DIG_VSS

61 PLL_DIG_VDD Power 62 PLL_ANA_VSS Ground Analog Ground for the 4X clock multiplier PLL.

63 PLL_ANA_VDD Power 1.8V power supply for the 4X clock multiplier PLL (1.8 VDC logic). 64 PLL_Filter Analog Input Filter cap for PLL. 65 GND Ground Paddle IC Ground

VDD_IO Power IC I/O input supply voltage (3.3 VDC logic).

NDRIVE[1:6] Output Low side drive signal used to initiate the ISL6580 to turn on the LSFET.

PWM[1:6] Output PWM performs pulse width modulation which is used to turn on the ISL6580’s power devices.

IDIG[1:6]

TEST[1:4] Output Test pins for part evaluation

NC N/A These pins have not been bonded out.

PLL Bypass

Input Current A/D data serial 7-bit digital word (MSB first). The first bit is a start bit (Start = 1). The

Ground

Input

range. A low signal indicates the voltage is not within range.

EEPROM external memory clock, data is clocked out of the IC on the rising edge and data is

clocked into the ISL6580 IC on the falling edge. Compliant with SPI™ EEPROMs.

EEPROM external memory data output. Compliant with SPI EEPROMs

EEPROM external memory data input. Compliant with SPI EEPROMs.

EEPROM external memory chip select (Active low). Compliant with SPI EEPROMs.

remaining 6 bits represent the sampled peak current in the drain of the particular ISL6580

P-Channel HSFET. (IDIG word transmission is triggered by the falling edge of the PWM signal.)

IDIG is an input that is received at SYSCLK/2, normally 66.6MHz.

internal PLL circuit to create a 4x frequency multiply of the OSC_IN frequency.

the control loop and used to regulate the output voltage.

the converter output.

converter output.

ISL6580 and ISL6590 controller.

Backside serial bus.

Digital Ground

Test mode to bypass PLL input to core.

1.8V power supply for the 4X clock multiplier PLL clock tree driver

for the 4X clock multiplier PLL.

(1.8 VDC logic).

ISL6590

General Description

The ISL6590 is a multiphase digital controller optimized for microprocessor core voltage generation in the 0.8375Vdc -

1.600Vdc output range and high current loading up to 150A with a 12Vdc input. It is intended to be used as a chipset with multiple ISL6580 power stages. The current per stage is up to 25A and the switching frequency can operate from 250kHz to 1MHz. The adaptability of having a digital controller with a serial data bus to the power stages means that the control algorithms can be adjusted with software instead of having to make hardware or board changes. All of the features of the ISL6590 are available in applications that require 3-6 phases of PWM (Pulse-Width Modulation) core voltage regulation. For more information on the power stage, consult the ISL6580 data sheet.

Block Diagram Overview

The ISL6590 contains functionality to control up to 6 power stages with PWM core voltage regulation. The blocks described follow the block diagram shown in Figure 1. For additional help it would be useful to reference the block diagram of the ISL6580, which is located in the ISL6580 data sheet.

Asynchronous Serial Interface (ASI) (ATX, ARX)

This 2-wire serial data host interface is designed to transfer command information from the designers PC to the controller, such as adjustments to register settings. The ASI is used during the design process to configure and test your power supply settings. It allows the designer to change loop coefficients to achieve the best response for their system design. This serial bus runs at 115K baud rate to interface with a host computer during testing.

Backside Serial Bus (BSB) (SDATA, SCLK)

The backside serial bus is a 2-wire communication between the ISL6590 controller and the ISL6580 power ICs used for transfer of control and status information. This bus is critical for proper operation of the system, any miscommunications will cause a bus error between the controller and power stages and shutdown the power supply. A bus error can be caused by poor routing of those lines or by a failed ISL6580.

Feedback (PWM, NDRIVE, ATR, IDIG, SOC, ERR)

The feedback control block implements the loop compensation, hysteretic control, and switch driver. Defaults for the loop compensation coefficients are retained in the memory block. If the default values need to be optimized, they can be adjusted using the ASI.

The PWM generator that drives NDRIVE and PWM derives its waveform from a current balancing circuit that balances the current to each phase. The current balancing circuit requires information about the amount of current each phase is supporting. This information is obtained using the 6-bit current ADC in each ISL6580.

Each of the ISL6580s contains a 6-bit voltage ADC that can be used to measure the difference between the core voltage at the output and a reference voltage that is set by the VID information. Even though each ISL6580 has the voltage ADC, only one of them is required to use it.

When a large change in current occurs at the output load, a large voltage transient also occurs. The ATRH and ATRL levels are designed to trigger a temporary mode in which the PWM generator aligns all phases or removes all phases in order to quickly raise or lower the output voltage.

Controller Memory

The internal volatile memory provides control and status registers which are reset to default states on each power up. These registers can be altered with commands from the ASI, the State Control and Fault Monitors, or the Serial Interface with the ISL6580 Power ICs.

EEPROM Interface (MCS, MCLK, MDI, MDO)

An external EEPROM (non-volatile memory) can be used to write custom information to the volatile memory. The nonvolatile memory can be modified via the ASI. The EEPROM contains configuration values for a given design. The ISL6590 uses the standard Serial Peripheral Interface (SPI™) serial protocol for this memory. be at least a 2K byte memory. Larger memory can be used without problems, however the ISL6590 will utilize only 2K bytes.

The EEPROM must

Clock Distribution (OSC_IN, OSC_OUT)

The clock distribution block creates the internal system clock from an external clock source such as a crystal oscillator. It performs a 4x frequency multiplication of the external clock frequency. The maximum clock input is 33.33MHz for an IC sample rate of 133.3MHz. It generates the read/write clock for the ASI. The system clock is provided to the ISL6580s via the SYS_CLK pin.

State Control and Fault Monitoring (OUTEN, VID[5:0], PWRGD)

Implements control of the power system state and processes fault information from the ISL6580 Power IC. All fault detection within the system is accomplished within each individual ISL6580 and is communicated to the ISL6590 via the Backside Serial Interface. ISL6590 detects the fault through constant polling of the ISL6580 fault registers and responds by tristating the outputs or shutting down the system which then requires a power cycle and initiates a softstart sequence.

Memory Bus Multiplexer

Controls the priority of data transfer to the volatile memory (control registers) from both the ASI and the state control and fault monitoring. The state control and fault monitoring is given priority over the ASI.

6-BIT OFFSET BINARY

ERR

(FROM ERR SIGNAL - ISL6580 VOLTAGE ADC)

1 2 3 4 5 6

6-BIT SERIAL

IDIG IDIG IDIG IDIG IDIG IDIG

CURRENT

AVERAGING

ISL6590

AVG

AVP

PID

OUT

PWM[6:1]

ISHARE

ATRH ATRL

(FROM ISL6580 ATRH AND ATRL SIGNALS)

FIGURE 2. FEEDBACK CONTROL DIAGRAM

Block Diagram Details

Feedback Control

At a minimum, there must be three ISL6580s available to implement the following modes.

1. Regulation Mode (Voltage ADC)

2. Voltage Transient Mode (ATR Window Comparator)

3. Over/Under Voltage Mode (O/U Voltage Comparator)

Additional phases 4-6 are in normal conversion mode. Located in the Feedback Control section of the ISL6590 is

an interface to the feedback information collected and delivered by the analog ISL6580 power stages. To understand the functionality of the ISL6590 feedback algorithms, key blocks of the ISL6580 must be understood, such as the ADC converters and the window comparator.

6-bit Current ADC (ISL6580)

A current ADC (Analog-to-Digital Converter) located in each ISL6580 measures, converts, and transmits that driver’s current back to the ISL6590 serially via the IDIG[6:1] bus. The start of conversion is initiated on the falling edge of the PWM input signal at the ISL6580 and the conversion takes about 8 SYSCLK cycles. The SYSCLK signal is provided by the ISL6590 to the ISL6580 and is equal to 4x the crystal

CURRENT

BALANCING

ERR

CURRENT

FLASH

LOGIC

ATRH

ATRL

PWM

GENERATOR

PARALLEL LINES

NDRIVE[6:1]

(TO ISL6580s)

oscillator rate. The 6-bit current ADC is a successive approximation converter, requiring one clock per bit, for a total of 6 clocks. Another clock cycle is for transferring data to the serial register. Since the PWM and SYSCLK may not be phase related, one extra clock cycle may be required depending on the alignment.

It is not possible to predict when the serial data will begin to transfer on the IDIG bus, so a start bit is used to notify the ISL6590 that data is coming. The start bit is followed by the six data bits in descending order from the MSB. A bit is transferred every two SYSCLK cycles. Since the PWM signal is used as the start of conversion signal, a significant glitch on the PWM signal during the conversion or data transfer will initiate a new conversion and abort the present conversion. The ISL6590 uses the serial current information on the IDIG bus to calculate the average of all the phases, compare it to the current of each phase, and balance the phases by adjusting each PWM and NDRIVE signal as necessary.

Because the start of conversion is dictated by the falling edge of the PWM signal, the effective sample rate of the current information is the PWM rate (typ<1MHz), even though each bit is converted and transferred at SYSCLK/2 =

66.6MHz. All ISL6580s will return IDIG information, regardless of their mode.

ISL6590

6-bit Voltage ADC (ISL6580)

Each of the ISL6580s contain a 6-bit voltage ADC that can be used to measure the difference between the core voltage at the output and a reference voltage that is set by the VID information. The VID is sent to the designated ISL6580 via the backside serial bus from the ISL6590 prior to soft start. The voltage difference measured is sent via the ERR signal serially to the ISL6590. Even though each ISL6580 has the voltage ADC, only one of them is required to use it. This mode is called the Regulation Mode. The conversion is initiated with the SOC (Start Of Conversion) signal from the ISL6580 pulsing high for two SYSCLK cycles. After another two SYSCLK cycles, the 6 bits of data are shifted out of the ISL6580 on the ERR signal, one bit every two SYSCLK cycles, starting with the MSB.

Because the ADC uses a successive approximation architecture, every two SYSCLK cycles converts one bit, for a total of 12 SYSCLK cycles to make the 6-bit conversion. With a 133.3MHz SYSCLK, 66.6MHz is the sample rate per bit of the ADC and is also the serial data rate of the ERR0 signal. However, since the SOC signal initiates the sampling process, the effective overall sample rate of the voltage measuring system is equal to the SOC rate.

Window Comparator (ISL6580)

Each ISL6580 contains a window comparator. At least two ISL6580s must be configured to use it. One is configured with comparator trip levels for Transient Voltage Mode (ATR described below) and the other for Over/Under Voltage Mode which responds via the fault registers and is described in detail under Fault Processing.

Adaptive Voltage Positioning (AVP)

The Adaptive Voltage Positioning section of the ISL6590 takes the average current of all the active ISL6580 channels and passes it through an AVP gain factor and a low pass filter. The AVP gain factor sets the slope of the load line so that the voltage at high current loading is intentionally less than the voltage at small current loading. The output of the low pass filter is subtracted from the ADC voltage error (ERR signal) to adjust the operating voltage position. The AVP value is modified in the digital compensation block with the coefficients stored in the ISL6590 memory. The resulting modified output is sent to the PWM generator to adjust the target output voltage for all phases with a voltage offset from the nominal VID so that current and voltage transients can better be accommodated.

removes all phases in order to quickly raise or lower the output voltage. The event is short-lived and the controller quickly returns to normal operation, but the result is an instantaneous boost or reduction in output voltage to keep the transient event within the required regulation window. An ATR window comparator located in the designated ISL6580 generates the ATRH or ATRL indicator signals when the event occurs. The ATRH and ATRL trip levels are offsets from the VID voltage and are set in ISL6590 register 0883h, each with a 4-bit word. The ATRH, ATRL, and VID values from the ISL6590 memory are sent to the designated ISL6580’s registers via the BSB prior to soft start. In the ISL6580, these are added or subtracted from the VID target value with 7.5mV LSB resolution to set the trip levels.

Whereas AVP is performed with slight, tightly controlled modifications to the PWM duty cycle in the ISL6590 using sampled current data from each phase, ATR is performed with preset values and trips a comparator in a single ISL6580. The ISL6580 ATRH or ATRL signals immediately tell the PWM generator in the ISL6590 to enter the ATR mode. For this reason, the ATR mode is able to react much quicker than the sample rate derived AVP.

MAX=VID

ATRL

PAVP

=MIN

LOAD

PVID

=MAX

LOAD

NAVP

ATRH

MIN

FIGURE 3. ADAPTIVE VOLTAGE POSITIONING AND ACTIVE

TRANSIENT RESPONSE TRIP LEVELS

Active Transient Response (ATR)

Voltage Transient Mode must be performed by one ISL6580 in the system (but not one already processing another mode). It is done by using the ATR signals between the ISL6580 and ISL6590. When a large change in current occurs at the load, a large voltage transient also occurs. The ATRH and ATRL levels are designed to trigger a temporary mode in which the PWM generator aligns all phases or

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