Intersil ISL6560, ISL6562 Application Note

®

ISL6560/62 Evaluation Board

Application Note April 2002

Introduction

The ISL6560/62 Evaluation Board was designed to
accommodate either the ISL6560 or the ISL6562 power
supply controller ICs. CORE voltage is set by a five bit DAC
that is usually programmed by the microprocessor. For this
board, DAC codes are entered via a five position dip switch.
Power supply input voltages may be applied through three
banana posts or an ATX connector on the board. With an
ATXsupply the main input voltage to theconverter is 5V.The
ATX 12V supply powers the ISL6560/62, the HIP6601 gate
drivers and the transient load generator. A toggle switch is
provided on the board to enable the ATX supply.

Converter input voltage via the banana connectors can
range from 5V to 12V. A separate connector supplies 12V to
the ISL6560/62, transient load generator and the gate
drivers as described above.

Figure 1 shows the Evaluation Board. Note the ATX
connector at the top of the board. The ATX power switch
SW2, is located to the right of the connector.

AN1009.0

Author: Hal Wittlinger

Description

This board was design so that a wide range of input voltages
could be used. Burndy binding posts at the lower end of the
board provide the high current connections for the output
load.

Just above the output connectors is a pulse generator to
provide 40A transient loading to verify response to pulse
loading of the supply. Scope probe connectors monitor the
current pulse, and output voltage.

Extra output capacitor locations are available to modify the
output capacitor configuration or type of capacitors. 22µF
ceramic capacitors accompany the bulk electrolytic
capacitors. In an application where the supply is connected
to an active load, high frequency capacitors should be
located as close as possible to the load to help reduce
undesired transient voltage changes at the load.

The ISL6560/62 is located on the left side of the board.
Immediately below the controller IC is the POWER GOOD
monitoring circuit. A dual RED-GREEN LED indicator is
green when the CORE voltage is within the defined data
sheet limits. Figure 13 shows a schematic diagram of the
POWER GOOD monitoring circuit.

ISL6560 and ISL6562

Figure 2 shows a simplified functional block diagram of these
devices, outlining the major differences between the two ICs.

REF

3V REF

WRGD

+

UV

X0.82

-

+

OVP

-

X1.24

VID4
VID3
VID2
VID1
VID0

FB

COMP

FIGURE 2. SIMPLIFIED BLOCK DIAGRAM SHOWING

D/A

DAC Codes
ISL6560 - VRM 9.0
ISL6562 - VRM 8.5

MAJOR DEVICE DIFFERENCES

+

E/A

-

CONTROL

GND

CS Threshold Voltage

VCC

UVLO and

BIAS CIRCUITS

OSCILLATOR

_

LOGIC

+

CMP

-

ISL6560 - 157mV
ISL6562 - 79mV

CT

PWM1

PWM2

CS+

CS-

FIGURE 1. EVALUATION BOARD

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002. All Rights Reserved

ISL6560/62 Evaluation Board

The ISL6560 has a DAC scaled for VRM9.0 codes while the
ISL6562’s DAC is set to VRM8.5 codes. The other major
difference is the Current Comparator threshold voltage.

The typical thresholdvoltage for the ISL6560 is 157mV while
the ISL6562 is more sensitiveand has a threshold voltage of
79mV.

Figure 3 shows the Current Comparator threshold voltage
versus the COMP voltage.

3.0

2.5

2.0

1.5

= 25V / V

i

n

1.0

COMP (Volts)

V

0.5

0

0

20 40

FIGURE 3. CURRENT COMPARATOR THRESHOLD

ISL6562

= 12.5V / V

i

n

60

V

VOLTAGE AS A FUNCTION OF V

80

CS(CL)

ISL6560

100 120

(mV)

140 160

COMP

Oscillator

An oscillator drives a divider that reduces the channel
frequency to one half of the oscillator. Each channel is
initiated by the oscillator and terminated by the current
comparator.A maximum duty cycle of 50% is established by
this arrangement.

Power Good

or a switch. This device should be located next the COMP
pin to reduce the possibility of external pickup by the pin.
The oscillator is disabled when the COMP voltage drops
below 0.56V for the ISL6560 and 0.64V for the ISL6562.
Minimum current for the pull down device should be 2mA.
The COMP terminal is brought out as a test point on the
Evaluation Board. A ground terminal and the 3V Reference
terminal are located near the COMP terminal on the
Evaluation Board.

ISL6562 On The Board

As explained earlier the board is designed to be used with
either the ISL6560 or the ISL6562. The boards are usually
shipped with the ISL6560. Boards populated with the
ISL6562 have an additional 5mΩ resistor placed in the R15
location.

Evaluation Board Quick Start

To aid in getting the board functioning as quickly as possible,
a sheet similar to Figure 4 is included with each board. This
shows the location of all pertinent parts and test points.

VID Codes

Pin 1

of ISL6560/62

5

1

12V Input for

Controller

Gate Drivers

and Load
Generator

Main Supply Input

ATX Connector

Note: ATX Supply connected

to use ATX 5V supply for

Main Input. ATX 12V is used

for low power circuitry on board.

3.3V or 12V

ATX Power Switch

CALL 1-888 Intersil

Operation of the controller is monitored by the Power Good
circuitry which controls an open drain N-Channel MOS
transistor. When the CORE voltage is outside the 82% and
124% limits, the MOSFET pulls down an external load. Over
voltage switches both upper PWM power MOSFETs OFF
and pulls down the lower output power MOSFETs to protect
the load.

Over Current

Over current is detected by the output voltage dropping
below the under voltage limit. This results in several
occurrences. First the Current Comparator limit is reduce to
95mV from 157mV for the ISL6560 and 47mV from 79mV for
the ISL6562. This effectivelyfoldsbackthe current, while the
CORE voltage is now set to a lowerlimitof 400mV to 500mV.
Moreover, the oscillator frequency is reduce to about one
fifth of its normal operating value by reducing the oscillator
charging current to 36µA from its normal operating value of
150µA.

Converter Disable

To disable the converter, the COMP terminal may be pulled
to ground with a NPN transistor, N-Channel MOS transistor

Scope Probe

10mV/A

Internal
Load Generator

2 Position Switch

Each Position

ON - OFF

Current for

each Position:

20A at 1.500V

C

Output to an External Load

FIGURE 4. PERTIENT POINTS ON ISL6560/62

EVALUATION BOARD

2

ISL6560/62 Evaluation Board

Transient Load Generator

Probably one of the most interesting tests for a regulator
system is the transient load. From this single test one can
access voltage droop, loop stability and the regulator’s
response to load changes going from no load to full load and
the recovery after rapid load removal. To quickly determine
these characteristics, a pulse load generator is incorporated
on the evaluation board. A current load pulse at about 20A
per position at 1.5V output is activated with two slide
switches.A scope probe connector is providedto monitor the
current pulse and is calibrated to read 10mV/A. Figures 5, 6,
and 7 show the transient response of the Evaluation Board
with 12V input, operating with the internal load generator
which provides slightly over a 40A load step. For all scope
shots: Top trace is PWM 1 output, next is V
Center trace is V

at 50mV/div and the lower traceis the

CORE

load current at 20A/div. DAC set to 1.500V.

COMP

at 1V/div.

Efficiency

Figures 8 and 9 show the efficiency of the converter with
CORE voltage at the two extremesof the DAC voltage and at

1.500V, near the middle of the range. The curves show 12V
input and 5V input. Note the improvement in efficiency as the
output voltage approaches the input voltage, with increasing
duty cycle.

Snubber Networks

Snubbers are not used in this design, but pad locations and
connections to PHASE and ground are provided by R2 - C7
for PHASE 1 and R4 - C9 for PHASE 2.

100

90

80
70

EFFICIENCY (%)

60

50

0 5 10 15 20 25 30 35 40

FIGURE 8. 12V INPUT EFFICIENCY AT DAC EXTREMES

VIN = 12V

V

OUT

= 1.85V

V

= 1.10V

OUT

LOAD CURRENT (A)

V

OUT

= 1.50V

FIGURE 5. 44A TRANSIENT CURRENT PULSE

FIGURE 6. EXPANDED FRONT EDGE OF CURRENT PULSE

FIGURE 7. EXPANDED BACK EDGE OF CURRENT PULSE

100

90

80
70

EFFICIENCY (%)

60

50

0 5 10 15 20 25 30 35 40

FIGURE 9. 5V INPUT EFFICIENCY AT DAC EXTREMES

VIN = 5V

V

V

= 1.10V

OUT

LOAD CURRENT (A)

OUT

= 1.85V

V

OUT

= 1.50V

PC Board Schematic

Figure 11 shows the main schematic. The Power Good
indicator circuit is shown in figure 13. Figure 12 shows the
schematic of the transient load generator.

The layout is shown in Figures 14 and 15, starting with the
silk screen in Figure 14.

The Bill of Material is shown in Table1.

Following the Bill of Materials is quick design guide.

PC Board Layout Considerations

Like all high current supplies where low voltage control
signals in the millivolt range must live with high voltage, high
current switching signals, PC board layout becomes crucial
in obtaining a satisfactory supply.

3

ISL6560/62 Evaluation Board

Figure 10 shows a simplified diagram highlighting the critical
areas of a PC board layout. This diagram and the following
material represent goals to work towards during the layout
phase. Goals will be compromised during the layout process
due to component placement and space constraints. The
following text reviews these layout considerations in more
detail.

Current Sampling

1. Place the current sampling or sense resistor as close as
possible to the upper MOSFET drains. This is important
since the added inductance and resistance increase the
impedance and result in a reduction in drain voltage during
high peak pulse currents.

2. Current sense is critical, especially at lower current levels
where the current comparator threshold voltage is lower. A
good Kelvin connection requires that the voltage sample
must be taken at the R

planes that the resistor is connected.

3. The lines to the current sense resistor should be parallel
and run away from the PHASE or PWM signals to prevent
coupling of spikes to the current comparator input that may
delay or advance triggering of the comparator. Parallel rout­ing will work towards equal exposure for both lines, so that
the comparator common mode rejection characteristic will
reduce the influence of coupled noise.

resistor ends and not at the

SENSE

Voltage Sampling

1. To obtain optimum regulation use the Kelvin connection
for the output voltage sample as shown on the Functional
System Schematic Diagram of Figure 10. The ground con­nection, pin 9 of the ISL6560 should be connected to the
system ground at the load.

2. The two voltage sampling lines described in item 1 above
should also be routed away from any high current or high
pulse voltages such as the phase lines or pads. Doing this
will reduce the possibility of coupling undesired pulses into
the feedback signal and either modifying the output of the
error amplifier or, if of sufficient amplitude, spuriously trigger­ing the current comparator by readjusting the threshold volt­age.

Other Considerations

1. Keep the leads to the timing capacitor connected to pin
CT short and return the ground directly to pin 9.

2. When using a transistor to disable the converter by pulling
the CT pin to ground, place the transistor close to the CT pin
to minimize extraneous signal pickup.

3. As in all designs, keep decoupling networks near the pins
that must be decoupled. For example, the decoupling/filter
network on the FB input shown below. The series resistor
should be located next to the FB pin.

4. Place the current sense filter network near the controller.
This will help reduce extraneous inputs to the comparator.

12V

+V

IN

VCC
REF

CS­PWM1
PWM2

CS+

GND

16
15
14
13
12
11
10

Locate

Parts

Next
to IC

9

INPUT

VID CODES

from

PROCSSOR

1

VID4

2

VID3

3

VID2

{

{

VID1

4

VID0

5

COMP

6

FB

7

CT

8

Locate

Parts

Next to IC

PWRGD

ISL6560

4. Large power and ground planes are critical to keeping
performance and efficiency high. Considera 1mΩ resistance
in a 40A supply line. With 1.8V output, this results in slightly
over 2% power loss in a 72W supply.

Keep Leads Together

& Away from Output

1
2
3
4

PHASE

UGATE
BOOT
PWM
GND

PVCC

VCC

LGATE

HIP6601ECB

Place Near Drains of the

Output Transistors

8
7
6
5

Try to return bypass
capacitors to ground

of lower MOSFETs

+V

CORE

FIGURE 10. SCHEMATIC DIAGRAM SHOWING ONLY ONE CHANNEL OF “IDEAL” COMPONENT PLACEMENT

4

ISL6560/62 Evaluation Board

ATX Connector

J1

20191817161415

8109

131112

1

2

3

4

576

SW2

5V - 12V

TP7

22k
R11

TP9

15k

R12

4.3k

R27

+V

12V

SW1

1nF

TP12

1

VID4

2

VID3

3

VID2
VID1

4

VID0

5

COMP

6

FB

7

CT

8

C14

100pF

C13

6 - 470µF
C15, C17-18
C29, C50-51

2 - 4.7µF

C41-42

4.7µF

VCC

REF

CS­PWM1
PWM2

CS+

PWRGD

GND

ISL6560

U3

C40

16
15
14
13
12
11
10

9

TP10

10Ω

R6

1nF

C10

330pF

C11

5mΩ

R13

15nF

C20

330Ω

R7

TP4

TP11

TP5

TP8

20Ω
R14

1

UGATE

2

BOOT

3

PWM

4

GND

HIP6601ECB

U1

1

UGATE

2

BOOT

3

PWM

4

GND

HIP6601ECB

U2

PHASE

PVCC

VCC

LGATE

PHASE

PVCC

VCC

LGATE

8
7
6
5

1µF
C2

8
7
6
5
1µF

C4

0.1µF
C1

TP1

0.1µF

C3

TP2

Q1

HUF76139

L1

900nH

Q2

HUF76145

TP6

Q3

HUF76139

L2

900nH

Q4 HUF76145

6 - 1500µF

C21, C24-28

16 - 22µF
C19, C30,

C34-37,

C39
C45-49,
C60-63

J2

J3

+V

CORE

TP13

L3

1µH

J4

IN

J5

J6

C12

150pF

1k

R5

FIGURE 11. SCHEMATIC DIAGRAM OF A 40A SUPPLY USING THE ISL6560 CONTROLLER AND HIP6601 GATE DRIVERS

To CORE Plan

4.7µF
C43

12V

1
2
3
4

V

DD

HB
HO
HS

HIP2100

12V

46.4k
R19

LO

V

SS

LI

HI

U4

402
R20

Q7 2N7002

SW4

8
7

10k
R29

6

732Ω
R26

324Ω
R16

5

732Ω
R32

SW4A

10k
R28

324Ω
R18

10µF

D1

BAV99TA

D2

BAV99TA

R22

0.05Ω

HUF78129

Q8

R30
100

R23

33.2

TP14

R31

100

Q9 HUF78129

Current

Monitoring

10mV / Amp

R24

0.05Ω

C44

To CORE GND Plan

FIGURE 12. SCHEMATIC DIAGRAM OF THE 40A PULSE GENERATOR ON THE POWER SUPPLY BOARD

5

ISL6560/62 Evaluation Board

To PWRGD

Pin 10

12V

GREEN RED

LED 1

LED 1A

120k

3.3k

R9

R8

Q5
2N7002

FIGURE 13. SCHEMATIC DIAGRAM OF THE POWER GOOD MONITORING CIRCUIT

3.3k
R10

Q6

2N7002

CAll 1-888 Intersil

6

C

FIGURE 14. SILK SCREEN

ISL6560/62 Evaluation Board

FIGURE 15A. TOP COPPER

FIGURE 15B. GROUND PLAN

FIGURE 15C. POWER PLAN

FIGURE 15D. BOTTOM COPPER

FIGURES 15A-D. Showing ALL FOUR LAYERS OF THE PC BOARD

7

ISL6560/62 Evaluation Board

TABLE 1. Bill of Materials

Quantity Reference Part PCB Footprint Vendor Part Number

2 C1,C3

2 C2,C4 1uF, 25V, X7R

2 C5,C8, Not Populated P1206
2 C7,C9 Not populated P1206
2 C10, C12 1nF, 25V, X7R

1 C11 330pF, 5%, 25V,

1 C13 100pF, 5%, 25V,

1 C14 150pF, 5%, 25V,

6 C15,C17,C18,C29,C50,C51 470uF, 16V 10x16 Rubycon 16ZA470-10x16

16 C19,C30,C34,C35,C36,C37,

C39,C45,C46,C47,C48,C49,
C60,C61,C62,C63

1 C20 15nF, 10%, 25V,

6 C21,C24,C25,C26,C27,C28 1500uF, 4V 10x20

6 C22,C23,C38,C31,C32,C33 Not Populated 10x20
5 C40,C41,C42, C43, C52 4.7uF,16V, Y5V

1 C44 10uF, 10%, 6.3V,

1 C64 Not Populated P1206
2 D1,D2 BAV99LT1 SM/SOT23_123
1 J1 ATX CONNECTOR ATX/CONN/20P

2 J3,J2 LUG BINDING/POST_2
1 J4 Red Binding Post Post
1 J5 Black Binding Post Post
1 J6 White Binding Post Post
1 LED1 GREEN / RED SMT/3MM/2.5MM/4LEAD
2 L1,L2 600nH 5T, AWG14 250WD/700LN Micrometals T60-8/90
1 L3 1uH 5T, AWG19 128WD/307OD Micrometals
2 Q1,Q3 HUF76139 TO263AB_M Fairchild
2 Q2,Q4 HUF76145 TO263AB_M Fairchild
3 Q5, Q6, Q7 2N7002 SM/SOT23_123 Various
2 Q9,Q8 HUF76129D3S TO252AA/DPAK Fairchild

0.1uF, 25V, X7R
Ceramic

Ceramic

Ceramic

NPO Ceramic

NPO Ceramic

NPO Ceramic

22uF, 6.3V, X5R
Ceramic

X7R Ceramic

Ceramic

X5R Ceramic

P0805 Various

P0805 Various

P0805 Various

P0805 Various

P0805 Various

P0805 Various

P1206 Various

P0805 Various

Sanyo
OS CON

P1206

P1206

Various

Various

ZETEX BAV99TA
Molex or

Jameco
Burndy KPA8CTP
Johnson 111-0702-001
Johnson 111-0703-001
Johnson 111-0701-001
Panasonic LN2162C13-(TR)

4SP1500M

39-29-9202
147379

T50-52

R2,R4 Not populated P1206

2

1 R5 1K, 5% P0805 Various
1R6 10Ω, 5% P0805 Various

8

ISL6560/62 Evaluation Board

TABLE 1. Bill of Materials (contiued)

1 R7 330Ω, 5% P0805 Various
2 R10,R8 3.3K, 5% P0805 Various
1 R9 120K, 5% P0805 Various
1 R11 22K, 5% P0805 Various
1 R12 15K, 5% P0805 Various
1 R13 5mΩ, 1% P2512 Panasonic ERJM1WSF5M0U,

1 R15 5mΩ, 1% for

ISL6562 only

1 R14 20Ω, 5% P0805 Various
2 R16,R18 324Ω, 1% P0603 Various
2 R26,R17 732Ω, 1% P0603 Various
1 R19 46.4k, 1% P0603 Various
1 R20 402 1% P0603 Various
2 R21, R25 Not Populated P2512

2 R22, R24 50mΩ, 1% P2512 Vishay WSL2512, 0.05 1%
1 R23 33.2Ω, 1% P0603 Various
1 R27 4.3K, 5% P0805 Various
2 R28, R29 10K, 5% P0603 Various
2 R30, R31 100Ω, 1% P0603 Various
1 SW1 SW DIP-5 DIPSW.100/10/W.300/L.550
1 SW2 DPST DPST_SWITCH

P2512 Not populated. Only
populated for ISL6562
operation

Panasonic ERJM1WSF5M0U,

CTS 2085
CK GT11MSCK

0.005 1%

0.005 1%

1 SW4,SW4A SW DIP-2 SPST_SWITCHs

11 TP1,TP2,TP4,TP5,TP6,TP7

TP8,TP9,TP10,TP11,TP12,
3 TP3, TP14 Test Probe TP\PROBE-SOCKET
2 U1,U2 HIP6601ECB 8L\EPAD\SOIC
1 U3 ISL6560/62Usingan

1 U4 HIP2100 8L\SOIC
1 PC Board 4 layers 2 0z Copper

TEST POINTS TP

16L\SOIC
ISL6562 - Populate
R15 with resistor

9

Grayhill 76SB02
Keystone 5002

Tektronix 131-4353-00
Intersil
Intersil

Intersil
Various

ISL6560/62 Evaluation Board

ISL6560 Supply Design Sequence

The ISL6560 data sheet describes in more detail the following equations. There are several changes from the computations in
the body of the data sheet. First, an operating frequency of 400kHz was chosen. Next, this design sequence shows the method of
setting the initial no load voltage at the DAC setting and offsetting the no load voltage 15mV abovethe programmed DACvoltage.

A. Specifications:

Output Current: 40A

Input Voltage: 12V
Output Voltage: VDAC + 15mV
Output Voltage for Calculations:
V

= 1.8V + 15mV

DAC

Droop Voltage: 65mV
Oscillator Frequency: 400kHz (fSW)

B. Calculate R

R

OUT

:

OUT

V

DROOP

--------------------------- ­I

OUT

65mV

---------------- 1.63mΩ===
40A

C. Determine Frequency Setting Capacitor CT:.

3000

1000

FREQUENCY (kHz)

100

FIGURE A. OSCILLATOR FREQUENCY vs. TIMING CAPACITOR

100 150 200 250 3000 50 350 400 450 500

CAPACITOR CT (pF)

From curve above, for 400kHz use 120pF.

D. Select Inductor Ripple Current (∆IL):

Choose 40% of IOUT

∆IL40A 0.4× 16A==

Or 8A / Channel

E. Determine the Inductors:

VINV

L

---------------------------------­f

SW

----------- -

2

–

×

OUT

∆I

L

V

×

-----------------

OUT

V

IN

12V 1.8V–

----------------------------------­200kHz 8A×

1.8V

×==

-----------­12V

956nH=

F. Output Capacitors:

Capacitor

Sonya 1500µF, 4V OS-CON Capacitors
have an ESR < 10mΩ

Six capacitors < 1.66mΩ
Total Capacitance = 9mF

≅ 1.63mΩ=

ESRROUT

G. Input Capacitor’s RMS Current:

Use the curve of Figure B

0.3

0.2

0.1

0

CURRENT MULTIPLIER

0

FIGURE B. CURRENT MULTIPLIER vs. DUTY CYCLE

For 40A with a duty cycle (D) of:

D

The multiplier from Figure B is 0.24.

I

RMS

Pensioned 470µF, 16V Rubdown ZA series capacitors
have a RMS current rating of 1.6A.
Six capacitors were selected.

H. Current Sense Resistor (R

R

SENSE

I. R

J. R

K. V

VSET 1V

Dissipation:

SENSE

I

RMSIPEAK

Power∴ I

Where: I

Power 24A=

Selection:

L

ni R

R

------------------------------------------

L

gm R

ni = ∆V

am Amplifier Gain

Computation for No Load Voltage = DAC:

SET

V

, the no load voltage programed to the DAC voltage

OUT

, the voltage set at the COMP pin

V

SET

0.1 0.2 0.3 0.4 0.5

V

OUT

----------------­V

IN

DUTY CYCLE (V

1.8V

------------ 0.15===
12V

O

/ VIN)

0.24=40A× 9.6A=

SENSE

V

CS TH()MIN

----------------------------------------------- ­I

I

---------------

OUT

2

RIPPLE

-------------------------+

2

142mV

------------------------ - 5.07mΩ===
20A 8A+

Use a 5mΩ resistor

D=

2

D× R

×=

P

= 20A + 4A = 24A

P

2

432mW=

×

SENSE

OUT

COMP

SENSE

(Using half 0f ripple current

0.15× 5mΩ×
Used a 1W resistor

12.5 5mΩ×

------------------------------------------------------- - 8.7kΩ== =

2××

2.2mS 1.63mΩ 2××

/ VCS(from data sheet)

gm RL× 2.2mS 8.7k 19.1=×==

I

RIPPLERSENSE

--------------------------------------------------------------------- -+=
8A 5mΩ 12.5××

1V

---------------------------------------------+=

2

2

ni××

1V 250mV+= 1.25V=

):

10

ISL6560/62 Evaluation Board

L. gm Amplifier Output Load Network:

V

V

REF = 3V

R

U

||

RUR

RL=

B

To COMP pin,

M. V

this voltage is V

R

B

R

B

R

B

Computation for No Load Voltage = DAC +15mV:

SET

V

, no load voltage to be set 15mV above

OUT

SET

V

SET

--------------------------------------- -=R
V

–

REFVSET

1.25V

-----------------------------= 20.9k× 14.9k=
3V 1.25V–

programed DAC voltage
Added output voltage of the gm amplifier will be:

15mV X gm Amplifier gain = 15mv x 19.1 = 287mV

I

V

SET

RIPPLERSENSE

1V

--------------------------------------------------------------------- - 287mV++=
8A 5mΩ 12.5××

---------------------------------------------+= 287mV+

1V

2

2

1V 250mV+= 287mV+ 1.536V=

REF

R

---------------- -=R

U

V

SET

3V

R

--------------- -= 8.7k× 20.9k=

U

1.25V

×

U

N. gm Amplifier Output Load Network:

V

V

×

L

REF = 3V

R

U

||

RUR

RL=

B

To COMP pin,

this voltage is V

R

B

R

B

R

B

and RC Selection:

O. C

C

V

REF = 3V

ni××

C

C

R

C

R

C

------------------------------------------

C

R

U

To COMP pin

R

B

OUTCOUT

R

SET

V

SET

--------------------------------------- -=R
V

–

REFVSET

1.54V

-----------------------------= 16.9k× 17.8k=
3V 1.54V–

×

R

L

||

RUR

= 0.5 x RL= 0.5 x 8.7k = 4.35k

C

RL=

B

REF

R

---------------- -=R

U

R

U

×

1.63mΩ 9mF×

---------------------------------------- - 1.68nF===

×

V

SET

3V

--------------- -= 8.7k× 16.9K=

1.54V

L

U

8.7k

AC Equivalent

R

C

COMP pin

R

L

C

C

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