intersil ISL6551 DATA SHEET

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ISL6551

Data Sheet January 3, 2006

ZVS Full Bridge PWM Controller

The ISL6551 is a zero voltage switching (ZVS) full-bridge PWM controller designed for isolated power systems. This part implements a unique control algorithm for fixedfrequency ZVS current mode control, yielding high efficiency with low EMI. The two lower drivers are PWM-controlled on the trailing edge and employ resonant delay while the two upper drivers are driven at a fixed 50% duty cycle.

This IC integrates many features in both 6x6 mm 28-lead SOIC packages to yield a complete and sophisticated power supply solution. Control features include programmable soft-start for controlled start-up, programmable resonant delay for zero voltage switching, programmable leading edge blanking to prevent false triggering of the PWM comparator due to the leading edge spike of the current ramp, adjustable ramp for slope compensation, drive signals for implementing synchronous rectification in high output current, ultra high efficiency applications, and current share support for paralleling up to 10 units, which helps achieve higher reliability and availability as well as better thermal management. Protective features include adjustable cycle-by-cycle peak current limiting for overcurrent protection, fast short-circuit protection (in hiccup mode), a latching shutdown input to turn off the IC completely on output overvoltage conditions or other extreme and undesirable faults, a non-latching enable input to accept an enable command when monitoring the input voltage and thermal condition of a converter, and VDD under voltage lockout with hysteresis. Additionally, the ISL6551 includes high current high-side and low-side totem-pole drivers to avoid additional external drivers for moderate gate capacitance (up to 1.6nF at 1MHz) applications, an uncommitted high bandwidth (10MHz) error amplifier for feedback loop compensation, a precision bandgap reference with ±1.5% (ISL6551AB) or ±1% (ISL6551IB) tolerance over recommended operating conditions, and a ±5% “in regulation” monitor.

In addition to the ISL6551, other external elements such as transformers, pulse transformers, capacitors, inductors and Schottky or synchronous rectifiers are required for a complete power supply solution. A detailed 200W telecom power supply reference design using the ISL6551 with companion Intersil ICs, Supervisor And Monitor ISL6550 and Half-bridge Driver HIP2100, is presented in Application Note AN1002.

QFN and

FN9066.5

Features

• High Speed PWM (up to 1MHz) for ZVS Full Bridge Control

• Current Mode Control Compatible

• High Current High-Side and Low-Side Totem-Pole Drivers

• Adjustable Resonant Delay for ZVS

• 10MHz Error Amplifier Bandwidth

• Programmable Soft-Start

• Precision Bandgap Reference

• Latching Shutdown Input

• Non-latching Enable Input

• Adjustable Leading Edge Blanking

• Adjustable Dead Time Control

• Adjustable Ramp for Slope Compensation

• Fast Short-Circuit Protection (Hiccup Mode)

• Adjustable Cycle-by-Cycle Peak Current Limiting

• Drive Signals to Implement Synchronous Rectification

• VDD Under-voltage Lockout

• Current Share Support

• ±5% “In Regulation” Indication

• QFN Package:

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Full-Bridge and Push-Pull Converters

• Power Supplies for Off-line and Telecom/Datacom

• Power Supplies for High End Microprocessors and Servers

In addition, the ISL6551 can also be designed in push-pull converters using all of the features except the two upper drivers and adjustable resonant delay features.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6551

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Ordering Information

PART

NUMBER

ISL6551IB 0 to 85 28 Ld SOIC M28.3

ISL6551IBZ (Note) 0 to 85 28 Ld SOIC (Pb-free) M28.3

ISL6551IR 0 to 85 28 Ld 6x6 QFN L28.6x6

ISL6551IRZ (Note) 0 to 85 28 Ld 6x6 QFN

ISL6551ABZ (Note) -40 to 105 28 Ld SOIC (Pb-free) M28.3

ISL6551AR -40 to 105 28 Ld 6x6 QFN L28.6x6

ISL6551ARZ (Note) -40 to 105 28 Ld 6x6 QFN

TEMP

RANGE (°C) PACKAGE

(Pb-free)

PKG.

DWG. #

L28.6x6

Pinouts

28 PIN WIDE BODY (SOIC)

TOP VIEW

VDD

VSS

R_RESDLY

R_RA

ISENSE

PKILIM

BGREF

R_LEB

CS_COMP

CSS

EANI

EAI

EAO

1 2 3 4 5 6 7 8

9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VDDP1 VDDP2 PGND UPPER1 UPPER2 LOWER1 LOWER2 SYNC1 SYNC2 ON/OFF DCOK LATSD SHARE

Ordering Information (Continued)

PART

NUMBER

ISL6551EVAL1 Evaluation Platform (ISL6551IR only)

Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

R_RESDLY

ISENSE

PKILIM

BGREF

R_LEB

CS_COMP

R_RA

TEMP

RANGE (°C) PACKAGE

28 PIN (QFN)

TOP VIEW

VSS

VDD

VDDP1

VDDP2

28 27 26 25 24 23 22

8 9 10 11 12 13 14

EANI

EAI

EAO

LATSD

CSS

PGND

DCOK

PKG.

DWG. #

UPPER1

UPPER2

LOWER1

LOWER2

SYNC1

SYNC2

ON/OFF

FN9066.5

January 3, 2006

ISL6551

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Functional Pin Description

PACKAGE PIN #

PIN SYMBOL FUNCTIONSOIC QFN

1 26 VSS Reference ground. All control circuits are referenced to this pin.

2 27 CT Set the oscillator frequency, up to 1MHz.

3 28 RD Adjust the clock dead time from 50ns to 1000ns.

4 1 R_RESDLY Program the resonant delay from 50ns to 500ns.

5 2 R_RA Adjust the ramp for slope compensation (from 50mV to 250mV).

6 3 ISENSE The pin receives the current information via a current sense transformer or a power resistor.

7 4 PKILIM Set the over current limit with the bandgap reference as the trip threshold.

8 5 BGREF Precision bandgap reference, 1.263V ±2% overall recommended operating conditions.

9 6 R_LEB Program the leading edge blanking from 50ns to 300ns.

10 7 CS_COMP Set a low current sharing loop bandwidth with a capacitor.

11 8 CSS Program the rise time and the clamping voltage with a capacitor and a resistor, respectively.

12 9 EANI Non-inverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).

13 10 EAI Inverting input of Error Amp. It receives the feedback voltage.

14 11 EAO Output of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).

15 12 SHARE This pin is the SHARE BUS connecting with other unit(s) for current share operation.

16 13 LATSD The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD.

17 14 DCOK Power Good indication with a ±5% window.

18 15 ON/OFF This is an Enable pin that controls the states of all drive signals and the soft-start.

19, 20 16, 17 SYNC2, SYNC1 These are the gate control signals for the output synchronous rectifiers.

21, 22 18, 19 LOWER2, LOWER1 Both lower drivers are PWM-controlled on the trailing edge.

23, 24 20, 21 UPPER2, UPPER1 Both upper drivers are driven at a fixed 50% duty cycle.

25 22 PGND Power Ground. High current return paths for both the upper and the lower drivers.

26, 27 23, 24 VDDP2, VDDP1 Power is delivered to both the upper and the lower drivers through these pins.

28 25 VDD Power is delivered to all control circuits including SYNC1 & SYNC2 via this pin.

FN9066.5

January 3, 2006

Functional Block Diagram

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ISL6551

BGREF

PKILIM

R_LEB

R_RESDLY

ISENSE

R_RA

6 5

BANDGAP

REFERENCE

RESODLY

RAMP

ADJUST

VDD 28

UVLO

LEB

ON/OFF 18

SHUTDOWN

LATCH

SHUTDOWN

LATSD 16

LATCH

SOFT

SOFT-

START

CSS 11

UPPER1 DRIVER

UPPER2 DRIVER

VDDP1

UPPER1

UPPER2

EAO

EAI

EANI

CIRCUITS REFERENCED TO VSS

CLOCK

GENERATOR

ERROR AMP

(See Fig. 4)

DC OK

17 DCOK

VSS

CURRENT

CS_COMP

PWM

LOGIC

19 SYNC2

SYNC1

EXTERNAL SINGLE POINT CONNECTION REQUIRED

25 PGND

CIRCUITS REFERENCED TO PGND

LOWER1 DRIVER

LOWER2 DRIVER

VDDP2

LOWER1

LOWER2

FN9066.5

January 3, 2006

ISL6551

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Absolute Maximum Ratings Thermal Information

Supply Voltage VDD, VDDP1, VDDP2 . . . . . . . . . . . . . . -0.3 to 16V

Enable Inputs (ON/OFF, LATSD) . . . . . . . . . . . . . . . . . . . . . . . . VDD

Power Good Sink Current (I ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . . 250V

) . . . . . . . . . . . . . . . . . . . . . . 5mA

DCOK

Thermal Resistance θ

QFN Package (Notes 1, 3). . . . . . . . . . 30 2.5

SOIC Package (Note 2) . . . . . . . . . . . . 55 N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC Lead Tips Only)

Recommended Operating Conditions

Ambient Temperature Range

ISL6551IB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C

ISL6551AB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 105°C

Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . 10.8V to 13.2V

Supply Voltage Range, VDDP1 & VDDP2. . . . . . . . . . . . . . . <13.2V

Maximum Operating Junction Temperature. . . . . . . . . . . . . . . 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379 for details.

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θ

3. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

(°C/W) θJC (°C/W)

Electrical Specifications These specifications apply for VDD = VDDP = 12V and T

(ISL6551AB), Unless Otherwise Stated

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SUPPLY (VDD, VDDP1, VDDP2)

Supply Voltage VDD 10.8 12.0 13.2 V

Bias Current from VDD (ISL6551IB) IDD VDD = 12V (not including drivers current at VDDP) 5 13 18 mA

Bias Current from VDD (ISL6551AB) IDD VDD = 12V (not including drivers current at VDDP) 3 20 mA

Total Current from VDD and VDDP ICC VDD = VDDP = 12V, F = 1MHz, 1.6nF Load 60 mA

UNDER VOLTAGE LOCKOUT (UVLO)

Start Threshold (ISL6551IB) VDD

Start Threshold (ISL6551AB) VDD

Stop Threshold (ISL6551IB) VDD

Stop Threshold (ISL6551AB) VDD

Hysteresis (ISL6551IB) VDD

Hysteresis (ISL6551AB) VDD

CLOCK GENERATOR (CT, RD)

Frequency Range F VDD = 12V (Figure 2) 100 1000 kHz

Dead Time Pulse Width (Note 4) DT VDD = 12V (Figure 3) 50 1000 ns

BANDGAP REFERENCE (BGREF)

Bandgap Reference Voltage (ISL6551IB)

Bandgap Reference Voltage (ISL6551AB)

Bandgap Reference Output Current IREF VDD = 12V, see Block/Pin Functional Descriptions

OFF

HYS

VREF VDD = 12V, 399kΩ pull-up, 0.1µF, after trimming 1.250 1.263 1.280 V

VREF VDD = 12V, 399kΩ pull-up, 0.1µF, after trimming 1.244 1.263 1.287 V

for details

= 0°C to 85°C (ISL6551IB) or -40°C to 105°C

9.2 9.6 9.9 V

9.16 9.94 V

8.03 8.6 8.87 V

7.98 8.92 V

0.3 1 1.9 V

0.27 1.93 V

100 µA

FN9066.5

January 3, 2006

ISL6551

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Electrical Specifications These specifications apply for VDD = VDDP = 12V and T

(ISL6551AB), Unless Otherwise Stated (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

PWM DELAYS (Note 4)

LOW1,2 delay “Rising” LOWR With respect to RESDLY rising 5 ns

LOW1,2 delay “Falling” LOWF Compare Delay @ Verror = Vramp 44 ns

SYNC1,2 delay “Falling” SYNCF With respect to RESDLY falling and with 20pF load 18 ns

SYNC1,2 delay “Rising” SYNCR With respect to CLK rising and with 20pF load 20 ns

ERROR AMPLIFIER (EANI, EAI, EAO) (Note 4)

Unity Gain Bandwidth UGBW 10 MHz

DC Gain DCG 79 dB

Maximum Offset Error Voltage Vos 3.1 mV

Input Common Mode Range Vcm VDD = 12V 0.4 9 V

Common Mode Rejection Ratio CMMR 82 dB

Power Supply Rejection Ratio PSSR 1mA load 95 dB

Maximum Output Source Current ISRC 2 mA

Maximum Lower Saturation Voltage Vsatlow Sinking 0.27mA 125 mV

RAMP ADJUST (R_RA) (Note 4)

Ramp Frequency F 100 1000 kHz

Linear Voltage Ramp, Minimum LVR 50 mV

Linear Voltage Ramp, Maximum 250 mV

Overall Variation 25 %

PEAK CURRENT LIMIT (PKILIM)

Peak Current Shutdown Threshold IpkThr BGREF = 0.1µF, 399kΩ pull-up 1.25 1.263 1.31 V

Peak Current Shutdown Delay (Note 4)

SOFT-START (CSS)

Charge Current Iss Vcss = 0.6V 8 12 µA

Discharge Current Idis 1.6 5.2 mA

Cycle-by-Cycle Current Limit (ISL6551IB)

Cycle-by-Cycle Current Limit (ISL6551AB)

DRIVERS (UPPER1, UPPER2, LOWER1, LOWER2)

Maximum Capacitive Load (each) CL VDD = VDDP = 12V, F = 1MHz,

Turn On Rise Time (ISL6551IB) Tr 1.0nF Capacitive load 8.9 16 ns

Turn On Rise Time (ISL6551AB) Tr 1.0nF Capacitive load 9.2 17 ns

Turn Off Fall Time (ISL6551IB) Tf 1.0nF Capacitive load 6.4 10 ns

Turn Off Fall Time (ISL6551AB) Tf 1.0nF Capacitive load 12 ns

Shutdown Delay (Note 4) T Rising Edge Delay (Note 4) T Falling Edge Delay (Note 4) T

Vsat_sourcing Vsat_high Sourcing 20mA 1.00 V

IpkDel 75 ns

Vclamp 2 8 V

Vclamp 1.9 8.1 V

Thermal Dependence

SD RD FD

1.0nF Capacitive load 14.5 ns

1.0nF Capacitive load 16.4 ns

1.0nF Capacitive load 13.7 ns

Sourcing 200mA 1.35 V

= 0°C to 85°C (ISL6551IB) or -40°C to 105°C

1600 pF

FN9066.5

January 3, 2006

ISL6551

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Electrical Specifications These specifications apply for VDD = VDDP = 12V and T

(ISL6551AB), Unless Otherwise Stated (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Vsat_sinking (ISL6551IB) Vsat_low Sinking 20mA 0.035 V

Sinking 200mA 0.31 V

Vsat_sinking (ISL6551AB) Vsat_low Sinking 20mA 0.04 V

Sinking 200mA 0.5 V

SYNCHRONOUS SIGNALS (SYNC1, SYNC2)

Maximum capacitive load (each) VDD = 12, F = 1MHz 20 pF

PROGRAMMABLE DELAYS (RESDLY, LEB) (Note 4)

Resonant Delay Adjust Range (Figure 7) 50 500 ns

Resonant Delay t

Leading Edge Blanking Adjust Range

Leading Edge Blanking t

LATCHING SHUTDOWN (LATSD)

Fault Threshold VIN 3 V

Fault_NOT Threshold VINN 1.9 V

Time to Set latch (Note 4) TSET 415 ns

ON/OFF (ONOFF)

Turn-off Threshold OFF 0.8 V

Turn-on Threshold ON 2 V

CURRENT SHARE (SHARE, CS_COMP) (Note 4)

Voltage Offset Between Error Amp Voltage of Master and Slave

Maximum Source Current To External Reference

Maximum Correctable Deviation In Reference Voltage Between Master and Slave

Share/Adjust Loop Bandwidth CS BW CS_COMP = 0.1µF 500 Hz

DC OK (DCOK)

Sink Current I

Saturation Voltage V

Input Reference Vref_in 1 5 V

Threshold (relative to Vref_in) OV (Figure 11) 5 %

Recovery (relative to Vref_in) OV (Figure 11) 3 %

Threshold (relative to Vref_in) UV (Figure 11) -5 %

Recovery (relative to Vref_in) UV (Figure 11) -3 %

Transient Rejection (Note 4) TRej 100mV transient on Vout (system implicit rejection

NOTE:

4. Guaranteed by design. Not 100% tested in production.

RESDLY

LEB

Vcs_offset SHARE = 30K 30 mV

Ics_source SHARE = 30K 190 µA

DCOK

SATDCOKIDCOK

R_RESDLY = 10K 55 ns

R_RESDLY = 120K 488 ns

(Figure 8) 50 300 ns

R_LEB = 20K 64 ns

R_LEB = 140K 302 ns

R_LEB = 12V 0 ns

SHARE = 30K, Rsource = 1K, OUTPUT REFERENCE = 1 to 5V, (See Figure 10)

= 5mA 0.4 V

and feedback network dependence (Figure 12)

= 0°C to 85°C (ISL6551IB) or -40°C to 105°C

190 mV

5mA

250 µs

FN9066.5

January 3, 2006

Drive Signals Timing Diagrams

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CLOCK

UPPER1

UPPER2

SYNC1

SYNC2

LOWER1

ISL6551

EAO

LOWER2

RAMP ADJUST OUTPUT TO PWM LOGIC

NOTES:

T1 = Leading edge blanking T2 = T4 = Resonant delay T3 = T5 = dead time In the above figure, the values for T1 through T5 are exaggerated for demonstration purposes.

T2 T3 T4 T5

Timing Diagram Descriptions

The two upper drivers (UPPER1 and UPPER2) are driven at a fixed 50% duty cycle and the two lower drivers (LOWER1 and LOWER2) are PWM-controlled on the trailing edge, while the leading edge employs resonant delay (T2 and T4). In current mode control, the sensed switch (FET) current (I

LOWER1

and I

LOWER2

) is processed in the Ramp Adjust and Leading Edge Blanking (LEB) circuits and then compared to a control signal (EAO). Spikes, due to parasitic elements in the bridge circuit, would falsely trigger the comparator generating the PWM signal. To prevent false triggering, the leading edge of the sensed current signal is blanked out by T1, which can be programmed at the R_LEB pin with a resistor. Internal switches gate the analog input to the PWM comparator, implementing the blanking function that eliminates response degrading delays which would be caused

if filtering of the current feedback was incorporated. The dead time (T3 and T5) is the delay to turn on the upper FET (UPPER1/UPPER2) after its corresponding lower FET (LOWER1/LOWER2) is turned off when the bridge is operating at maximum duty cycle in normal conditions, or is responding to load transients or input line dipping conditions. Therefore, the upper and lower FETs that are located at the same side of the bridge can never be turned on together, which eliminates shoot-through currents. SYNC1 and SYNC2 are the gate control signals for the output synchronous rectifiers. They are biased by VDD and are capable of driving capacitive loads up to 20pF at 1MHz clock frequency (500kHz switching frequency). External drivers with high current capabilities are required to drive the synchronous rectifiers, cascading with both synchronous signals (SYNC1 and SYNC2).

EAO

FN9066.5

January 3, 2006

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