intersil ISL6545, ISL6545A DATA SHEET

®

ISL6545, ISL6545A

Data Sheet November 15, 2006

5V or 12V Single Synchronous Buck
Pulse-Width Modulation (PWM) Controller

The ISL6545 makes simple work out of implementing a
complete control and protection scheme for a DC/DC stepdown
converter driving N-channel MOSFETs in a synchronous buck
topology. Since it can work with either 5V or 12V supplies, this
one IC can be used in a wide variety of applications within a
system. The ISL6545 integrates the control, gate drivers, output
adjustment, monitoring and protection functions into a single 8
Ld SOIC or 10 Ld DFN package.

The ISL6545 provides single feedback loop, voltage-mode
control with fast transient response. The output voltage can be
precisely regulated to as low as 0.6V , with a maximum
tolerance of ±1.0% over temperature and line voltage
variations. A selectable fixed frequency oscillator (ISL6545 for
300kHz; ISL6545A for 600kHz) reduces design complexity,
while balancing typical application cost and efficiency.

The error amplifier features a 20MHz gain-bandwidth
product and 9V/μs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.

Protection from overcurrent conditions is provided by
monitoring the r
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.

of the lower MOSFET to inhibit PWM

DS(ON)

FN6305.3

Features

• Operates from +5V or +12V Supply Voltage (for bias)

- 1.0V to 12V V

Input Range (up to 20V possible with

IN

restrictions; see Input Voltage Considerations)

- 0.6V to V

- Integrated Gate Drivers use V

Output Range

IN

(5V to 12V)

CC

- 0.6V Internal Reference; ±1.0% tol erance

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

- Drives N-Channel MOSFETs

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Cycle

• Lossless, Programmable Overcurrent Protection

- Uses Lower MOSFET’s r

DS(ON)

• Small Converter Size in 8 Ld SOIC or 10 Ld DFN

- 300kHz or 600kHz Fixed Frequency Oscillator

- Fixed Internal Soft-Start, Capable into a Pre-biased
Load

- Integrated Boot Diode

- Enable/Shutdown Function on COMP/SD Pin

- Output Current Sourcing and Sinking

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

Pinout

BOOT

UGATE

GND

LGATE/OCSET

ISL6545 (10 LD 3x3 DFN)

BOOT

UGATE

N/C

GND

LGATE/OCSET

ISL6545 (SOIC)

TOP VIEW

1
2
3
4

TOP VIEW

1
2

GND

3
4
5

1

8
7
6
5

10

9
8
7

6

PHASE
COMP/SD
FB
VCC

PHASE
COMP/SD

FB
N/C

VCC

• Power Supplies for Microprocessors or Peripherals

- PCs, Embedded Controllers, Memory Supplies

- DSP and Core Communications Processor Supplies

• Subsystem Power Supplies

- PCI, AGP; Graphics Cards; Digital TV

- SSTL-2 and DDR/DDR2/DDR3 SDRAM Bus
Termination Supply

• Cable Modems, Set Top Boxes, and DSL Modems

• Industrial Power Supplies; General Purpose Supplies

• 5V or 12V-Input DC/DC Regulators

• Low-Voltage Distributed Power Supplies

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2006. All Rights Reserved

ISL6545, ISL6545A

*

Ordering Information

TEMP.

PAR T NUMB ER PART M ARKI NG

ISL6545CBZ* (300kHz) 6545 CBZ 0 to +70 8 Ld SOIC (Pb-free) M8.15
ISL6545ACBZ*(600kHz)

6545 ACBZ 0 to +70 8 Ld SOIC (Pb-free) M8.15

(Note)
ISL6545IBZ* (300kHz)

6545 IBZ -40 to +85 8 Ld SOIC (Pb-free) M8.15

(Note)
ISL6545AIBZ* (600kHz)

6545 AIBZ -40 to +85 8 Ld SOIC (Pb-free) M8.15

(Note)
ISL6545CRZ* (300kHz)

545Z 0 to +70 10 Ld DFN (Pb-free) L10.3x3C

(Note)
ISL6545ACRZ* (600kHz)

45AZ 0 to +70 10 Ld DFN (Pb-free) L10.3x3C

(Note)
ISL6545IRZ* (300kHz)

45IZ -40 to +85 10 Ld DFN (Pb-free) L10.3x3C

(Note)
ISL6545AIRZ* (600kHz)

5ARZ -40 to +85 10 Ld DFN (Pb-free) L10.3x3C

(Note)
ISL6545EVAL1 Evaluation Board (SO-8)
ISL6545AEVAL1 Evaluation Board (SO-8)

*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

RANGE (°C) PACKAGE PKG. DWG. #

2

FN6305.3

November 15, 2006

Block Diagram

LGATE/OCSET

FB

COMP/SD

Typical Application

21.5μA

TO

5V int.

20μA

SAMPLE

AND

HOLD

0.6V

0.4V

ISL6545, ISL6545A

+

­OC

COMPARATOR

ERROR

AMP

DIS

+

-

+

-

FIXED 300 (or 600)kHz

PWM

COMPARATOR

OSCILLATOR

POR AND

SOFT-START

+

-

INTERNAL

REGULATOR

5V int.

INHIBIT

PWM

CONTROL

LOGIC

DIS

GND

GATE

VCC

D

BOOT

VCC

20kΩ

BOOT

UGATE

PHASE

LGATE/OCSET

R

OFFSET

R

F

C

F

V

CC

5V or 12V

C

DCPL

COMP/SD

C

I

Type II
compensation
shown

ISL6545

7

63

FB

5

VCC

GND

R

S

1

8

BOOT

PHASE

UGATE

2

LGATE/OCSET

4

R

OCSET

C

BOOT

L

OUT

C

OUT

V

IN

1V-12V

C

+V

BULK

O

C

HF

3

FN6305.3

November 15, 2006

ISL6545, ISL6545A

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V

BOOT Voltage, V
UGATE Voltage V
LGATE/OCSET Voltage, V
PHASE Voltage, V
Upper Driver Supply Voltage, V
Clamp Voltage, V

FB, COMP/SD Voltage. . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 6V

. . . . . . . . . . . . . . . . . . . .GND - 0.3V to 36V

BOOT

. . . . . . . .V

UGATE

LGATE/OCSET

. . . . . . . . . .GND - 0.3V to V

PHASE

BOOT

BOOT

- VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .24V

- 0.3V to V

PHASE

GND - 0.3V to VCC + 0.3V

- V

. . . . . . . . . . . . .15V

PHASE

BOOT

BOOT

+ 0.3V

+ 0.3V

ESD Classification, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV

ESD Classification, MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150V

ESD Classification, CDM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV

Operating Conditions

Supply Voltage, VCC . . . . +5V ±10%, +12V ±20%, or 6.5V to 14.4V

Ambient Temperature Range

ISL6545C, ISL6545AC. . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL6545I, ISL6545AI . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

is measured with the component mounted on a high effective thermal conductivity test board in free air, with “direct attach” features. See

2. θ

JA

Tech Brief TB379 for details.

3. For θ

4. Guaranteed by design; not production tested

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance θ

(°C/W) θJC (°C/W)

JA

SOIC Package (Note 1) . . . . . . . . . . . . 95 N/A

DFN Package (Note 3). . . . . . . . . . . . . 44 5.5

Maximum Junction Temperature

(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C

Maximum Lead Temperature

(Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)

Electrical Specifications Test Conditions: V

= 12V, TJ = 0 to 85°C, Unless Otherwise Noted.

CC

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SUPPLY CURRENT

V

CC

Input Bias Supply Current I

VCC

VCC = 12V; disabled 4 5.2 7 mA

POWER-ON RESET

Rising V
V

CC

POR Threshold V

CC

POR

POR Threshold Hysteresis 0.30 0.35 0.40 V

3.9 4.1 4.3 V

OSCILLATOR

Switching Frequency f

OSC

ISL6545C 270 300 330 kHz
ISL6545I 240 300 330 kHz

f

OSC

ISL6545AC 540 600 660 kHz
ISL6545AI 510 600 660 kHz

Ramp Amplitude (Note 4) ΔV

OSC

1.5 V

REFERENCE

Reference Voltage Tolerance ISL6545C -1.0 - +1.0 %

ISL6545I -1.5 - +1.5 %

Nominal Reference Voltage V

REF

0.600 V

ERROR AMPLIFIER

DC Gain (Note 4) GAIN - 96 - dB
Gain-Bandwidth Product (Note 4) GBWP - 20 - MHz
Slew Rate (Note 4) SR - 9 - V/μs

GATE DRIVERS

Upper Gate Source Impedance R
Upper Gate Sink Impedance R
Lower Gate Source Impedance R

UG-SRChVCC
UG-SNKhVCC
LG-SRChVCC

= 14.5V; I = 50mA - 3.0 - Ω
= 14.5V; I = 50mA - 2.7 - Ω
= 14.5V; I = 50mA - 2.4 - Ω

P-P

4

FN6305.3

November 15, 2006

ISL6545, ISL6545A

Electrical Specifications Test Conditions: V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Lower Gate Sink Impedance R
Upper Gate Source Impedance R
Upper Gate Sink Impedance R
Lower Gate Source Impedance R
Lower Gate Sink Impedance R

PROTECTION/DISABLE

OCSET Current Source I

Disable Threshold (COMP/SD pin) V

LG-SNKhVCC

UG-SRClVCC
UG-SNKlVCC
LG-SRClVCC
LG-SNKlVCC

OCSET

DISABLE

= 12V, TJ = 0 to 85°C, Unless Otherwise Noted. (Continued)

CC

= 14.5V; I = 50mA - 2.0 - Ω
= 4.25V; I = 50mA - 3.5 - Ω
= 4.25V; I = 50mA - 2.7 - Ω
= 4.25V; I = 50mA - 2.75 - Ω
= 4.25V; I = 50mA - 2.1 - Ω

ISL6545C; LGATE/OCSET = 0V 19.5 21.5 23.5 μA
ISL6545I; LGATE/OCSET = 0V 18.0 21.5 23.5 μA

Functional Pin Description (SOIC,DFN)

VCC (SOIC Pin 5, DFN Pin 6)

This pin provides the bias supply for the ISL6545, as well as
the lower MOSFET’s gate, and the BOOT voltage for the
upper MOSFET’s gate. An internal 5V regulator will supply
bias if V
BOOT will still be sourced by VCC). Connect a well­decoupled 5V or 12V supply to this pin.

FB (SOIC Pin 6, DFN Pin 8)

This pin is the inverting input of the internal error amplifier. Use
FB, in combination with the COMP/SD pin, to compensate the
voltage-control feedback loop of the converter. A resistor divider
from the output to GND is used to set the regulation voltage.

GND (SOIC Pin 3, DFN Pin 4)

This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available. For the DFN package, Pin
4 MUST be connected for electrical GND; the metal pad
under the package should also be connected to the GND
plane for thermal conductivity.

PHASE (SOIC Pin 8, DFN Pin 10)

Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.

UGATE (SOIC Pin 2, DFN Pin 2)

Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.

BOOT (SOIC Pin 1, DFN Pin 1)

This pin provides ground referenced bias voltage to the upper
MOSFET driver. A bootstrap circuit is used to create a voltage
suitable to drive an N-channel MOSFET (equal to V
the on-chip BOOT diode voltage drop), with respect to PHASE.

rises above 6.5V (but the LGATE/OCSET and

CC

CC

minus

0.375 0.400 0.425 V

COMP/SD (SOIC Pin 7, DFN Pin 9)

This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/SD, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.

Pulling COMP/SD low (V

DISABLE

= 0.4V nominal) will
shut-down (disable) the controller, which causes the
oscillator to stop, the LGATE and UGATE outputs to be held
low, and the soft-start circuitry to re-arm. The external pull­down device will initially need to overcome up to 5mA of
COMP/SD output current. However, once the IC is disabled,
the COMP output will also be disabled, so only a 20µA
current source will continue to draw current.

When the pull-down device is released, the COMP/SD pin
will start to rise, at a rate determined by the 20µA charging
up the capacitance on the COMP/SD pin. When the
COMP/SD pin rises above the V

DISABLE

trip point, the

ISL6545 will begin a new Initialization and soft-start cycle.

LGATE/OCSET (SOIC Pin 4, DFN Pin 5)

Connect this pin to the gate of the lower MOSFET; it provides
the PWM-controlled gate drive (from V

). This pin is also

CC

monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.

During a short period of time following Power-On Reset
(POR) or shut-down release, this pin is also used to
determine the overcurrent threshold of the converter.
Connect a resistor (R

) from this pin to GND. See the

OCSET

Overcurrent Protection section for equations. An
overcurrent trip cycles the soft-start function, after two
dummy soft-start time-outs. Some of the text describing the
LGATE function may leave off the OCSET part of the name,
when it is not relevant to the discussion.

N/C (DFN only; Pin 3, Pin 7)

These two pins in the DFN package are No Connect.

5

FN6305.3

November 15, 2006

ISL6545, ISL6545A

Functional Description

Initialization (POR and OCP sampling)

Figure 1 shows a simplified timing diagram. The Power-On­Reset (POR) function continually monitors the bias voltage at
the V
(V
Overcurrent Protection (OCP) sample and hold operation
(while COMP/SD is ~1V). When the sampling is complete,
V

If the COMP/SD pin is held low during power-up, that will just
delay the initialization until it is released, and the COMP/SD
voltage is above the V

GND>

GND>

GND>

GND>

pin. Once the rising POR threshold is exceeded

CC

~4V nominal), the POR function initiates the

POR

begins the soft-start ramp.

OUT

DISABLE

~4V POR

trip point.

COMP/SD (1V/DIV)

VCC (2V/DIV)

V

(1V/DIV)

OUT

hold at T3, the soft-start operation is initiated, and the output
voltage ramps up between T4 and T5.

LGATE

STARTS

SWITCHING

COMP/SD (0.25V/DIV)

0.4V

LGATE/OCSET (0.25V/DIV)

GND>

GND>

GND>

GND>

T0 T1 T2 T3 T4 T5

FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION

3.4ms3.4ms 0 - 3.4ms

V

OUT

(0.5V/DIV)

6.8ms

Soft-Start and Pre-Biased Outputs

Functionally, the sof t-start internally ramps the reference on the
non-inverting terminal of the error amp from zero to 0.6V in a
nominal 6.8ms The output voltage will thus follow the ramp,
from zero to final value, in the same 6.8ms (the actual ramp
seen on the V
some initialization timing, between T3 and T4).

will be less than the nominal time, due to

OUT

FIGURE 1. POR AND SOFT-START OPERATION

Figure 2 shows a typical power-up sequence in more detail.
The initialization starts at T0, when either VCC rises above
V

, or the COMP/SD pin is released (after POR). The

POR

COMP/SD will be pulled up by an internal 20µA current
source, but the timing will not begin until the COMP/SD
exceeds the V

DISABLE

trip point (at T1). The external
capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20µA current source will charge the COMP/SD pin. With
typical values, it should add a small delay compared to the
soft-start times. The COMP/SD will continue to ramp to ~1V.

From T1, there is a nominal 6.8ms delay, which allows the V

CC

pin to exceed 6.5V (if rising up towards 12V), so that the
internal bias regulator can turn on cleanly. At the same time, the
LGA TE/OCSET pin is initialized, by disabling the LGA TE driver
and drawing I

(nominal 21.5μA) through R

OCSET

OCSET

. This
sets up a voltage that will represent the OCSET trip point. At
T2, there is a variable time period for the OCP sample and hold
operation (0 to 3.4ms nominal; the longer time occurs with the
higher overcurrent setting). The sample and hold uses a digital
counter and DAC to save the voltage, so the stored value does
not degrade, for as long as the V

is above V

CC

POR

. See the
Overcurrent Protection on page 7 for more details on the
equations and variables. Upon the completion of sample and

The ramp is created digitally, so there will be 64 small discrete
steps. There is no simple way to change this ramp rate
externally, and it is the same for either frequency version of the
IC (300kHz or 600kHz).

After an initialization period (T3 to T4), the error amplifier
(COMP/SD pin) is enabled, and begins to regulate the
converter’s output voltage during soft-start. The oscillator’s
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitors. When the internally generated
soft-start voltage exceeds the reference voltage (0.6V), the soft­start is complete, and the output should be in regulation at the
expected voltage. This method provides a rapid and controlled
output voltage rise; there is no large inrush current charging the
output capacitors. The entire start-up sequence from POR
typically takes up to 17ms; up to 10.2ms for the delay and OCP
sample, and 6.8ms for the soft-start ramp.

Figure 3 shows the normal curve in blue; initialization begins
at T0, and the output ramps between T1 and T2. If the output
is pre-biased to a voltage less than the expected value, as
shown by the magenta curve, the ISL6545 will detect that
condition. Neither MOSFET will turn on until the soft-start
ramp voltage exceeds the output; V

starts seamlessly

OUT

ramping from there. If the output is pre-biased to a voltage
above the expected value, as in the red curve, neither
MOSFET will turn on until the end of the soft-start, at which
time it will pull the output voltage down to the final value. Any

6

FN6305.3

November 15, 2006

ISL6545, ISL6545A

resistive load connected to the output will help pull down the
voltage (at the RC rate of the R of the load and the C of the
output capacitance).

V

OVER-CHARGED

OUT

V

PRE-BIASED

OUT

V

NORMAL

GND>GND>

GND>

If the V
supply that comes up after V
through its cycle, but with no output voltage ramp. When V
turns on, the output would follow the ramp of the V

OUT

T0 T1 T2

FIGURE 3. SOFT-START WITH PRE-BIAS

to the upper MOSFET drain is from a different

IN

, the soft-start would go

CC

IN

IN

(at
close to 100% duty cycle, with COMP/SD pin >4V), from
zero up to the final expected voltage. If V

is too fast, there

IN

may be excessive inrush current charging the output
capacitors (only the beginning of the ramp, from zero to
V

matters here). If this is not acceptable, then consider

OUT

changing the sequencing of the power supplies, or sharing
the same supply, or adding sequencing logic to the
COMP/SD pin to delay the soft-start until the V

supply is

IN

ready (see Input Voltage Considerations).
If the IC is disabled after soft-start (by pulling COMP/SD pin

low), and then enabled (by releasing the COMP/SD pin),
then the full initialization (including OCP sample) will take
place. However, that there is no new OCP sampling during
overcurrent retries.

Following POR (and 6.8ms delay), the ISL6545 initiates the
Overcurrent Protection sample and hold operation. The
LGATE driver is disabled to allow an internal 21.5μA current
source to develop a voltage across R

OCSET

. The ISL6545
samples this voltage (which is referenced to the GND pin) at
the LGATE/OCSET pin, and holds it in a counter and DAC
combination. This sampled voltage is held internally as the
Overcurrent Set Point, for as long as power is applied, or
until a new sample is taken after coming out of a shut-down.

The actual monitoring of the lower MOSFET’s on-resistance
starts 200ns (nominal) after the edge of the internal PWM
logic signal (that creates the rising external LGATE signal).
This is done to allow the gate transition noise and ringing on
the PHASE pin to settle out before monitoring. The monitoring
ends when the internal PWM edge (and thus LGATE) goes
low. The OCP can be detected anyw here withi n the above
window.

If the regulator is running at high UGATE duty cycles (around
75% for 600kHz or 87% for 300kHz operation), then the
LGATE pulse width may not be wide enough for the OCP to
properly sample the r

. For those cases, if the LGAT E

DS(ON)

is too narrow (or not there at all) for 3 consecutive pulses,
then the third pulse will be stretched and/or inserted to the
425ns minimum width. This allows for OCP monitoring every
third pulse under this condition. This can introduce a small
pulse-width error on the output voltage, which will be
corrected on the next pulse; and the output ripple voltage will
have an unusual 3-clock pattern, which may look like jitter.
This is not necessarily a problem; it is more of a compromise
to maintain OCP at the higher duty cycles. If the OCP is
disabled (by choosing a too-high value of R

OCSET

, or no
resistor at all), then the pulse stretching feature is also
disabled. Figure 4 illustrates the LGATE pulse width
stretching, as the width gets smaller.

> 425 ns

If the output is shorted to GND during soft-start, the OCP will
handle it, as described in the next section.

Overcurrent Protection (OCP)

The overcurrent function protects the converter from a shorted
output by using the lower MOSFET’s on-resistance, r
to monitor the current. A resistor (R

OCSET

) programs the
overcurrent trip level (see Typical Applicatio n diagram). Th is
method enhances the converter’s efficiency and reduces cost
by eliminating a current sensing resistor. If overcurrent is
detected, the output immediately shuts off, it cycles the so f t­start function in a hiccup mode (2 dummy sof t-s t ar t ti me -outs,
then up to one real one) to provide fault protection. If the
shorted condition is not removed, this cycle will continue
indefinitely.

7

DS(ON)

= 425 ns

,

FIGURE 4. LGATE PULSE STRETCHING

< 425 ns

<< 425 ns

FN6305.3

November 15, 2006

ISL6545, ISL6545A

The overcurrent function will trip at a peak inductor current
(I

determined by:

PEAK)

2I

× xR

I

PEAK

-----------------------------------------------------------=

OCSET

OCSET

r

DS ON()

internal soft-start ramp

where I

is the internal OCSET current source (21.5μA

OCSET

typical). The scale factor of 2 doubles the trip point of the
MOSFET voltage drop, compared to the setting on the
R
due to the MOSFET’s r

resistor. The OC trip point varies in a system mainly

OCSET

variations (over process,

DS(ON)

current and temperature). To avoid overcurrent tripping in
the normal operating load range, find the R

OCSET

resistor

from the equation above with:

1. The maximum r

at the highest junction

DS(ON)

temperature.

2. The minimum I

3. Determine I

PEAK

where ΔI is the output inductor ripple current.

from the specification table.

OCSET

I

for

PEAKIOUT MAX()

+>

ΔI()

----------

2

,

For an equation for the ripple current see Output Inductor
Selection.

The range of allowable voltages detected (2 * I
R

) is 0 to 475mV; but the practical range for typical

OCSET

OCSET

*

MOSFETs is typically in the 20 to 120mV ballpark (500 to
3000Ω). If the voltage drop across R

OCSET

is set too low,
that can cause almost continuous OCP tripping and retry. It
would also be very sensitive to system noise and inrush
current spikes, so it should be avoided. The maximum
usable setting is around 0.2V across R

OCSET

(0.4V across
the MOSFET); values above that might disable the
protection. Any voltage drop across R

OCSET

that is greater
than 0.3V (0.6V MOSFET trip point) will disable the OCP.
The preferred method to disable OCP is simply to remove
the resistor; that will be detected that as no OCP.

Note that conditions during power-up or during a retry may
look different than norma l opera ti on. During power-up in a
12V system, the IC starts operation just above 4V; if the
supply ramp is slow, the soft-start ramp might be over well
before 12V is reached. So with lower gate drive voltages, the
r

of the MOSFETs will be higher during power-up,

DS(ON)

effectively lowering the OCP trip. In addition, the ripple
current will likely be different at lower input voltage.

Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect a small load
transient, and a current spike to charge the output
capacitors. The heig ht of the curre nt spike is not controlled; it
is affected by the step size of the output, the value of the
output capacitors, as well as the IC error amp compensation.
So it is possible to trip the overcurrent with inrush current, in
addition to the normal load and ripple considerations.

V

OUT

(0.5V/DIV)

GND>

6.8ms6.8ms 0 - 6.8ms

T0 T1 T2 T0

FIGURE 5. OVERCURRENT RETRY OPERATION

6.8ms

T1

Figure 5 shows the output response during a retry of an
output shorted to GND. At time T0, the output has been
turned off, due to sensing an overcurrent condition. There
are two internal soft-start delay cycles (T1 and T2) to allow
the MOSFETs to cool down, to keep the average power
dissipation in retry at an acceptable level. At time T2, the
output starts a normal soft-start cycle, and the output tries to
ramp. If the short is still applied, and the current reaches the
OCSET trip point any time during soft-start ramp period, the
output will shut off, and return to time T0 for another delay
cycle. The retry period is thus two dummy soft-start cycles
plus one variable one (which depends on how long it takes to
trip the sensor each time). Figure 5 shows an example
where the output gets about half-way up before shutting
down; therefore, the retry (or hiccup) time will be around
17ms. The minimum should be nominally 13.6ms and the
maximum 20.4ms. If the short condition is finally removed,
the output should ramp up normally on the next T2 cycle.

Star ting up into a sho rted lo ad looks t he same as a re try into
that same shorted load. In both cases, OCP is always
enabled during soft-start; once it trips, it will go into retry
(hiccup) mode. The retry cycle will always have two dummy
time-outs, plus whatever fraction of the real soft-start time
passes before the detection and shutoff; at that point, the
logic immediately starts a new two dummy cycle time-out.

Output Voltage Selection

The output voltage can be programmed to any level between
the 0.6V internal reference, up to the V
ISL6545 can run at near 100% duty cycle at zero load, but
the r

DS(ON)

of the upper MOSFET will effectively limit it to
something less as the load current increases. In addition, the
OCP (if enabled) will also limit the maximum effective duty
cycle.

An external resistor divider is used to scale the output
voltage relative to the internal reference voltage, and feed it
back to the inverting input of the error amp. See the Typical

supply. The

IN

8

FN6305.3

November 15, 2006

ISL6545, ISL6545A

Application schematic on page 2 for more detail; RS is the
upper resistor; R

OFFSET

lower one. The recommended value for R
for accuracy) and then R
equation below. Since R

(shortened to RO below) is the

is 1 - 5kΩ (±1%

OFFSET

S

is chosen according to the

is part of the compensation circuit

S

(see Feedback Compensation section), it is often easier to
change R

OFFSET

to change the output voltage; that way the
compensation calculations do not need to be repeated. If
V

= 0.6V, then R

OUT

OFFSET

can be left open. Output

voltages less than 0.6V are not available.

V

R

OUT

O

----------------------------------

=

V

0.6V

RS0.6V•

OUT

---------------------------

•=

R

0.6V–

O

+()

R

SRO

Input Voltage Considerations

The Typical Application diagram on page 2 shows a
standard configuration where V
12V (±20%); in each case, the gate drivers use the V
voltage for LGATE and BOOT/UGATE. In addition, V
allowed to work anywhere from 6.5V up to the 14.4V
maximum. The V

range between 5.5V and 6.5V is NOT

CC

allowed for long-term reliability reasons, but transitions
through it to voltages above 6.5V are acceptable.

There is an internal 5V regulator for bias; it turns on between

5.5 and 6.5V; some of the delay after POR is there to allow a
typical power supply to ramp up past 6.5V b ef ore th e soft­start ramps begins. This prevents a disturbance on the
output, due to the internal regulator turning on or off. If the
transition is slow (not a step change), the disturbance should
be minimal. So while the recommendation is to not have the
output enabled during the transition through this region, it
may be acceptable. The user should monitor the output for
their application, to see if there is any problem.

The V
as V

to the upper MOSFET can share the same supply

IN

, but can also run off a separate supply or other

CC

sources, such as outputs of other regulators. If V
up first, and the V

is not present by the time the

IN

initialization is done, then the soft-start will not be able to
ramp the output, and the output will later follow part of the
V

ramp when it is applied. If this is not desired, then

IN

change the sequencing of the supplies, or use the
COMP/SD pin to disable V

Figure 6 shows a simple sequencer for this situation. If VCC
powers up first, Q1 will be off, and R3 pulling to V
Q2 on, keeping the ISL6545 in shut-down. When V
on, the resistor divider R1 and R2 determines when Q1 turns
on, which will turn off Q2, and release the shut-down. If V
powers up first, Q1 will be on, turning Q2 off; so the ISL6545
will start-up as soon as V

CC

point is 0.4V nominal, so a wide variety of NFET’s or NPN’s
or even some logic IC’s can be used as Q1 or Q2; but Q2
must be low leakage when off (open-drain or open-collector)

is either 5V (±10%) or

CC

CC

until both supplies are ready.

OUT

CC

comes up. The V

DISABLE

CC

is

CC

powers

will turn

turns

IN

trip

IN

so as not to interfere with the COMP output. Q2 should also
be placed near the COMP/SD pin.

V

R

1

R

2

FIGURE 6. SEQUENCER CIRCUIT

The V

range can be as low as ~1V (for V

IN

0.6V reference). It can be as high as 20V (for V
below V

). There are some restrictions for running high VIN

IN

V

IN

CC

R

3

to COMP/SD

Q

Q

1

2

as low as the

OUT

OUT

just

voltage.
The first consideration for high V

voltage of 36V . The V

(as seen on PHASE) plus VCC (boot

IN

is the maximum BOOT

IN

voltage - minus the diode drop), plus any ringing (or other
transients) on the BOOT pin must be less than 36V. If V
20V, that limits V

plus ringing to 16V.

CC

IN

is

The second consideration for high VIN is the maximum
(BOOT - V
BOOT = V

) voltage; this must be less than 24V. Since

CC

+ VCC + ringing, that reduces to (VIN + ringing)

IN

must be <24V. So based on typical circuits, a 20V maximum
V

is a good starting assumption; the user should verify the

IN

ringing in their particular application.
Another consideration for high V

is duty cycle. Very low

IN

duty cycles (such as 20V in to 1.0V out, for 5% duty cycle)
require component selection compatible with that choice
(such as low r

lower MOSFET, and a good LC output

DS(ON)

filter). At the other extreme (for example, 20V in to 12V out),
the upper MOSFET needs to be low r

DS(ON)

. In addition, if
the duty cycle gets too high, it can affect the overcurrent
sample time. In all cases, the input and output capacitors
and both MOSFETs must be rated for the voltages present.

Switching Frequency

The switching frequency is either a fixed 300 or 600kHz,
depending on the part number chosen (ISL6545 is 300kHz;
ISL6545A is 600kHz; the generic name “ISL6545” may apply
to either in the rest of this document, except when choosing
the frequency). However, all of the other timing mentioned
(POR delay, OCP sample, soft-start, etc.) is independent of
the clock frequency (unless otherwise noted).

BOOT Refresh

In the event that the UGATE is on for an extended period of
time, the charge on the boot capacitor can start to sag,
raising the r

DS(ON)

of the upper MOSFET. The ISL6545 has
a circuit that detects a long UGA TE on-time (nominal 100µs),
and forces the LGATE to go high for one clock cycle, which
will allow the boot capacitor some time to recharge.
Separately, the OCP circuit has an LGATE pulse stretcher

9

FN6305.3

November 15, 2006

ISL6545, ISL6545A

(to be sure the sample time is long enough), which can also
help refresh the boot. But if OCP is disabled (no current
sense resistor), the regular boot refresh circuit will still be
active.

Current Sinking

The ISL6545 incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6545 when it is known that
the converter may sink current.

When the converter is sinking current, it is behaving as a
boost converter that is regulating its input voltage. This
means that the converter is boosting current into the V

CC

rail, which supplies the bias voltage to the ISL6545. If there
is nowhere for this current to go, such as to other distributed
loads on the V
device, or other methods, the capacitance on the V

rail, through a voltage limiting protection

CC

CC

bus
will absorb the current. This situation will allow voltage level
of the V

rail to increase. If the voltage level of the rail is

CC

boosted to a level that exceeds the maximum voltage rating
of the ISL6545, then the IC will experience an irreversible
failure and the converter will no longer be operational.
Ensuring that there is a path for the current to follow other
than the capacitance on the rail will prevent this failure
mode.

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.

V

IN

ISL6545

UGATE
PHASE

LGATE/OCSET

Q

1

Q

2

L

O

V

OUT

C

IN

C

O

LOAD

plane in a printed circuit board. The components shown should
be located as close together as possible. Please note that the
capacitors C

and CO may each represent numerous physical

IN

capa ci t or s. F or be s t r es u lt s , l o ca te th e ISL6545 wi th in 1 inch of
the MOSFETs, Q

and Q2. The circuit traces for the MOSFET

1

gate and source connections from the ISL6545 must be sized
to handle up to 1A peak current.

+V

BOOT

C

BOOT

ISL6545

LGATE/OCSET

OCSET

R

FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL

GND

PHASE
VCC

+V

CC

C

VCC

LAYOUT GUIDELINES

IN

Q

L

1

Q

O

C

2

V

OUT

O

Figure 8 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP/SD pin and locate the resistor,
R
current source is only 20μA. Provide local V
between V

close to the COMP/SD pin because the internal

OSCET

and GND pins. Locate the capacitor, C

CC

decoupling

CC

BOOT

as close as practical to the BOOT and PHASE pins. All
components used for feedback compensation (not shown)
should be located as close to the IC as practical.

Feedback Compensation

This section highlights the design consideration for a voltage­mode controller requiring external compensation. T o address a
broad range of applications, a type-3 feedback network is
recommended, as shown in the top part of Figure 9.

Figure 9 also highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the
ISL6545 circuit. The output voltage (V
reference voltage, V

. The error amplifier output (COMP pin

REF

voltage) is compared with the oscillator (OSC) modified saw­tooth wave to provide a pulse-width modulated wave with an
amplitude of V

at the PHASE node. The PWM wave is

IN

smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented by
the series resistor E.

) is regulated to the

OUT

LOAD

RETURN

FIGURE 7. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

Figure 7 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power

10

FN6305.3

November 15, 2006

COMP

E/A

R2

C2

-

+

VREF

C1

FB

R3

Ro

R1

ISL6545, ISL6545A

C3

R1 F

⋅⋅

V

OSC

---------------------------------------------

=

R2

d

MAXVINFLC

5. Calculate C1 such that F

0

⋅⋅

is placed at a fraction of the FLC,

Z1

at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F

1

------------------------------------------------

=

C1

⋅⋅⋅

2π R2 0.5 F

LC

, the lower the FZ1

CE/FLC

LC

).

OSCILLATOR

V

IN

V

PWM

CIRCUIT

FIGURE 9. VOLT AGE-MODE BUCK CONVERTER

OSC

UGATE

HALF-BRIDGE

DRIVE

ISL6545

COMPENSATION DESIGN

PHASE

LGATE

EXTERNAL CIRCUIT

V

OUT

L

D

C

E

The modulator transfer function is the small-signal transfer
function of V
gain, given by d

OUT/VCOMP

MAXVIN/VOSC

filter, with a double pole break frequency at F
F

. For the purpose of this analysis, L and D represent the

CE

. This function is dominated by a DC

, and shaped by the output

and a zero at

LC

channel inductance and its DCR, while C and E represent the
total output capacitance and its e quivalent series resistance.

F

LC

---------------------------

=

2π LC⋅⋅

1

F

CE

------------------------

=

2π CE⋅⋅

1

The compensation network consists of the error amplifier
(internal to the ISL6545) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F

; typically 0.1 to 0.3 of FSW) and adequate phase

0

margin (better than 45°). Phase margin is the difference
between the closed loop phase at F

and 180°. The

0dB

equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 9. Use the following guidelines for locating the
poles and zeros of the compensation network:

4. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
value for R2 for desired converter bandwidth (F

0

). If
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 9, the design procedure can
be followed as presented.

6. Calculate C2 such that F

---------------------------------------------------------

=

C2

2π R2 C1 F

C1

7. Calculate R3 such that F

is placed at FCE.

P1

1–⋅⋅⋅

CE

is placed at FLC. Calculate C3

Z2

such that FP2 is placed below FSW (typically, 0. 5 to 1.0
times FSW). FSW represents the switching frequency.
Change the numerical factor to reflect desired placement
of this pole. Placement of F

lower in frequency helps

P2

reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.

R3

----------------------

=

F

------------

F

R1

SW

LC

-------------------------------------------------

C3

=

1–

2π R3 0.7 F

1

⋅⋅⋅

SW

It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G

d

----------------------------- -

f()

G

MOD

1sf() R2 C1⋅⋅+

------------------------------------------------------

f()

G

FB

G

CL

sf() R1 C1 C2+()⋅⋅

---------------------------------------------------------------------------------------------------------------------------- -

⋅

1sf() R3 C3⋅⋅+()1sf() R2

f() G

MOD

) and closed-loop response (GCL):

FB

⋅

MAXVIN

V

OSC

1sf() R1 R3+()C3⋅⋅+

f() GFBf()⋅=

----------------------------------------------------------------------------------------

⋅=

1sf() ED+()C⋅⋅s

1sf() EC⋅⋅+

⋅=

⎛⎞

⋅

⎝⎠

⋅⋅+

where s f(), 2π fj⋅⋅=

), feedback

MOD

2

f() LC⋅⋅++

C1 C2⋅

⎛⎞

----------------------

⎝⎠

C1 C2+

COMPENSATION BREAK FREQUENCY EQUATIONS

1

--------------------------------

F

=

Z1

2π R2 C1⋅⋅

---------------------------------------------------

=

F

Z2

2π R1 R3+()C3⋅⋅

1

F

=

P1

F

1

-----------------------------------------------

2π R2

P2

C1 C2⋅

----------------------

⋅⋅

C1 C2+

--------------------------------

=

2π R3 C3⋅⋅

1

Figure 10 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,

11

FN6305.3

November 15, 2006

ISL6545, ISL6545A

which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log graph of Figure 10 by adding the modulator gain, G
dB), to the feedback compensation gain, G

against the capabilities of the error

P2

, is constructed on the log-

CL

(in dB). This is

FB

MOD

(in

equivalent to multiplying the modulator transfer function and the
compensation transfer function and then plotting the resulting
gain.

F

Z1

GAIN

R2

⎛⎞

------- -

20

log

⎝⎠

R1

0

LOG

LOG

FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

F

F

Z2

F

LC

F

P1

F

F

CE

0

MODULATOR GAIN

P2

COMPENSATION GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

d

⋅

V

MAX

20

---------------------------------log
V

OSC

G

CL

G

MOD

FREQUENCY

IN

G

FB

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, F

SW

.

This is just one method to calculate compensation
components; there are variations of the above equations.
The error amp is similar to that on other Intersil regulators,
so existing tools can be used here as well. Special
consideration is needed if the size of a ceramic output
capacitance in parallel with bulk capacitors gets too large;
the calculation needs to model them both separately
(attempting to combine two different capacitors types into
one composite component model may not work properly; a
special tool may be needed; contact your local Intersil
person for assistance).

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.

Modern components and loads are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor values
are generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements ra ther than
actual capacitance requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate tran sient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equ ivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:

- V

V

IN

ΔI =

Fsw x L

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6545 will provide ei ther 0% or 100% du ty cycle i n
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient

OUT

V

OUT

x

V

IN

ΔV

OUT

= ΔI x ESR

12

FN6305.3

November 15, 2006

ISL6545, ISL6545A

current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

L x I

t

=

RISE

where: I

TRAN

VIN - V

OUT

is the transient load current step, t

TRAN

t

FALL

response time to the application of load, and t

L x I

V

TRAN

OUT

FALL

RISE

is the

is the

=

response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the volt age
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk cap acito rs
to supply the current needed each time Q

turns on. Place the

1

small ceramic capacitors physically close to the MOSFETs
and between the drain of Q

and the source of Q2.

1

The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.

For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can also be used, but caution must be exercised
with regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.

MOSFET Selection/Considerations

The ISL6545 requires 2 N-Channel power MOSFETs. These
should be selected based upon r
requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFET s. These losses are distributed between
the two MOSFETs according to duty factor. The switching

DS(ON)

, gate supply

losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching
losses when the converter is sinking current (see the
equations below). These equations assume linear voltage­current transitions and do not adequately model power loss
due the reverse-recovery of the upper and lower MOSFET’s
body diode. The gate-charge losses are dissipated by the
ISL6545 and don't heat the MOSFETs. However, large gate­charge increases the switching interval, t

which increases

SW

the MOSFET switching losses. Ensure that both MOSFETs
are within their maximum junction temperature at high ambient
temperature by calculating the te mperatur e rise acc ording to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.

Losses while Sourcing Current

1

x (1 - D)

-- -

2

× t

Io⋅ V

IN

××+=

SWFS

P

UPPER

P

LOWER

Io2r

= Io2 x r

× D×

DS ON()

DS(ON)

Losses while Sinking Current

P

P

= Io2 x r

UPPER

LOWER

Where: D is the duty cycle = V

Io2r

is the combined switch ON and OFF time, and

t

SW

is the switching frequency.

F

SW

When operating with a 12V power supply for V

x D

DS(ON)

× 1D–()×

DS ON()

OUT

1

-- -

2

/ VIN,

× t

Io⋅ V

IN

(or down

CC

××+=

SWFS

to a minimum supply voltage of 6.5V), a wide variety of N­MOSFETs can be used. Check the absolute maximum V

GS

rating for both MOSFETs; it needs to be above the highest
V

voltage allowed in the system; that usually means a

CC

20V V

rating (which typically correlates with a 30V VDS

GS

maximum rating). Low threshold transistors (around 1V or
below) are not recommended, for the reasons explained in
the next paragraph.

For 5V only operation, given the reduced available gate bias
voltage (5V), logic-level transistors should be used for both
N-MOSFETs. Look for r

DS(ON)

ratings at 4.5V. Caution
should be exercised with devices exhibiting very low
V

characteristics. The shoot-through protection

GS(ON)

present aboard the ISL6545 may be circumvented by these
MOSFETs if they have large parasitic impedences and/or
capacitances that would inhibit the gate of the MOSFET from
being discharged below its threshold level before the
complementary MOSFET is turned on. Also avoid MOSFET s
with excessive switching times; the circuitry is expecting
transitions to occur in under 50ns or so.

13

FN6305.3

November 15, 2006

ISL6545, ISL6545A

C

BOOT

+V

IN

Q1

Q2

V

≈ V

≈ V

CC

CC

- V

D

G-S

V

G-S

+V

CC

VCC

+ V

-

D

ISL6545

VCC

-

+

GND

FIGURE 11. UPPER GATE DRIVE BOOTSTRAP

BOOT

UGATE
PHASE

LGATE/OCSET

BOOTSTRAP Considerations

Figure 1 1 shows the upper gate drive (BOOT pin) supplie d by
a bootstrap circuit from V
develops a floating supply voltage referenced to the PHASE
pin. The supply is refreshed to a voltage of V
diode drop (V

) each time the lower MOSFET, Q2, turns on.

D

Check that the voltage rating of the capacitor is above the
maximum V

voltage in the system; a 16V rating should be

CC

sufficient for a 12V system. A value of 0.1µF is typical for
many systems driving single MOSFETs.

. The boot capacitor, C

CC

BOOT

less the boot

CC

,

If V

is 12V, but VIN is lower (such as 5V), then another

CC

option is to connect the BOOT pin to 12V, and remove the
BOOT cap (although, you may want to add a local cap from
BOOT to GND). This will make the UGATE V

voltage

GS

equal to (12V - 5V = 7V). That should be high enough to
drive most MOSFETs, and low enough to improve the
efficiency slightly . Do NOT
to get the same effect by driving BOOT through V

leave the BOOT pin open, and try

and the

CC

internal diode; this path is not designed for the high current
pulses that will result.

For low V

voltage applications where efficiency is very

CC

important, an external BOOT diode (in parallel with the
internal one) may be considered. The external diode drop
has to be lower than the internal one; the resulting higher
V

of the upper FET will lower its r

G-S

DS(ON)

. The modest
gain in efficiency should be balanced against the extra cost
and area of the external diode.

For information on the Application circuit, including a
complete Bill-of-Materials and circuit board description, can
be found in Application Note AN1257.

14

FN6305.3

November 15, 2006

ISL6545, ISL6545A

Dual Flat No-Lead Plastic Package (DFN)

(DAT UM B )

6

INDEX

AREA

(DATUM A)

NX (b)

5

SECTION "C-C"

6

INDEX
AREA

SEATING

PLANE

NX L

8

A

C

D

TOP

VIEW

SIDE VIEW

D2

D2/2

12

N

N-1

e
(Nd-1)Xe

REF .

BOTTOM VIEW

(A1)

2X

A3

E2/2

NX b

5

C

L

e

CC

FOR ODD TERMINAL/SIDE

87

E

A

NX k

E2

0.10

ABC0.15

2X

0.15

//

M

9

TERMINAL TIP

0.10

0.08

L

CB

BAC

L10.3x3C

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 ­A1 - - 0.05 ­A3 0.20 REF -

b 0.18 0.25 0.30 5, 8

D 3.00 BSC ­D2 2.23 2.38 2.48 7, 8

E 3.00 BSC -

C

C

E2 1.49 1.64 1.74 7, 8

e 0.50 BSC ­k0.20 - - ­L 0.30 0.40 0.50 8

N102
Nd 5 3

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identi fier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.

NOTESMIN NOMINAL MAX

Rev. 0 3/05

15

FN6305.3

November 15, 2006

ISL6545, ISL6545A

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC ­H 0.2284 0.2440 5.80 6.20 ­h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87

a

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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16

FN6305.3

November 15, 2006