Intersil ISL6539 Application Note

®

DDR Power Solution Using the ISL6539

Application Note October 30, 2006 AN1278.0

Author: Douglas Mattingly

Introduction

The ISL6539 is capable of providing a complete solution for
the power requirements of DDRI, DDRII or DDRIII memory
systems. The ISL6539 can be configured to operate as a
dual switching regulator or as a DDR regulator. This
application note will focus on the ISL6539 configured as a
DDR regulator. For information on the ISL6539 configured
as a dual switching regulator, refer to either the datasheet[1]
or to application note AN1278.

As a DDR regulator, the ISL6539 provides control and
protection for both the V
providing V

for the DDR system. Both V

REF

are provided through synchronous buck regulation. V

and VTT rails while also

DDQ

DDQ

and VTT

REF

is

provided via a low current buffer.
The switching frequency is fixed at 300kHz for both the

V

and VTT regulators. The two channels can be phase

DDQ

shifted 90° in order to minimize interaction. The ISL6539
incorporates voltage-feed-forward ramp modulation, current
mode control, and internal feedback compensation, which
provides fast response to input voltage and output load
transients.

Protection features include undervoltage and overvoltage
protection as well as a programmable overcurrent protection
feature that utilizes the r

of the lower MOSFET. A

DS(ON)

more complete description of the ISL6539 can be found in
the datasheet.

Quick Start Evaluation

The ISL6539EVAL1 board is shipped ‘ready to use’ right
from the box. The box includes this application note, the
ISL6539 datasheet, and the evaluation board.

The evaluation board supports testing with laboratory power
supplies. Both regulated outputs can be exercised through
external loads. There are posts available on the two
regulated output rails for drawing a load and/or monitoring
the voltages. An LED indicates the status of the PGOOD
signal. There are also three scope probe points that allow for
in depth analysis and two posts available to monitor the
enable signals for either channel. Four jumpers have also
been provided for control and monitoring purposes.

Recommended Test Equipment

To test the full functionality of the ISL6539, the following
equipment is recommended:

• Two laboratory power supplies

• Two Electronic Loads

• Four-channel Oscilloscope with probes

• Precision Digital Multimeters

CIRCUIT SETUP

Refer to Figure 1 for locations of the jumpers, connectors
and components described in the following sections.

JUMPER SETTINGS

There are four jumpers on the board. Shunting jumper JP3
pulls the EN1 pin to VCC and is used to enable Channel 1,
which is the V
Channel 2, which is the V
the input rail for the V
V

rail is to be disabled and the VTT rail enabled, then

DDQ

the V

rail must be energized from an external power

DDQ

regulator. Shunting jumper JP4 enables

DDQ

regulator. It should be noted that

TT

regulator is the V

TT

DDQ

rail. If the

supply and a 0.01µF capacitor should be installed in location
C21 for the V
capacitor for the V

rail to soft-start properly . C21 is the sof t-start

TT

rail, as shown in the schematic.

TT

Jumper JP1 can be used to monitor the ISL6539 bias current
by connecting an ammeter to the two jumper pins. If the bias
current is not being monitored, this jumper must be shunted.

Jumper JP5 is used to set the phase angle between the two
switching regulators. Refer to Figure 1 for the jumper
positions relating to the desired phase angle. Table 1 also
provides a detailed description of the jumper descriptions
and positions.

JUMPER POSITION FUNCTION

An AmpMeter may be connected across

JP1 Shunted

JP3

JP4

JP5

TABLE 1. DETAILED DESCRIPTION OF THE JUMPER

Shunted CH1 enabled

Removed CH1 disabled

Shunted CH2 enabled

Removed CH2 disabled

Toward

VINPRG

Away from

VINPRG

SETTINGS

these pins to measure IC and GATE Drive
current

This will tie VIN pin to the input voltage for
feed forward. It will also program CH2
PWM to phase lag CH1 by 90°

This will tie VIN pin to GND, disabling
input voltage feed forward, and will also
program in phase PWM for CH1 and CH2

CONNECTING LOADS

Loads should only be connected to the V

Loading V

: Connect the positive terminal of an

DDQ

and VTT rails.

DDQ

electronic load to the VDDQ post (J5). Connect the return
terminal of the same load to the adjacent GND post (J7).

Loading V

- Sourcing Current: To test VTT while the

TT

regulator sources current, connect the positive terminal of an
electronic load to the VTT post (J6). Connect the return
terminal of the same load to the adjacent GND post (J9).

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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Copyright Intersil Americas Inc. 2006. All Rights Reserved

Application Note 1278

Posts for connecting
Power, Ground, Load,
and Probes.

Four Probe points
available for
monitoring VTT,
VDDQ, and both
Phase nodes

ISL6539 IC

Two locations for
monitoring Enable
signals

Total Solution Area

FIGURE 1. ISL6539EVAL1 BOARD

Loading VTT - Sinking Current: To test VTT while the
regulator sinks current, connect the positive terminal of an
electronic load to the VDDQ post (J5). Connect the return
terminal of the same load to the VTT post (J6).

CAUTION: The return terminal of the load must float for this
to work properly.

CONNECTING PROBES

The table below lists all the locations available for
monitoring. The scope probe test points provide a low
impedance ground connection and all GND post can be
utilized as a ground connection for probes.

TYPE VOLTAGE LOCATION

POST V

SCOPE PROBE

TEST POINT

TERMINAL V

TABLE 2. PROBE TYPES AND LOCATIONS

DDQ

V

V

PGOOD

V

REF

V

CC

V

V

V

DDQ

V

PHASE1

V

PHASE2

EN1

V

EN2

TT

IN

TT

J5
J6

J11

J8
J4

J2
TP1
TP2
TP4
TP3

J12
J13

PGOOD status LED

Shorting this jumper
enables the VTT rail

Shorting this jumper
enables the VDDQ rail

This jumper can be used
to monitor bias current
to the ISL6539

Phase Angle

Jumper Positions

90o Phase

Shift

No Phase

Shift

Terminals J12 (EN1) and J13 (EN2) may also be connected
to a pulse generator for controlled ON/OFF operation of the
respective regulators. However, make sure the signal
generator for the enable voltage is no more than 5V and that
the respective Enable jumper is removed.

CONNECTING POWER

Prior to connecting the power supplies to the evaluation
board, the power supplies should either be turned off or the
outputs should be disabled.

VCC Power Connection: Connect the positive terminal of a
laboratory power supply to the VCC post (J4). Connect the
return terminal of the same load to the adjacent GND post
(J1).

V

Power Connection: Connect the positive terminal of a

IN

laboratory power supply to the VIN post (J2). Connect the
return terminal of the same load to the adjacent GND post
(J3).

2

Application Note 1278

Operation

APPLY POWER

Prior to applying power, ensure that jumpers JP1 and JP5
are in the desired position, all loads are connected properly,
and all probes are connected properly. Jumpers JP3 and
JP4 can be shunted and removed after power has been
applied.

V

IN

1V/DIV

The V

power supply must be turned on or enabled first.

IN

Likewise, it must always be disabled or turned off last. This
supply can be set from a minimum of 1.2V
maximum of 18V. After the V

power supply has been

IN

DDQ

to a

enabled, the VCC power supply may be enabled. The VCC
power supply must be 5V.

The PGOOD status LED will give a visual indication of the
V

regulator level. Table 3 de scribes the tw o state s of the

DDQ

LED.

LED CONDITION RESULT

Green V

CR1

Red

TABLE 3. PGOOD STATUS LED CONDITION INDICATOR

WITHIN PGOOD RANGE

OUT1

(89%-115% of nominal value)
V

OUTSIDE PGOOD RANGE

OUT1

(89-115% of nominal value)

EXAMINE WAVEFORMS

Start-up is immediate following Power On Reset (POR).
Using an oscilloscope or other laboratory equipment, the
ramp-up and/or regulation of the outputs can be studied.
Loading of the outputs can be accomplished through the use
of electronic loads. Any other method, however, will work as
well.

Evaluation Board Design

V

DDQ

500mV/DIV

Timebase: 500µs/DIV

FIGURE 2. POR SOFT-START, VCC = VIN

Figure 3 shows the start up the V
the enabling of the V

regulator.

DDQ

V

IN

1V/DIV

V

DDQ

500mV/DIV

V

TT

500mV/DIV

and VTT rails through

DDQ

V

500mV/DIV

V

EN

5V/DIV

TT

General

The evaluation board is built on a 2-ounce, four layer printed
circuit board. The board is designed to support a continuous
load of 5A on the V
continuous load on the V

rail and a simultaneous 3A

DDQ

rail while operating at room

TT

temperature and under natural convection cooling. Loading
on V

should not exceed 10mA.

REF

The schematic, bill of material, and the layout plots for the
ISL6539EVAL1 evaluation board are provided at the end of
this application note.

Eval Board Performance

Power-Up

When the VCC voltage exceeds the POR level, the ISL6539
will begin the soft-start procedure. Figure 2 shows the start­up of both the V

and VTT rails from POR.

DDQ

3

Timebase: 500µs/DIV

FIGURE 3. ENABLED SOFT-START

Application Note 1278

The ISL6539 is capable of starting into a prebiased output
rail. Figure 4 shows the ISL6539 soft-starting both the V
and V

rails from POR with a prebias on the V

TT

V

IN

1V/DIV

V

DDQ

500mV/DIV

Timebase: 500µs/DIV

DDQ

500mV/DIV

FIGURE 4. START-UP INTO PREBIASED OUTPUT

DDQ

rail.

V

TT

Output Ripple

Figure 5 shows the ripple on both the V
with a 90° phase shift implemented between the two
regulators.

and VTT rails

DDQ

Figure 6 shows the ripple on both the V
with a no phase shift implemented between the two

and VTT rails

DDQ

regulators.

V

(AC Coupled)

DDQ

50mV/DIV

V

PHASE1

5V/DIV

Timebase: 2µs/DIV

V

(AC Coupled)

TT

50mV/DIV

V

PHASE2

5V/DIV

FIGURE 6. OUTUPT RIPPLE - NO PHASE SHIFT

Transient Performance

Figure 7 shows both the V
rail is under transient loading.

and VTT rails while the V

DDQ

DDQ

V

(AC Coupled)

DDQ

50mV/DIV

V

PHASE1

5V/DIV

Timebase: 2µs/DIV

V

(AC Coupled)

TT

50mV/DIV

V

PHASE2

5V/DIV

FIGURE 5. OUTUPT RIPPLE - 90° PHASE SHIFT

V

(AC Coupled)

DDQ

100mV/DIV

V

(AC Coupled)

TT

100mV/DIV

I

VDDQ

2A/DIV

Timebase: 100µs/DIV

FIGURE 7. TRANSIENT LOAD ON V

DDQ

4

Application Note 1278

Figure 8 shows both the V

and VTT rails while the VTT

DDQ

rail is experiencing a sourcing transient load.

V

(AC Coupled)

DDQ

100mV/DIV

V

(AC Coupled)

TT

100mV/DIV

I

VTT

2A/DIV

Timebase: 100µs/DIV

FIGURE 8. SOURCING TRANSIENT LOAD ON V

Figure 9 shows both the V

and VTT rails while the VTT

DDQ

rail is experiencing a sinking transient load.

TT

Efficiency

Figure 10 shows the efficiency of the individual regulators.
These efficiencies were measured while the complementary
regulator was disabled.

100%

95%

90%

85%

80%

75%

012345

V

w/VIN=5V

DDQ

V

w/VIN=15V

DDQ

V

w/VIN=VDDQ

TT

Load Current [A]

FIGURE 10. EFFICIENCY

V

(AC Coupled)

DDQ

100mV/DIV

V

(AC Coupled)

TT

100mV/DIV

I

VTT

2A/DIV

Timebase: 100µs/DIV

FIGURE 9. SINKING TRANSIENT LOAD ON V

TT

5

Application Note 1278

ISL6539EVAL1 Customization

There are numerous ways in which a designer might modify
the ISL6539EVAL1 evaluation board for differing
requirements. Some of the changes which are possible
include:

• The output inductors, L1 and L2, for the V
regulators, respectively.

• The input capacitance may be changed. The evaluation
board is shipped with two 10µF ceramic capacitors, C2
and C3, as the input capacitance. A spot has been set
aside for the installation of a 10mm diameter through hole
aluminum electrolytic capacitor in location C1.

• The output capacitance of either regulator may be
modified. The evaluation board is shipped with one 220µF
capacitor on the output of each regulator. There are two
empty locations, C13 and C24, available for the V
regulator and one empty location, C15, available for the
VTT regulator.

• The overcurrent trip point of the V
programmed through the OCSET resistor, R9. Refer to the
ISL6539 datasheet for details on this.

• Changing the value of C20 will alter the rise time of the
outputs during soft-start. Refer to the ISL6539 datasheet
for details on this.

DDQ

regulator,

DDQ

and VTT

DDQ

Conclusion

The ISL6539EVAL1 is a versatile platform that allows
designers to gain a full understanding of the functionality of
the ISL6539 in a DDR memory system. The board is also
flexible enough to allow the designer to modify the board for
differing requirements. The following pages provide a
schematic, bill of materials, and layout drawings to support
implementation of this solution.

References

For Intersil documents available on the web, see
http://www.intersil.com/

[1] ISL6539 Data Sheet, Intersil Corporation, File No.

FN9144.

• The load capacity for either rail can be increased by
exchanging the MOSFETs, U2 and U3, for ones with
higher current handling capabilities. The ISEN resistor
values, R4 and R5, may need to be modified if this is
done. The overcurrent resistor value, R9, would also have
to be reviewed. Refer to the ISL6539 datasheet for details
on calculating the values of these resistors.

• The output voltage of the V
by changing resistor R10. Refer to the ISL6539 datasheet
for details on this.

• The percentage at which the V
voltage track the V
resistor divider set up by resistors R11 and R14.

rail can be modified by altering the

DDQ

regulator may be modified

DDQ

rail and the V

TT

REF

6

ISL6539EVAL1 Schematic

VIN

JP1

VCC

C4

+

C2,3

C1

VDDQ

R11

R14

C8

C25

C26

L1

+

C12,13,24

C17

R8

C11

R7

R10

Application Note 1278

JP5

D1

C9

U2

R9

14 13 28

U1

VIN

R2 R3

6

BOOT1

ISL6539

5

UGATE1

4

R4 R5

PHASE1

7

ISEN1

2

LGATE1

3

PGND1 PGND2

10

VSEN1

18

OCSET2

11

OCSET1

12

SOFT1

C20

1,9,20

R1

DDR

BOOT2

UGATE2
PHASE2

ISEN2

LGATE2

VSEN2

PG1

PG2/REF

SOFT2

EN1
EN2GND

VCC

C5

28

24

25

22

27

26

19

15

16

17

8

21

C10

C21

D2

U3

VCC

JP3

R6

R17

C19

JP4

C6

L2

C14,15

R18

VDDQ

VTT

+

C16

C7

PGOOD

VREF

C23

R20

J12

R19

J14

7

Application Note 1278

ISL6539EVAL1 Bill of Materials (BOM)

QTY REFERENCE DESCRIPTION VENDOR MFG. PART NO.

2 C20, C26 CAPACITOR, SMD, 0805, 0.01µF, 50V, 10%, X7R PANASONIC ECJ-2VB1H103K
1 C11 CAPACITOR, SMD, 0805, 0.015µF, 50V, 10%, X7R PANASONIC ECU-V1H153K
2 C9, C10 CAPACITOR, SMD, 0805, 0.15µF, 25V, 10%, X7R PANASONIC ECJ-2YB1E154kK
2 C7, C8 CAPACITOR, SMD, 1206, 1µF, 10V, 10%, X7R VENKEL C1206X7R100-105KNE
5 C5, C6, C16, C23, C25 CAPACITOR, SMD, 1206, 4.7µF, 10V, 10%, X7R VENKEL C1206X7R100475KNE
3 C12, C13, C14, C24 CAP TANT, LOW ESR, SMD, D3, 220µF, 4V, 20% SANYO 4TPC220M
1 C4 CAP TANT, LOW ESR, SMD, D, 68µF, 16V,10% KEMET T494D686K016AS
2 C2, C3 CAPACITOR, SMD, 1812, 10µf, 25V, 20%, X5R TAIYO YUDEN TMK432BJ106MM-T
2 D1, D2 DIODE-SCHOTTKYBARR, SMD, SOT323, 3P, 30V,

0.2A
1 CR1 LED, SMD, 4P, OTHER, POLARIZED RED/GRN LUMEX SSL-LXA3025IGC-TR
1 L1 PWR CHOKE COIL, SMD, 5.7mm, 4.6µH, 25% PANASONIC ETQ-P6F4R6HFA
1 L2 PWR CHOKE COIL, SMD, 6x6x3mm,1.5µH, 20%

1 U1 IC-DUAL SWITCHER 30V, 28P, QSOP INTERSIL ISL6539CA
1 Q1 TRANSISTOR, N-CHANNEL, 3P, SOT23 ON-SEMICONDUCTOR BSS123LT1-T
2 U2, U3 TRANSISTOR - DUAL MOS, N-CHANNEL, 8P,

2 R2, R3 RESISTOR, SMD, 0805, 0
1 R5 RESISTOR, SMD, 0805, 1k, 1/10W, 1%, TF PANASONIC ERJ-6ENF1001
5 R10, R11, R14, R19, R20 RESISTOR, SMD, 0805, 10k, 1/10W, 1%, TF PANASONIC ERJ-6ENF1002V
2 R1, R9 RESISTOR, SMD, 0805, 100k, 1/10W, 1%, TF PANASONIC ERJ-6ENF1003V
1 R8 RESISTOR, SMD, 0805, 17.8k, 1/10W, 1%, TF PANASONIC ERJ-J6ENF1782V
1 R4 RESISTOR, SMD, 0805, 2.49k, 1/10W, 1%, TF PANASONIC ERJ-6ENF2491
4 R15 - R18 RESISTOR, SMD, 0805, 680

3.2A

SOIC, 30V

Ω, 1/10W, TF PANASONIC ERJ-6GEY0R00V

Ω, 1/10W, 5%, TF PANASONIC ERJ-6GEYJ681V

ON-SEMICONDUCTOR BAT54WT1-T

PANASONIC ELL6SH1R5M

FAIRCHILD FDS6912A

8

Application Note 1278

ISL6539EVAL1 Printed Circuit Board Layers

ISL6539EVAL1 - TOP SILK SCREEN

9

ISL6539EVAL1 - TOP LAYER

Application Note 1278

ISL6539EVAL1 Printed Circuit Board Layers (Continued)

GND

VDDQ

ISL6539EVAL1 - INTERNAL 1 - GROUND

VTT

VCC

10

ISL6539EVAL1 - INTERNAL 2 - POWER

Application Note 1278

ISL6539EVAL1 Printed Circuit Board Layers (Continued)

ISL6539EVAL1 - BOTTOM LAYER

Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.

For information regarding Intersil Corporation and its products, see www.intersil.com

11

ISL6539EVAL1 - BOTTOM SILK SCREEN