intersil ISL6535 DATA SHEET

®

ISL6535

Data Sheet January 17, 2006 FN9255.0

Synchronous Buck Pulse-Width
Modulator (PWM) Controller

The ISL6535 is a high performance synchronous controller
for demanding DC/DC converter applications. It provides
overcurrent fault protection and is designed to safely startup
into prebiased output loads.

The output voltage of the converter can be precisely
regulated to as low as 0.597V, with a maximum tolerance of
±1% over the commercial temperature range, and ±1.5%
over the industrial temperature range.

The ISL6535 provides simple, single feedback loop, voltage­mode control with fast transient response. It includes a
triangle-wave oscillator that is adjustable from below 50kHz
to over 1.5MHz. Full (0% to 100%) PWM duty cycle support
is provided.

The error amplifier features a 15MHz gain-bandwidth
product and 6V/µs slew rate which enables high converter
bandwidth for fast transient performance.

The ISL6535's overcurrent protection monitors the current

by using the r

the need for a current sensing resistor.

Pinouts

(14 LD NARROW SOIC AND 16 LD QFN)

OCSET

COMP

of the upper MOSFET which eliminates

DS(ON)

ISL6535

TOP VIEW

VCC

RT

SS

FB
EN

GND

1
2
3
4
5
6
7

14
13
12
11
10

9
8

PVCC
LGATE
PGND
BOOT
UGATE
PHASE

Features

• Operates from +12V Input

• Excellent Output Voltage Regulation

- 0.597V Internal Reference

- ±1% Over the Commercial Temperature Range

- ±1.5% Over the Industrial Temperature Range

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

- Leading and Falling Edge Modulation

• Small Converter Size

- Constant Frequency Operation

- Oscillator Programmable from 50kHz to Over 1.5MHz

• 12V High Speed MOSFET Gate Drivers

- 2.0A Source/3A Sink at 12V Low Side Gate Drive

- 1.25A Source/2A Sink at 12V High Side Gate Drive

- Drives Two N-Channel MOSFETs

• Overcurrent Fault Monitor

- High-Side MOSFET’s r

DS(ON)

Sensing

- Reduced ~120ns Blanking Time

• Converter can Source and Sink Current

• Soft-Start Done and an External Reference Pin for
Tracking Applications are Available in the QFN Package

• Pin Compatible with ISL6522

• Supports Start-Up into Prebiased Loads

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Power Supply for some Pentium®, PowerPC™, as well as
Graphic CPUs

• High-Power 12V Input DC/DC Regulators

• Low-Voltage Distributed Power Supplies

SS

COMP

FB

EN

OCSET

SSDONE

1516 14 13

1

2

3

4

6578

GND

REFIN

1

RT

PHASE

VCC

12

11

10

9

UGATE

PVCC

LGATE

PGND

BOOT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Ordering Information

PAR T

NUMBER

(Note)

ISL6535CBZ 6535CBZ 0 to 70 14 Ld SOIC M14.15

ISL6535IBZ 6535IBZ -40 to 85 14 Ld SOIC M14.15

ISL6535CRZ 6535CRZ 0 to 70 16 Ld 4x4 QFN L16.4x4

ISL6535IRZ 6535IRZ -40 to 85 16 Ld 4x4 QFN L16.4x4

Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

All other trademarks mentioned are the property of their respective owners.

PAR T

MARKING

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

TEMP.

RANGE

(°C)

Copyright Intersil Americas Inc. 2006. All Rights Reserved

PACKAGE

(Pb-free)

PKG.

DWG. #

Block Diagram

EN

SS

VCC

INTERNAL

REGULATOR

6µA

2

REFIN

(QFN ONLY)

REFERENCE
V

= 0.597 V

REF

30µA

POWER-ON

RESET (POR)

SOFT-START

AND

FAULT LOGIC

SOURCE OCP

200µA

OCSET

BOOT

UGATE

ISL6535

GATE

FB

COMP

GND

EA

CONTROL

LOGIC

PWM

OSCILLATOR

PHASE

PVCC

LGATE

PGND

SSDONE

(QFN ONLY)

January 17, 2006

FN9255.0

RT

Simplified Power System Diagram

ISL6535

+12V

Typical Application

+12V

IN

C

F1

SSDONE

(QFN ONLY)

(QFN ONLY)

C

vcc

R

FS

R

FILTER

REFIN

R

OCSET

+1.2V to +12V

IN

Q1

L

OUT

V

OUT

ISL6535

C

L

C

OUT

BIN

OUT

V

OUT

Q2

C

SS

VCC

PVCC

R

2

L

IN

C

HFIN

C

F2

D

BOOT

R

1

BOOT

R

OCSET

OCSET

C

OCSET

Q1

C

BOOT

UGATE

PHASE

EN

LGATE

Q2

C

HFOUT

C

BOUT

PGND

R

RT

RT

ISL6535

SS

C

SS

3

COMP

FB

GND

C

2

C

1

R

2

R

O

C

R

3

3

R

1

FN9255.0

January 17, 2006

ISL6535

Absolute Maximum Ratings Thermal Information

Supply Voltage, V
Enable Voltage, V
Soft-start Done Voltage, V
Boot Voltage, V
Phase Voltage, V

All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.0V

PVCC,VVCC

. . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +16V

EN

. . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +36V

BOOT

PHASE

. . . . . . . . . . . . . . GND - 0.3V to +16V

SSDONE

. . . . . . . . . V

. . . . . . . . . . GND - 0.3V to +16V

- 16V to V

BOOT

BOOT

+ 0.3V

Operating Conditions

Supply Voltage, V
Supply Voltage, V
Boot to Phase Voltage, V

Ambient Temperature Range, ISL6535C . . . . . . . . . . . . 0°C to 70°C

Ambient Temperature Range, ISL6535I. . . . . . . . . . . .-40°C to 85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured with the component mounted on an evaluation PC board in free air.

1. θ

JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

2. θ

JA

Tech Brief TB379. For θ

3. Parameters designated by GBD are "Guaranteed by Design."

. . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

VCC

. . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

PVCC

- V

BOOT

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

. . . . . . . . . . . . . . <V

PHASE

PVCC

Electrical Specifications Recommended Operating Conditions, unless otherwise noted specifications in bold are valid for process,

temperature, and line operating conditions.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

V

SUPPLY CURRENT

CC

Shutdown Supply V

Shutdown Supply V

CC

PVCC

POWER-ON RESET

V

CC/VPVCC

V

CC/VPVCC

Rising Threshold 6.55 7.10 7.55 V

Hysteresis 170 250 500 mV

OCSET Rising Threshold 0.70 0.73 0.75 V

OCSET Hysteresis 180 200 220 mV

Enable - Rising Threshold 1.4 1.5 1.60 V

Enable - Hysteresis 175 250 325 mV

OSCILLATOR

Trim Test Frequency R

Total Variation 8kΩ < R

Ramp Amplitude ∆V

ERROR AMPLIFIER

DC Gain R

Gain-Bandwidth Product GBWP R

Slew Rate SR R

PROTECTION

OCSET Current I

OCSET Current I

OCSET Measurement Offset OCP

Soft-start Current I

I

VCC

I

PVCC

OSC

OCSET

OCSET

OFFSET

SS

SS/EN = 0V 3.5 6.1 8.5 mA

SS/EN = 0V 0.30 0.5 0.75 mA

= OPEN V

RT

to GND < 200kΩ - GBD - ±15 - %

RT

RRT = OPEN 1.7 1.9 2.15 V

= 10kΩ, CL= 100pF - GBD - 88 - dB

L

= 10kΩ, CL= 100pF - GBD - 15 - MHz

L

= 10kΩ, CL= 100pF - GBD - 6 - V/µs

L

T

= 0°C to 70°C 180 200 220 µA

J

T

= -40°C to 85°C 176 200 224 µA

J

OCSET= 1.5V to 15.4V - GBD - ±10 - mV

Thermal Resistance (Typical) θ

(°C/W) θJC (°C/W)

JA

SOIC Package (Note 1) . . . . . . . . . . . . 95 N/A

QFN Package (Note 2). . . . . . . . . . . . . 47 8.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(SOIC - Lead tips only)

ESD Ratings

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

= 12 175 200 220 kHz

VCC

22 30 38 µA

P-P

4

FN9255.0

January 17, 2006

ISL6535

Electrical Specifications Recommended Operating Conditions, unless otherwise noted specifications in bold are valid for process,

temperature, and line operating conditions. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

REFERENCE

Reference Voltage T

System Accuracy T

REFIN Current Source (QFN Only) -4 -6 -8 µA

REFIN Threshold (QFN Only) 2.10 - 3.50 V

REFIN Offset (QFN Only) -3 - 3 mV

GATE DRIVERS

Upper Drive Source Current I

Upper Drive Source Impedance R

Upper Drive Sink Current I

Upper Drive Sink Impedance R

Lower Drive Source Current I

Lower Drive Source Impedance R

Lower Drive Sink Current I

Lower Drive Sink Impedance R

U_SOURCEVBOOT

U_SOURCE

U_SINK

U_SINK

L_SOURCEVPVCC

L_SOURCE

L_SINK

L_SINK

SSDONE (QFN ONLY)

SSDONE Low Output Voltage I

= 0°C to 70°C 0.591 0.597 0.603 V

J

= -40°C to 85°C 0.588 0.597 0.606 V

T

J

= 0°C to 70°C -1.0 - 1.0 %

J

= -40°C to 85°C -1.5 - 1.5 %

T

J

- V

= 12V, 3nF Load - GBD - 1.25 - A

PHASE

90mA Source Current - 2.0 - Ω

V

BOOT

- V

= 12V, 3nF Load- GBD - 2 - A

PHASE

90mA Source Current - 1.3 - Ω

= 12V, 3nF Load - GBD - 2 - A

90mA Source Current - 1.3 - Ω

V

= 12V, 3nF Load - GBD - 3 - A

PVCC

90mA Source Current - 0.94 - Ω

SSDONE

= 2mA 0.30 V

Typical Performance Curves

RRT PULLUP

1000

100

RESISTANCE (kΩ)

10

10 100 1000

TO +12V

RRT PULLDOWN

TO GND

SWITCHING FREQUENCY (kHz)

FIGURE 1. RRT RESISTANCE vs FREQUENCY

Functional Pin Description (SOIC/QFN)

RT (Pin 1/14)

This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
switching frequency is set from between 200kHz and

1.5MHz according to the following equation: .

RRTkΩ[]

------------------------------------------------------- 1.3kΩ–≈
F

kHz[]200 kHz[]–

s

) from this pin to GND, the

RT

6500

(RRT to GND)

80
70
60
50

(mA)

40
30

PVCC+VCC

I

20
10

0

100 200 300 400 500 600 700 800 900 1000

C

= 3300pF

GATE

SWITCHING FREQUENCY (kHz)

C

C

GATE

GATE

= 1000pF

= 10pF

FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

Alternately ISL6535’s switching frequency can be lowered
from 200kHz to 50kHz by connecting the RT pin with a
resistor to VCC according to the following equation:

RRTkΩ[]

55000

------------------------------------------------------- 70kΩ+≈
200 kHz[]F

kHz[]–

s

(RRT to VCC)

5

FN9255.0

January 17, 2006

ISL6535

OCSET (Pin 2/15)

The current limit is programmed by connecting this pin with a
resistor and capacitor to the drain of the high side MOSEFT.
A 200

µA current source develops a voltage across the resis-

tor which is then compared with the voltage developed
across the high side MOSFET. A blanking period of 120ns is
provided for noise immunity.

SS (Pin 3/1)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 30µA current source, sets the soft-start
interval of the converter.

COMP (Pin 4/2) and FB (Pin 5/3)

COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error ampli­fier and the COMP pin is the error amplifier output. These
pins are used to compensate the voltage-control feedback
loop of the converter.

EN (Pin 6/4)

This pin is a TTL compatible input. Pull this pin below 0.8V to
disable the converter. In shutdown the soft-start pin is dis­charged and the UGATE and LGATE pins are held low.

GND (Pin 7/6)

Signal ground for the IC. All voltage levels are measured
with respect to this pin.

PHASE (Pin 8/7)

This pin connects to the source of the high side MOSFET
and the drain of the low side MOSFET. This pin represents
the return path for the high side gate driver. During normal
switching, this pin is used for high side current sensing.

UGATE (Pin 9/8)

Connect UGATE to the upper MOSFET gate. This pin pro­vides the gate drive for the upper MOSFET.

VCC (Pin 14/13)

Provide a 12V bias supply for the chip to this pin. The pin
should be bypassed with a capacitor to GND.

REFIN (QFN ONLY Pin 5)

Upon enable if REFIN is less than 2.2V, the external refer­ence pin is used as the control reference instead of the inter­nal 0.597V reference. An internal 6

µA pull up to 5V is

provided for disabling this functionality.

SSDONE (QFN ONLY Pin 16)

Provides an open drain signal at the end of soft-start.

Functional Description

Initialization

The ISL6535 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the bias voltage at the VCC pin and the driver input on the
PVCC pin. When the voltages at VCC and PVCC exceed
their rising POR thresholds, a 30µA current source driving
the SS pin is enabled. Upon the SS pin exceeding 1V, the
ISL6535 begins ramping the non-inverting input of the error
amplifier from GND to the System Reference. During
initialization the MOSFET drivers pull UGATE to PHASE and
LGATE to PGND.

Soft-start

During soft-start, an internal 30µA current source charges the
external capacitor (C
ISL6535 is utilizing the internal reference, then as the SS pin’s
voltage ramps from 1V to 3V, the soft-start function scales the
reference input (positive terminal of error amp) from GND to
VREF (0.597V nominal). If the ISL6535 is utilizing an

V

EN

) on the SS pin up to ~4V. If the

SS

BOOT (Pin 10/9)

This pin provides bias to the upper MOSFET driver. A boot­strap circuit may be used to create a BOOT voltage suitable
to drive a standard N-Channel MOSFET.

PGND (Pin 11/10)

This is the power ground connection. Tie the lower MOSFET
source and board ground to this pin.

LGATE (Pin 12/11)

Connect LGATE to the lower MOSFET gate. This pin pro­vides the gate drive for the lower MOSFET.

PVCC (Pin 13/12)

Provide a 12V ±10% bias supply for the lower gate drive to
this pin. This pin should be bypassed with a capacitor to
PGND.

6

V

OUT

V

SS

t

SS

FIGURE 3. TYPICAL SOFT-START INTERVAL

externally supplied reference, when the voltage on the SS pin
reaches 1V, the internal reference input (into of the error amp)
ramps from GND to the externally supplied reference at the
same rate as the voltage on the SS pin. Figure 3 shows a

FN9255.0

January 17, 2006

ISL6535

typical soft-start interval. The rise time of the output voltage is,
therefore, dependent upon the value of the soft start capacitor,
C

. If the internal reference is used, then the soft start

SS

capacitance value can be calculated through:

30µ AtSS⋅

C

----------------------------=

SS

2V

If an external reference is used, then the soft start
capacitance can be calculated through:

30µ AtSS⋅

----------------------------=

C

SS

V

REFEXT

Prebiased Load Startup

Drivers are held in tri-state (UG pulled to Phase, LG pulled to
PGND) at the beginning of a soft-start cycle until two PWM
pulses are detected. The low side MOSFET is turned on first
to provide for charging of the bootstrap capacitor. This
method of driver activation provides support for startup into
prebiased loads by not activating the drivers until the control
loop has entered its linear region, thereby substantially
reducing output transients that would otherwise occur had
the drivers been activated at the beginning of the soft-start
cycle.

SSDONE

Soft-start done is only available in the 16 Lead QFN
packaging option of the ISL6535. When the soft-start pin
reaches 4V, an open drain signal is provided to support
sequencing requirements. SSDONE is deasserted by
disabling of the part, including pulling SS low, and by POR
and OCP events.

Oscillator

The oscillator is a triangular waveform, providing for leading
and falling edge modulation. The peak to peak of the ramp
amplitude is set at 1.9V and varies as a function of
frequency. At 50kHz the peak to peak amplitude is
approximately 1.8V while at 1.5MHz it is approximately 2.2V.
In the event the regulator operates at 100% duty cycle for 64
clock cycles an automatic boot cap refresh circuit will
activate turning on LG for approximately 1/2 of a clock cycle.

Overcurrent Protection

The OCP function is enabled with the drivers at startup. OCP
is implemented via a resistor (R
(C

) connecting the OCSET pin and the drain of the

OCSET

high side MOSEFT. An internal 200
develops a voltage across R

OCSET

with the voltage developed across the high side MOSFET at
turn on as measured at the PHASE pin. When the voltage
drop across the MOSFET exceeds the voltage drop across
the resistor, a sourcing OCP event occurs. C
placed in parallel with R
R

in the presence of switching noise on the input bus.

OCSET

to smooth the voltage across

OCSET

) and a capacitor

OCSET

µA current source

which is then compared

OCSET

is

A 120ns blanking period is used to reduce the current
sampling error due to leading-edge switching noise. An
additional simultaneous 120ns low pass filter is used to
further reduce measurement error due to noise.

OCP faults cause the regulator to disable (upper and lower
drives disabled, SSDONE pulled low, soft-start capacitor
discharged) itself for a fixed period of time, after which a
normal soft-start sequence is initiated. If the voltage on the
SS pin is already at 4V and an OCP is detected, a 30µA
current sink is immediately applied to the SS pin. If an OCP
is detected during soft start, the 30µA current sink will not be
applied until the voltage on the SS pin has reached 4V. This
current sink discharges the C

capacitor in a linear fashion.

SS

Once the voltage on the SS pin has reached approximately
0V, the normal soft start sequence is initiated. If the fault is
still present on the subsequent restart, the ISL6535 will
repeat this process in a hiccup mode. Figure 4 shows a
typical reaction to a repeated overcurrent condition that
places the regulator in a hiccup mode. If the regulator is

V

SSDONE

V

SS

I

OCP

I

LOAD

T

HICCUP

FIGURE 4. TYPICAL OVERCURRENT PROTECTION

repeatedly tripping overcurrent, the hiccup period can be
approximated by the following formula:

T

HICCUP

The OCP trip point varies mainly due to MOSFET r

8V CSS⋅

------------------------=

30µ A

DS(ON)

variations and layout noise concerns. To avoid overcurrent
tripping in the normal operating load range, find the R

OCSET

resistor from the following equations with:

1. The maximum r

at the highest junction

DS(ON)

temperature;

2. The minimum I

from the specification table;

OCSET

7

FN9255.0

January 17, 2006

ISL6535

Determine the overcurrent trip point greater than the
maximum output continuous current at maximum inductor
ripple current.

Simple OCP Equation

R

OCSET

I

OC_SOURCE

----------------------------------------------------------- -----=

200µ A

r•

DS ON()

Detailed OCP Equation

I∆

---- -+

2

•

HSOCNU

r•

DS ON()

R

OCSET

N

U

∆I =

F

SW



I

OC_SOURCE



-------------------------------------------------------------- ------------------- -=

NUMBER OF HIGH SIDE MOSFETs=

- V

V

IN

OUT

---------------------------------

FSWL

•

OUT

Regulator Switching Frequency=

V

--------------- -

•

I

OUT

V

IN

High Speed MOSFET Gate Driver

The integrated driver has the same drive capability and
feature as the Intersil’s 12V gate driver, ISL6612. The PWM

tri-state feature helps prevent a negative transient on the

output voltage when the output is being shut down. This
eliminates the Schottky diode that is used in some systems
for protecting the microprocessor from reversed-output­voltage damage. See the ISL6612 datasheet for
specification parameters that are not defined in the current
ISL6535 electrical specifications table.

impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.

A multi-layer printed circuit board is recommended. Figure 5
shows the critical components of the converter. Note that

+12V

C

BP_PVCC

C

BP_VCC

C

C

SS

VIN

C

Q

IN

Q

IN

1

L

OUT

2

C

OUT

V

OUT

LOAD

ISL6535

GND

VCC

PVCC

UGATE

BOOT

PHASE

LGATE

SS

PGND

Reference Input

The REFIN pin allows the user to bypass the internal 0.597V
reference with an external reference. If REFIN is NOT above
~2.2V, the external reference pin is used as the control
reference instead of the internal 0.597V reference. When not
using the external reference option the REFIN pin should be
left floating. An internal 6

µA pull-up keeps this REFIN pin

above 2.2V in this situation.

Internal Reference and System Accuracy

The Internal Reference is set to 0.597V. The total DC
system accuracy of the system is to be within 1.0% over
commercial temperature range and 1.5% over the industrial
temperature range. System Accuracy includes Error
Amplifier offset, and Reference Error. The use of REFIN may
add up to 3mV of offset error into the system (as the Error
Amplifier offset is trimmed out via the int ern a l System
reference.)

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the

KEY

TRACE SIZED FOR 3A PEAK CURRENT
SHORT TRACE, MINIMUM IMPEDANCE

ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

capacitors C

and C

IN

could each represent numerous

OUT

physical capacitors. Dedicate one solid layer, usually a
middle layer of the PC board, for a ground plane and make
all critical component ground connections with vias to this
layer. Dedicate another solid layer as a power plane and
break this plane into smaller islands of common voltage
levels. Keep the metal runs from the PHASE terminals to the
output inductor short. The power plane should support the
input power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the phase
nodes. Use the remaining printed circuit layers for small
signal wiring.

Locate the ISL6535 within 2 to 3 inches of the MOSFETs, Q1
and Q2 (1 inch or less for 500kHz or higher operation). The

8

FN9255.0

January 17, 2006

ISL6535

circuit traces for the MOSFETs’ gate and source connections
from the ISL6535 must be sized to handle up to 3A peak
current. Minimize any leakage current paths on the SS pin
and locate the capacitor, C
internal current source is only 30µA. Provide local V

close to the SS pin as the

ss

CC

decoupling between VCC and GND pins. Locate the
capacitor, C

as close as practical to the BOOT pin and

BOOT

the phase node.

Compensating the Converter

The ISL6535 Single-phase converter is a voltage-mode
controller. This section highlights the design consideration for a
voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 6).

C2

C

R

C

3

R

R

3

1

2

VOUT

1

COMP

FB

ISL6535

PWM

CIRCUIT

COMP

HALF-BRIDGE

C

R

2

-

+

E/A

VREF

OSCILLATOR

V

OSC

DRIVE

2

C

C

1

R

FB

GND

UGATE

PHASE

LGATE

3

3

R

1

V

OUT

V

IN

L

DCR

C

ESR

FIGURE 6. COMPENSATION CONFIGURATION FOR THE

ISL6535 CIRCUIT

Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The error amplifier
output is compared with the oscillator triangle wave to
provide a pulse-width modulated wave with an amplitude of
V

at the PHASE node. The PWM wave is smoothed by the

IN

output filter. The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.

The modulator transfer function is the small-signal transfer
function of V

OUT/VCOMP

. This function is dominated by a
DC gain and shaped by the output filter, with a double pole
break frequency at F

and a zero at FCE. For the purpose

LC

of this analysis, L and DCR represent the output inductance
and its DCR, while C and ESR represents the total output
capacitance and its equivalent series resistance.

FLC

---------------------------=

2π LC⋅⋅

1

FCE

1

---------------------------------=

2π C ESR⋅⋅

EXTERNAL CIRCUITISL6535

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

The compensation network consists of the error amplifier
(internal to the ISL6535) and the external R

1-R3

, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F

; typically 0.1 to 0.3 of FSW) and adequate

0

phase margin (better than 45 degrees). Phase margin is the
difference between the closed loop phase at F

and 180°.

0dB

The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R
and C

) in Figures 6 and 7. Use the following guidelines for

3

, R2, R3, C1, C2,

1

locating the poles and zeros of the compensation network:

1. Select a value for R
value for R

for desired converter bandwidth (F0). If

2

(1kΩ to 10kΩ, typically). Calculate

1

setting the output voltage to be equal to the reference set
voltage as shown in Figure 7, the design procedure can
be followed as presented. As the ISL6535 supports 100%

V

⋅⋅

----------------------------------------------=

2

D

MAXVINFLC

OSCR1F0

⋅⋅

equals 1. The ISL6535 uses a fixed

MAX

) of 1.9V, the above equation

OSC

R

duty cycle, D
ramp amplitude (V
simplifies to:

1.9 R1F

⋅⋅

⋅

INFLC

0

-------------------------------=

R

2

V

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ISL6535

2. Calculate C1 such that FZ1 is placed at a fraction of the FLC,
at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor below
to the desired number). The higher the quality factor of the
output filter and/or the higher the ratio F

CE/FLC

, the lower

the FZ1 frequency (to maximize phase boost at FLC).

C

1

3. Calculate C

C

2

4. Calculate R

1

-----------------------------------------------=

2π R

--------------------------------------------------------=

2π R2C1FCE1–⋅⋅⋅

0.5 F

⋅⋅ ⋅

2

2

3

LC

such that FP1 is placed at FCE.

C

1

such that FZ2 is placed at FLC. Calculate C3
such that FP2 is placed below FSW (typically, 0.3 to 1.0
times F

). FSW represents the switching frequency of the

SW

regulator. Change the numerical factor (0.7) below to reflect
desired placement of this pole. Placement of FP2 lower in
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant duty
cycle jitter.

R

1

----------------------=

R

3

F

SW

------------ 1–
F

LC

-------------------------------------------------=

C

3

2π R

1

0.7 F

⋅⋅ ⋅

3

SW

It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G

D

G

MOD

G

FB

G

CL

------------------------------ -

f()

----------------------------------------------------

f()

sf() R

----------------------------------------------------------- ---------------------------------------------------------- ----

f() G

) and closed-loop response (GCL):

FB

⋅

MAXVIN

V

1sf() R

OSC

⋅⋅+

1C1C2

⋅=

2C1

1sf() R

1sf() R

⋅⋅+()1sf() R

3C3

f() GFBf()⋅=

MOD

--------------------------------------------------------------- --------------------------------------------

1sf() ESR DCR+()C⋅⋅s

+()⋅⋅

1sf() ESR C⋅⋅+

⋅=

+()C

⋅⋅+

1R3



⋅




where s f(), 2π fj⋅⋅=

), feedback

MOD

3

C1C2⋅



---------------------

⋅⋅+



2

C

+



1C2

2

f() LC⋅⋅++

COMPENSATION BREAK FREQUENCY EQUATIONS

F

Z1

F

Z2

1

------------------------------ -=

⋅⋅

2π R

2C1

-------------------------------------------------=

2π R

1

+()C

⋅⋅

1R3

F

P1

F

P2

3

---------------------------------------------=

2π R

⋅⋅

------------------------------ -=

⋅⋅

2π R

1

2

1

3C3

C1C2⋅

--------------------­+

C

1C2

Figure 8 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the

compensation gain at F
amplifier. The closed loop gain, G

against the capabilities of the error

P2

, is constructed on the

CL

log-log graph of Figure 8 by adding the modulator gain,
G

(in dB), to the feedback compensation gain, GFB (in

MOD

dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.

MODULATOR GAIN

P2

COMPENSATION GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

D

V

⋅

MAX

V

OSC

G

MOD

FREQUENCY

IN

------------------------------- ---log

G

CL

G

FB

GAIN

0

LOG

LOG

F

Z1

R2



--------

log

20



R1

F

F

Z2

F

LC

F

P1

20

F

F

CE

0

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin. The mathematical model
presented makes a number of approximations and is
generally not accurate at frequencies approaching or
exceeding half the switching frequency. When designing
compensation networks, select target crossover frequencies
in the range of 10% to 30% of the switching frequency,
F

.

SW

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.

Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance

10

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ISL6535

components. Consult with the manufacturer of the load on
specific decoupling requirements.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors.
The bulk capacitor’s ESR will determine the output ripple
voltage and the initial voltage drop after a high slew-rate
transient. An aluminum electrolytic capacitor's ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance
(ESL) of these capacitors increases with case size and can
reduce the usefulness of the capacitor to high slew-rate
transient loading. Unfortunately, ESL is not a specified
parameter. Work with your capacitor supplier and measure
the capacitor’s impedance with frequency to select a
suitable component. In most cases, multiple electrolytic
capacitors of small case size perform better than a single
large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:

- V

V

IN

--------------------------------

∆I =

Fs x L

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6535 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

LOI

------------------------------- -=

RISE

V

where: I

TRAN

response time to the application of load, and T
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the

V

OUT

OUT

--------------- -

•

×

TRAN

–

INVOUT

V

IN

T

∆V

FALL

= ∆I x ESR

OUT

LOI

-------------------------------=T

×

V

TRAN

OUT

is the transient load current step, T

RISE

FALL

is the

is the

application or removal of load and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for
the worst case response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place
the small ceramic capacitors physically close to the
MOSFETs and between the drain of Q1 and the source of
Q2.

The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select a bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage, a voltage rating of 1.5 times greater is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.

For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV­GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.

MOSFET Selection/Considerations

The ISL6535 requires at least 2 N-Channel power
MOSFETs. These should be selected based upon r
gate supply requirements, and thermal management
requirements.

In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. At a
300kHz switching frequency, the conduction losses are the
largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed
between the two MOSFETs according to duty factor (see the
following equations). Only the upper MOSFET exhibits
switching losses, since the schottky rectifier clamps the
switching node before the synchronous rectifier turns on.

These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse­recovery of the lower MOSFETs body diode. The
gate-charge losses are dissipated by the ISL6535 and don't
heat the MOSFETs. However, large gate-charge increases

DS(ON)

,

11

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January 17, 2006

ISL6535

P

UPPER

P

LOWER

= I

= I

2

x r

O

DS(ON)

2

x r

O

DS(ON)

where: D is the duty cycle = V

x D +

x (1 - D)

/ VIN,

O

1

Io x VIN x TSW x Fs

2

TSW is the switching interval, and
Fs is the switching frequency.

the switching interval, TSW which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.

Standard-gate MOSFETs are normally recommended for
use with the ISL6535. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to­source voltage rating determine whether logic-level
MOSFETs are appropriate.

Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from +12V. The boot capacitor, C

BOOT

develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of +12V
less the boot diode drop (V

) when the lower MOSFET, Q2

D

turns on. A MOSFET can only be used for Q1 if the
MOSFETs absolute gate-to-source voltage rating exceeds
the maximum voltage applied to +12V. For Q2, a logic-level
MOSFET can be used if its absolute gate-to-source voltage
rating also exceeds the maximum voltage applied to +12V.

Figure 10 shows the upper gate drive supplied by a direct
connection to +12V. This option should only be used in
converter systems where the main input voltage is +5 VDC
or less. The peak upper gate-to-source voltage is
approximately +12V less the input supply. For +5V main
power and +12V DC for the bias, the gate-to-source voltage
of Q1 is 7V. A logic-level MOSFET is a good choice for Q1
and a logic-level MOSFET can be used for Q2 if its absolute
gate-to-source voltage rating exceeds the maximum voltage
applied to PVCC. This method reduces the number of
required external components, but does not provide for
immunity to phase node ringing during turn on and may
result in lower system efficiency.

+12V

ISL6535

­+

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

+12V

ISL6535

-

+

FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION

D

+

GND

GND

BOOT

V

D

BOOT

UGATE

PHASE

PVCC

LGATE
PGND

BOOT

UGATE

PVCC

LGATE
PGND

BOOT

+1.2V TO +12V

Q1

Q2

+5V OR LESS

Q1

Q2

NOTE:
V

D2

NOTE:

V

D2

≈ VCC - V

G-S

NOTE:
V

≈ PVCC

G-S

≈ VCC - 5V

G-S

NOTE:
V

≈ PVCC

G-S

D

-

C

+12V

+12V

Schottky Selection

Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency could slightly decrease
as a result. The diode's rated reverse breakdown voltage
must be greater than the maximum input voltage.

12

FN9255.0

January 17, 2006

Small Outline Plastic Packages (SOIC)

ISL6535

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45

o

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

A1

C

0.10(0.004)

M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.3367 0.3444 8.55 8.75 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC ­H 0.2284 0.2440 5.80 6.20 ­h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N14 147

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

13

FN9255.0

January 17, 2006

ISL6535

Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 ­A1 - - 0.05 ­A2 - - 1.00 9
A3 0.20 REF 9

b 0.23 0.28 0.35 5, 8

D 4.00 BSC ­D1 3.75 BSC 9
D2 1.95 2.10 2.25 7, 8

E 4.00 BSC ­E1 3.75 BSC 9
E2 1.95 2.10 2.25 7, 8

e 0.65 BSC ­k0.25 - - ­L 0.50 0.60 0.75 8

L1 - - 0.15 10

N162
Nd 4 3
Ne 4 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

NOTESMIN NOMINAL MAX

Rev. 5 5/04

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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14

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