intersil ISL6523A DATA SHEET

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ISL6523A

Data Sheet February 2002

VRM8.5 Dual PWM and Dual Linear Power
System Controller

The ISL6523A provides the powe r control and prote ct ion for
four output voltages in high-performance microprocessor
and computer applications. The IC integrates two PWM
controllers and two linear controllers, as well as the
monitoring and protection functions into a 28-pin SOIC
package. One PWM con trol ler regu late s th e m ic ropro ce ssor
core voltage with a synchronous-rectified buck converter.
The second PWM con t rol le r supplies the computer system’s
AGTL+ 1.2V bus power with a standard buck converter. The
linear controllers regulate power for the 1.5V AGP bus and
the 1.8V power for the chipset core voltage and/or cache
memory circuits.

The ISL6523A includes an Intel VRM8.5 compatible, TTL
5-input digital-to-a nalog converter (DAC) that adjusts the
microprocessor core-targeted PWM output voltage from

1.050V to 1.825V in 25mV steps. The precision reference
and voltage-mode control provid e ±1% stati c regu lation . The
second PWM controller’s output provides a voltage level of

1.2V with ±3% accuracy. The linear regulators use external
N-channel MOSFETs or bipolar NPN pass transistors to
provide fixed o utput volt ages of 1. 5V ±3% (V
±3% (V

OUT4

).

OUT3

) and 1.8V

The ISL6523A monitors all the output voltages. A delayed­rising VTT (standard buck output) Power Good signal is
issued before the core PWM starts to ramp up. Another
system Power Good signal is issued when the core is within
±10% of the DAC setting and all other outputs are above
their under- voltage levels. Additional built-in overvoltage
protection for the core output uses the lower MOSFET to
prevent output vol tages above 115% of the DAC setting. Th e
PWM controllers’ overcurrent function monitors the output
current by using the voltage drop across the upper
MOSFET’s r

, eliminating the need for a current

DS(ON)

sensing resistor.

Ordering Information

PART NUMBER

ISL6523ACB 0 to 70 28 Ld SOIC M28.3
ISL6523EVAL1 Evaluation Board

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

FN9063

Features

• Provides 4 Regulated Voltages

- Microprocessor Core, AGTL+ Bus, AGP Bus Power,
and North/South Bridge Core

• Drives N-Channel MOSFETs

• Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors

• Simple Single-Loop Control Designs

- Voltage-Mode PWM Control

• Fast PWM Converter Transient Response

- High-Bandwidth Error Amplifiers

- Full 0% to 100% Duty Ratios

• Excellent Output Voltage Regulation

- Core PWM Output . . . . . . . . . . ±1% Over T em perature

- All Other Outputs . . . . . . . . . . . . .±3% Over Temperature

• VRM8.5 TTL-Compatible 5-Bit DAC Microprocessor Core
Output Voltage Selection

- Wide Range . . . . . . . . . . . . . . . . . . . . 1.050V to 1.825V

• Power-Good Output Voltage Monitors

- Separate delayed VTT Power Good

• Overcurrent Fault Monitors

- Switching Regulators Do Not Require Extra Current

Sensing Elements, Use MOSFET’s r

DS(ON)

• Small Converter Size

- Constant Frequency Opera tio n

- 200kHz Internal Oscillator

Applications

•

Motherboard Power Regulation for Computers

Pinout

ISL6523A (SOIC)

TOP VIEW

VCC

UGATE2
PHASE2

VID3
VID2
VID1
VID0

VID25

PGOOD

VTTPG

OCSET2

VSEN2

SS24
SS13

VSEN4

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

UGATE1
PHASE1
LGATE1
PGND
OCSET1
VSEN1
FB1
COMP1
VSEN3
DRIVE3
GND
VAUX
DRIVE4

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002. All Rights Reserved

ISL6523A

VCC

OCSET1

VSEN1

POWER-ON

VAUX

RESET (POR)

PGOOD

200µA

-

+

1.10

x

-

+

0.90

x

-

+

1.15

x

VCC

DRIVE1

UGATE1

+

OC1

PHASE1

-

LGATE1

VCC

GATE

CONTROL

PWM1

PWM

COMP1

-

+

EA1

-

+

DRIVE

SYNCH

PGND

GND

TTL D/A

CONVERTER

DACOUT

28µA

(DAC)

VID25

VID0

VID1

VID3 VID2

COMP1

FB1

4.5V

OV

SS24

200µA

OCSET2

UV3

UV4

-

-

+

+

OC2

+

-

-

+

VSEN3

VAUX

1.5V

-

+

EA3

x0.75

x0.75

+

1.8V

-

+

-

EA4

DRIVE2

VCC

PWM

INHIBIT

SOFT-

LOGIC

START

& FAULT

FAULT

COMP2

+

-

PWM2

GATE

CONTROL

VCC

EA2

-

+

UV2

-

28µA

+

SET

1.2V

x0.90

+

4.5V

FIGURE 1. BLOCK DIAGRAM

SS13

OSCILLATOR

>

D

CLK

CLR

Q

Q

VTTPG

-

DRIVE3

2

DRIVE4

VSEN4

UGATE2

PHASE2

VSEN2

+5V

+12V

ISL6523A

IN

+3.3V

V

OUT2

1.2V

+5V

Q1

V

OUT1

V

OUT2

Q3

PWM2

CONTROLLER

PWM1

CONTROLLER

Q2

ISL6523A

IN

V

OUT3

Q4

LINEAR

CONTROLLER

LINEAR

CONTROLLER

Q5

V

OUT4

FIGURE 2. SIMPLIFIED POWER SYSTEM DIAGRAM

IN

IN

L

IN

C

IN

VCC

OCSET1

PGOOD

UGATE1
PHASE1

Q1

L

OUT1

POWERGOOD

V

OUT1

1.3V to 3.5V

C

OUT2

L

OUT2

CR2

Q3

OCSET2

UGATE2
PHASE2

VTT POWERGOOD

+3.3V

IN

V

OUT3

1.5V
C

OUT3

V

OUT4

1.8V
C

OUT4

Q5

Q4

C

VSEN2

VTTPG

ISL6523A

VAUX

DRIVE3

VSEN3

DRIVE4

VSEN4

SS24

SS24

FIGURE 3. TYPICAL APPLICATION

GND

LGATE1
PGND

VSEN1

FB1

COMP1

VID3
VID2
VID1

VID0
VID25

SS13

C

SS13

Q2

C

OUT1

3

ISL6523A

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V

PGOOD, RT/FA ULT, DRIVE, PHASE, and

GAT E Voltage. . . . . . . . . . . . . . . . . . . GND - 0.3V to V

Input, Output or I/O Voltage. . . . . . . . . . . . . . . . . . G ND -0.3V to 7V

CC

+ 0.3V

ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Resistance (Typical, Note 1)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

Recommended Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Tem perature Range. . . . . . . . . . . . . . . . . . . . 0

Junction Temper ature Range. . . . . . . . . . . . . . . . . . . 0

CAUTION: Stresses above those li sted in “Abs olute Maxi mum Ratings” may cause perman ent damag e to the device. T his is a stress on ly rating an d operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

o

C to 70oC

o

C to 125oC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply Current I

CC

POWER-ON RESET

Rising VCC Threshold - - 10.4 V
Falling VCC Threshold 8.2 - - V
Rising VAUX Threshold -2.5- V
VAUX Threshold Hysteresis -0.5- V
Rising V

Threshold -1.26- V

OCSET1

OSCILLATOR

Free Running Frequency F
Ramp Amplitude ∆V

OSC

OSC

DAC AND STANDARD BUCK REGULATOR REFERENCE

DAC (VID25-VID3) Input Low Voltage --0.8V
DAC (VID25-VID3) Input High Voltage 2.0 - - V
DACOUT Voltage Accuracy -1.0 - +1.0 %
PWM2 Regulation Voltage -1.2- V
PWM2 Regulation Voltage Tolerance -3- %

1.5V AND 1.8V LINEAR REGULATORS (V

OUT3

AND V

Regulation Tolerance -3- %
VSEN3 Regulation Voltage VREG
VSEN4 Regulation Voltage VREG
VSEN3,4 Under-Voltage Level VSEN3,4
VSEN3 Under-Voltage Hysteresis VSEN3 Falling - 7 - %
Output Drive Current VAUX-V

SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER

DC Gain Note 2 - 88 - dB
Gain-Bandwidth Product GBWP Note 2 - 15 - MHz
Slew Rate SR COMP1 = 10pF, Note 2 - 6 - V/µs

PWM CONTROLLERS GATE DRIVERS

UGATE1,2 Source I
UGATE1,2 Sink R

UGATE

UGATEVGATE-PHASE

UGATE1, LGATE1, UGATE2, DRIVE3, and

-9- mA

DRIVE4 Open

185 200 215 kHz

-1.9- V

)

OUT4

3
4

VSEN3,4 Rising - 75 - %

UV

DRIVE3,4

VCC = 12V, V

> 0.6V 20 40 - mA

UGATE1

(or V

) = 6V - 1 - A

UGATE2

-1.5- V

-1.8- V

= 1V - 1.7 3.5 Ω

θ

(oC/W)

JA

o

C to 150oC

P-P

o

C

o

C

4

0

ISL6523A

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

LGATE Source I
LGATE Sink R

PROTECTION

VSEN1 Over-Voltage (VSEN1/DACOUT) VSEN1 Rising - 120 - %
OCSET1,2 Current Source I
Soft-Start Current I

POWER GOOD

VSEN1 Upper Threshold
(VSEN1/DACOUT)

VSEN1 Under-Voltage
(VSEN1/DACOUT)

VSEN1 Hysteresis (VSEN1/D AC O UT ) VSEN1 Falling - 2 - %
PGOOD Voltage Low V
VSEN2 Under-Voltage VSEN2 Rising - 1.00 - V
VSEN2 Hysteresis VSEN2 Falling - 60 - mV
VTTPG Voltage Low V

NOTE:

2. Guaranteed by design

LGATE

LGATE

OCSET

SS13,24VSS13,24

PGOODIPGOOD

VTTPGIVTTPG

VCC = 12V, V
V

= 1V - 1.4 3.0 Ω

LGATE

V

VSEN1 Rising 108 - 110 %

VSEN1 Rising 92 - 94 %

= 4.5V

OCSET

= 2.0V

= -4mA - - 0.8 V

= -4mA - - 0.8 V

= 1V - 1 - A

LGATE1

DC

DC

170 200 230 µA

-28- µA

Typical Performance Curve

140

C

= C

UGATE1

= 5V

V

IN

120

VCC = 12V

100

80

(mA)

CC

60

I

40

20

0

100 200 300 400 500 600 700 800 900 100

FIGURE 4. BIAS SUPPLY CURRENT vs FREQUENCY

= C

UGATE2

SWITCHING FREQUENCY (kHz)

LGATE1

= C

C = 4800pF

C = 3600pF

C = 1500pF

C = 660pF

Functional Pin Descriptions
VCC (Pin 28)

Provide a 12V bi as s upp ly fo r t he IC t o this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.

GND (Pin 17)

Signal ground for the IC. All voltage levels are measured
with respect to this pin.

PGND (Pin 24)

This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.

VAUX (Pin 16)

Connect this pin t o the ATX 3.3V output. The voltage present
at this pin is monitored for sequencing purposes. This pin
provides the necessary base bias for the NPN pass
transistors, as well as the current sunk through the 5kΩ VID
pull-up resistors.

SS13 (Pin 13)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the soft-start
interval of the sync hronous sw itching con verter (V
the AGP regulator (V

). A VTTPG high signal is also

OUT3

OUT1

) and

delayed by the time interval required by the charging of this
capacitor from 0V to 1.25V (see Soft-Start details).

SS24 (Pin 12)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the soft-start
interval of the st andard buck co nverter. Pulling this pin below

0.8V induces a chip reset (POR) and shutdown.

VTTPG (Pin 9)

VTTPG is an open collector output used to indicate the
status of the st andard buck regul ator output volt age. This pin
is pulled low when the output is below the under-voltage
threshold or when the SS13 pin is below 1.25V.

5

ISL6523A

PGOOD (Pin 8)

PGOOD is an open collector output used to indicate the
status of the output voltages. Th is pi n i s p ul led low when the
synchronous regulator output is not within

±10% of the

DACOUT reference vol tage or w hen any of the other o utputs
is below its under-voltage threshold.

VID3, VID2, VID1, VID0, VID25 (Pins 3-7)

VID3-25 are the TTL-compatible input pins to the 5-bit DAC.
The logic states of these five pins program the internal
voltage reference (D ACOUT). The leve l of DACOUT set s the
microprocessor core converter output voltage (V

OUT1

), as
well as the corresponding PGOOD and OVP thresholds.
Each VID pin is connected to the VAUX pin through a 5kΩ
pull-up resistor.

OCSET1, OCSET2 (Pins 23, 10)

Connect a resistor (R
drain of the corresponding upper MOSFET. R
internal 200µA current source (I
MOSFET’s on-resistance (r
current (OC) trip point according to the following equation:

I

PEAK

I

----------------------------------------------------=

×

OCSETROCSET

r

DS ON()

An overcurrent trip cycles the soft-start function.
The voltage at OCSET1 pin is monitored for power-on reset

(POR) purposes.

) from one of these pins to the

OCSET

), and the upper

OCSET

) set the converter over-

DS(ON)

OCSET

, an

PHASE1, PHASE2 (Pins 26, 2)

Connect the PHASE pins to the respective PWM converter’s
upper MOSFET sources. These pins represent the gate
drive return current p ath and a re used to monitor the volt age
drop across the upper MOSFETs for overcurrent protection.

UGATE1, UGATE2 (Pins 27, 1)

Connect UGATE pins to the respective PWM converters’
upper MOSFET gate. These pins provide the gate drive for
the upper MOSFETs.

LGATE1 (Pin 25)

Connect LGATE1 to the synchronous PWM converter’s
lower MOSFET gate. Th is p in pro vid es th e gat e d riv e for the
lower MOSFET.

COMP1 and FB1 (Pins 20, 21)

COMP1 and FB1 are the available external pins of the
synchronous PWM regulator error amplifier. The FB1 pin is
the inverting input of the error amplifier. Similarly, the
COMP1 pin is the error am plifier output. Th ese pins are us ed
to compensate the voltage-mode control feedback loop of
the synchronous PWM converter.

VSEN1 (Pin 22)

This pin is connected to the synchronous PWM converters’
output voltage. The PGOOD and OVP comparator circuits
use this signal to report output voltage status.

VSEN2 (Pin 11)

Connect this pin to the output of the standard buck PWM
regulator. The voltage at this pin is regulated to a 1.5 V le ve l.
This pin is also monitored for under-voltage events.

DRIVE3 (Pin 18)

Connect this pin to the gate/base of a N-type external pass
transistor (MOSFET or bipolar). This pin provides the drive
for the 1.5V regulator’s pass transistor.

VSEN3 (Pin 19)

Connect this pin to the output of the 1.5V linear regulator.
This pin is monitored for undervoltage events.

DRIVE4 (Pin 15)

Connect this pin t o t he ba se of an external b ip ola r tra ns istor.
This pin provides the drive for the 1.8V regulator’s pass
transistor.

VSEN4 (Pin 14)

Connect this pin to the output of the linear 1.8V regulator.
This pin is monitored for undervoltage events.

Description

Operation

The ISL6523A monitors and precisely controls 4 output voltage
levels (Refer to Figures 1, 2, 3). It is designed for
microprocessor computer applications with 3.3V , 5V, and 12V
bias input from an ATX power supply. The IC has 2 PWM and
two linear controllers. The first PWM controller (PWM1) is
designed to regulate the microprocessor core voltage (V
PWM1 controller drives 2 MOSFETs (Q1 and Q2) in a
synchronous-rectified buck converter and regulates the core
voltage to a level programmed by the 5-bit digital-to-analog
converter (DAC). The second PWM controller (PWM2) is
designed to regulate the AGTL+ bus voltage (V

OUT2

controller drives a MOSFET (Q3) in a standard buck converter
and regulates the output voltage to a level of 1.2V. The two
linear controllers supply the 1.5V advanced graphics port
(AGP) bus power (V
(V

).

OUT4

) and the 1.8V chipset core power

OUT3

Initialization

The ISL6523A automatically initializes in ATX-based
systems upon receipt of input power. The Power-On Reset
(POR) function continually monitors the input supply
voltages. The POR monitors the bias vol tage (+1 2V
VCC pin, the 5V input voltage (+5V
and the 3.3V input voltage (+3.3V
normal level on OCSET1 is equal to +5V
voltage drop (se e o ver cu rrent pro tec tio n). The POR function
initiates soft-start operation after all supply voltages exceed
their POR thresholds.

) at the OCSET1 pin,

IN

) at the VAUX pin. The

IN

less a fixed

IN

OUT1

). PWM2

) at the

IN

).

6

ISL6523A

Soft-Start

The 1.8V supply designed to power the chipset (OUT4), cannot
lag the ATX 3.3V by more than 2V , at any time. To meet this
special requirement, the linear block controlling this output
operates independently of the chip’s power-on reset. Thus,
DRIVE4 is driven to raise the OUT4 voltage before the input
supplies reach their POR levels. As seen in Figure 5, at time T0
the power is turned on and the input supplies ramp up.
Immediately following, OUT4 is also ramped up, lagging the
ATX 3.3V by about 1.8V. At time T1, the POR function initiates
the SS24 soft-start sequence. Initially, the voltage on the SS24
pin rapidly increases to approximately 1V (this minimizes the
soft-start interval). Then, an internal 28µA current source
charges an external capacitor (C
about 4.5V. As the SS24 voltage increases, the PWM2 error
amplifier allows generation of PHASE pulses of increasing
width that charge the output capacitor(s), providing a smooth
transition to the final set voltage. The OUT4 reference (clamped
to SS24) increasing past the intermediary level, established
based on the ATX 3.3V presence at the VAUX pin, brings the
output in regulation soon after T2.

ATX 12V

10V

ATX 5V

SS24

0V

3.0V

ATX 3.3V

V

OUT4

(1.8V)

) on the SS24 pin to

SS24

VTTPG

SS13

PGOOD

V

OUT1

(1.65V)

As the SS13 pin voltage increases, the pulse-width on the
PHASE1 pin increases, bringing the OUT1 output within
regulation limits. Similarly, the SS13 voltage clamps the
reference voltage for OUT3, enabling a controlled output
voltage ramp-up. At time T4, all output voltages are within
power-good limits, situation reported by the PGOOD pin
going high.

The T2 to T3 time interval is dependent upon the value of
C

. The same capacitor is also responsible for the ramp-

SS13

up time of the OUT1 and OUT3 voltages. If selecting a
different capacitor then recommend ed in the circuit application
literature, consider the effects the dif f erent value will hav e on
the ramp-up time and inrush currents of the OUT1 and OUT3
outputs.

Fault Protection

All four outputs a re monitored a nd protected ag ainst extr eme
overload. The chip’s response to an output overload is
selective, depending on the faulting output.

An overvoltage on V
1, 2, and 3, and latches the IC off. An under-voltage on
V

output latches the IC off. A single overcurrent event

OUT4

on outputs 1 or 2, or an under-voltage event on output 3,
increments the respective fault counter and triggers a
shutdown of outputs 1, 2, and 3, followed by a soft-start re­start. After three consecutive fault events on either counter,
the chip is latched of f. Removal of bi as power resets both the
fault latch and the counters. Both counters are also reset by
a successful start -up of all the out puts.

UV3

OC1

SS13

SS13UP

4V

output (VSEN1) disables outputs

OUT1

OC

LATCH

SRQ

>

COUNTER

R

INHIBIT1,2,3

SSDOWN

V

(1.2V)

OUT2

V

(1.5V)

OUT3

0V

T1 T2 T4T0 T5

FIGURE 5. SOFT-START INTERVAL

T3

TIME

As OUT2 increases past the 90% power-good level, the second
soft-start (SS13) is released. Between T2 and T3, the SS13
pin voltage ramps from 0V to the valley of the oscillator’s
triangle wave (at 1.25V). Contingent upon OUT2 remaining
above 1.08V, the first PWM pulse on PHASE1 triggers the
VTTPG pin to go high. The oscillator’s triangular wave form
is compared to the clamped error amplifier output voltage.

7

0.8V

SS24

SS24UP

4V

OV

UV4

OC2

FIGURE 6. FAULT LOGIC - SIMPLIFIED SCHEMATIC

POR

SRQ

OC

LATCH

COUNTER

FAULT
LATCH

S

Q

Q

R

R

>

FAULT

Figure 6 shows a simplified schematic of t he fault logic. The
overcurrent latches are set depend ent upon the st ates of the
overcurrent (OC1 and OC2), output 3 under-voltage (UV3)

I

ISL6523A

and the soft-start signals (SS13, SS24). Window
comparators monitor the SS pins and indicate when the
respective C

pins are fully charged to above 4.0V (UP

SS

signals). An under-volta ge on eith er linea r output (VSEN3 or
VSEN4) is ignored until the respective UP signal goes high.
This allows V

OUT3

and V

to increase without fault at

OUT4

start-up. Followi ng an overcurrent event (O C1, OC2, or UV3
event), bringing the SS24 pin below 0.8V resets the
overcurrent latch and generates a soft-started ramp-up of
the outputs 1, 2, and 3.

OUT1 Overvoltage Protection

During operation, a short across the synchronous PWM
upper MOSFET (Q1) causes V

to increase. When the

OUT1

output exceeds the over-voltage threshold of 120% of
DACOUT, the over-voltage comparator trips to set the fault
latch and turns the lower MOSFET (Q2) on as needed to
regulate the output voltage to the 120% threshold. This
operation typically results in the blow of the input fuse,
subsequent discharge of V

OUT1

.

A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltage s above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2, is driven on.

Overcurrent Protection

All outputs are protected against excessive overcurrents.
Both PWM controllers use the upper MOSFET’s on­resistance, r
against shorted outputs. Both linear regulators monitor their
respective VSEN pins for under-voltage to protect against
excessive current s.

Figure 7 illustrates the overcurrent protec tion with an overload
on OUT2. The overload is applied at T0 and the current
increases through the inductor (L
comparator trips when the voltage acros s Q3 (i
exceeds the level programmed by R
outputs 1, 2, and 3, discharges s oft-start cap acitor C
28µA current sink, and increments the counter. Soft-start
capacitor C

SS13

and initiates a soft-st art cycle with th e error amplifiers clamped
by soft-start. With OUT2 still overloaded, the inductor current
increases to trip the overcurrent comparator. Again, this
inhibits the outputs, but the soft-st art vol tage continues
increasing to above 4.0V before discharging. The counter
increments to 2. The soft-start cyc le repeats at T3 and trips
the overcurrent comparator. The SS pin voltage increases to
above 4.0V at T4 and the counter increments to 3. This sets
the fault latch to disable the converter.

The PWM1 controller oper ates in the same way as PWM2 to
overcurrent faults. Additionally, the two linear controllers
monitor the VSEN pins for under-voltage. Should excessive
currents cause VSEN3 or VSEN4 to fall below the linear
under-voltage threshold, the respective UV signals set the

to monitor the current for protection

DS(ON)

). At time T1, the OC2

OUT2

OCSET

is quickly discharged. C

SS24

• r

D

DS(ON)

. This inhibits

SS24

recharges at T2

)

with

OC latch or the FAULT latch, providing respective C

SS

capacitors are fully charged. Blanking the UV signals during the
C

charge interval allows the linear outputs to build above

SS

the under-voltage threshold during normal ope ration. Cycling
the bias input power off then on resets the counter and the
fault latch.

CHIP

1

FAULT

LATCH

0

4V

2V

SS13

SS24

0V

0A

INDUCTOR CURRENT

Resistors (R

COUNT

= 1

OVERLOAD

APPLIED

T1 T2 T3T0 T4

FIGURE 7. OVERCURRENT OPERATION

OCSET1

and R

DISABLED

COUNT

= 2

TIME

OCSET2

COUNT

= 3

) program the overcurrent
trip levels for each PWM converter. As shown in Figure 8, the
internal 200µA current sink (I
R

OCSET (VSET

) that is referenced to VIN. The DRIVE signal

) develops a voltage across

OCSET

enables the overcurrent comparator (OVERCURRENT1 or
OVERCURRENT2). When the voltage across the upper
MOSFET (V
comparator trips to set the overcurrent latch. Both V
V

are referenced to VIN and a small capacitor across

DS

R

OCSET

helps V

DS(ON)

OCSET

) exceeds V

, the overcurrent

SET

track the variations of VIN due to

SET

and

MOSFET switching. The overcurrent function will trip at a peak
inductor current (I

I

OCSETROCSET

=

PEAK

----------------------------------------------------

r

DS ON()

determined by:

PEAK)

×

The OC trip point varies with MOSFET’s rDS(ON)
temperature variation s. To avoid overcurrent tripping in the
normal operating load range, determine the ROCSET
resistor value from the equation above with:

1. The maximum r

2. The minimum I

3. Determine I

PEAK

at the highest junction temperature

DS(ON)

from the specification table

OCSET

for I

PEAK

> I

OUT(MAX)

+ (∆I) /2,

where ∆I is the outp ut indu ctor rip ple cur rent .

For an equation for the ripple current see the section under
component guidelin es t itl ed ‘Out put Induct or Se le cti on’.

8

ISL6523A

OVERCURRENT TRIP:

VDSV

>

iDr

× I

DS ON()

OVER-

CURRENT

OC

+

-

PWM

CONTROL

FIGURE 8. OVERCURRENT DETECTION

SET

×>

OCSETROCSET

OCSET

I

OCSET

200µA

DRIVE

GATE

R

OCSET

V

VCC

UGATE

PHASE

V

PHASEVINVDS

V

OCSETVINVSET

SET

+

VIN = +5V

i

D

+

V

DS

–=

–=

OUT1 Voltage Program

The output voltage of the PWM1 converter is programmed to
discrete levels between 1.050V and 1.825V. This output
(OUT1) is designed to supply the core voltage of Intel’ s
advanced microprocessors. The voltage identification (VID)
pins program an internal voltage reference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter (DAC). The
level of DACOUT also sets the PGOOD and OVP thresholds.
Table 1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, since they are internally
pulled to the V A UX pin thro ugh 5kΩ res istors. C hanging the
VID inputs during operation is not recommended and could
toggle the PGOOD signal and exercise the overvolt age
protection. The output voltage program is Intel VRM8.5
compatible.

TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM

PIN NAME NOMINAL

010001.050

010001.050

010011.075

001101.100

001111.125

001001.150

001011.175

000101.200

000111.225

000001.250

000011.275

111101.300

111111.325

111001.350

111011.375

110101.400

110111.425

DACOUT

VOLTAGEVID3 VID2 VID1 VID0 VID25

TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM (Continued)

PIN NAME NOMINAL

110001.450

110011.475

101101.500

101111.525

101001.550

101011.575

100101.600

100111.625

100001.650

100011.675

011101.700

011111.725

011001.750

011011.775

010101.800

010111.825

NOTE: 0 = connected to GND, 1 = open or connected to 3.3V
through pull-up resistors

DACOUT

VOLTAGEVID3 VID2 VID1 VID0 VID25

Application Guidelines

Soft-Start Interval

Initially, the soft-st art function clamps the error amplifier’s output
of the PWM converters. This generates PHASE pulses of
increasing width that charge the output capacitor(s). The
resulting output voltages start-up as shown in Figure 5.

The soft-start functio n contro ls the ou tput vo ltag e rat e of rise
to limit the current surge at start-up. The soft-start interval
and the surge current are programmed by the soft-start
capacitor, C
increases the peak surge current. Using the recommended

0.1µF soft start capacitors ensure all output voltages ramp
up to their set v al ues i n a q uic k an d c on trol led fashion, while
meeting the system timing requirements.

Shutdown

Neither PWM output switches until the soft-start voltage
(V

) exceeds the oscillator’s valley voltage. Additionally,

SS

the reference on each linear’s amplifier is clamped to the
soft-start voltage. Holding the SS24 pin low (with an open
drain or open collecto r signa l) turns off regulat ors 1, 2 a nd 3.
Regulator 4 (MCH) will simply drop its output to the
intermediate soft-start level. This output is not allowed to
violate the 2V maximum potential gap to the ATX 3.3V
output.

. Programming a faster soft-start interval

SS

9

ISL6523A

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit desig n min im ize s the vol t ag e
spikes in the c onverter. Consider, a s an exam ple, th e turn-of f
transition of the upper MOSFET. Prior to turn-off, the upper
MOSFET was carrying the full load current. During the turn­off, current stop s flowing in the uppe r MOSFET and is picked
up by the lower MOSFET or Schottky diode. Any inductance
in the switched current path generates a large voltage spike
during the switching interval. Careful component selection,
tight layout of the c ritica l comp onent s, an d short , wide circu it
traces minimize the magnitude of voltage spikes.

There are two sets of critical components in a DC-DC
converter using an ISL6523A controller. The switching
power component s are the mo st crit ical b ecaus e they sw itch
large amounts of e nergy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.

The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high­frequency ceramic de-coupling capacitors, clos e to the
power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate the
PWM controller close to the MOSFETs.

The critical small signal components include the bypass
capacitor fo r VCC and the soft-start capacitor, C
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from any SS
node, since the internal current source is only 28µA.

A multi-layer printed circuit board is recommend ed. F igu re 9
shows the connections of the critical components in the
converter. Note that the capacitors C

and C

IN

could represent numero us physica l capacit ors. Dedicate o ne
solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another so lid la yer as a po wer plane an d break thi s
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dV /dt volt age s, the
stray capacitor formed between these islands and the
surrounding circui try will te nd to co uple sw itch ing noi se. Us e

OUT

. Locate

SS

each

the remaining printed circuit layers for small signal wiring.
The wiring traces from the control IC to the MOSFET gate
and source should be sized to carry 2A peak currents.

L

IN

LOAD

OUT3

LOAD

+3.3V

IN

C

IN

+12V

C

C

OCSET2

R

OCSET2

Q3

L

OUT2

C

CR2

OUT2

C

SS24,13

C

OUT3

Q4

IN

KEY

ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA/THROUGH-HO LE CONN EC TIO N TO GROU ND PLAN E

VCC

OCSET2

UGATE2

PHASE2

SS24

SS13

ISL6523A

DRIVE3

PGND

GNDVCC

OCSET1

UGATE1

PHASE1

LGATE1

DRIVE4

C

OCSET1

Q2

Q5

R

OCSET1

Q1

L

OUT1

CR1

C

C

OUT1

OUT4

V

V

OUT4

OUT1

LOAD

LOAD

+5V

V

OUT2

V

FIGURE 9. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

PWM1 Controller Feedback Compensation

Both PWM controllers use voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller requiring external
compensation. Apply these methods and considerations
only to the synchrono us PWM control ler. The considerations
for the standard PWM controller are presented separately.

Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V

) is regulated to the Reference voltage level. The

OUT

reference voltage level is the DAC output voltage (DACOUT)
for PWM1. The error amplifier output (V
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V
The PWM wave is smoothed by the output filter (L

The modulator transfer function is the small-signal transfer
function of V

OUT/VE/A

Gain, given by V

. This function is dominated by a DC

IN/VOSC

, and shaped by the output filter , with

a double pole break frequency at F

) is compared with

E/A

at the PHASE node.

IN

and a zero at F

LC

and CO)..

O

ESR

.

10

F

1

F

1

N

P

L

ISL6523A

V

IN

L

O

PHASE

(PARASITIC)

IN

Z

FB

Z

IN

C3

R1

FB

R3

C

ESR

V

O

OUT

V

OUT

∆V

OSC

OSC

PWM

COMP

­+

Z

V

E/A

FB

-

+

ERROR
AMP

DETAILED COMPENSATION COMPONENTS

COMP

ISL6523A

DRIVER

DRIVER

REFERENCE

C2

C1

R2

-

+

DACOUT

Z

FIGURE 10. VOLT AGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

Modulator Break Frequency Equations

F

LC

2π L

××

OCO

F

ESR

1

----------------------------------------=

The compensation network consists of the error amplifier
(internal to the ISL6523A) and the impedance networks Z
and Z

. The goal of the compensation network is to provide a

FB

closed loop transfer function with high 0dB crossing frequency
(f

) and adequate phase margin. Phase margin is the

0dB

difference between the closed loop phase at f
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 10. Use these guidelines for locating the poles
and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1

3. Place 2

4. Place 1

5. Place 2

ST

Zero Below Filter’s Double Pole (~75% FLC)

ND

Zero at Filter’s Double Pole

ST

Pole at the ESR Zero

ND

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

1

-----------------------------------------=

2π ESR C

and 180o.

0dB

××

O

IN

Compensation Break Frequency Equations

-------------------------------------------------------=

Z1

Z2

-----------------------------------=

2π R× 2C1×

-------------------------------------------------------=

2π R1 R3+()C3××

1

F

P1

2π R

F

-----------------------------------=

P2

2π R× 3C3×

C1 C2×



----------------------

××

2



C1 C2+

1

Figure 11 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 11. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F

with the capabilities

P2

of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 11 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.

OPEN LOOP

ERROR AMP GAIN

V



IN

----------------- -

log

20



V



PP–

COMPENSATION

GAIN

CLOSED LOO

GAIN

10M1M100K10K1K10010

100

GAIN (dB)

-20

-40

-60

80

60

40

20

0

F

Z1

R2



------- -

log

20



R1

MODULATOR

GAIN

F

Z2

F

LCFESR

FREQUENCY (Hz)

F

F

P1

P2

FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAI

The compensation gain uses external impedance networks
Z

and ZIN to provide a stab le, high bandwid th (BW) overal l

FB

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.

PWM2 Controller Feedback Compensation

To reduce the number of external small-signal components
required by a typical application, the standard PWM
controller is internally stabilized. The only stability criteria
that needs to be m et relates the mini mum value o f the outpu t
inductor to the equivalent ESR of the output capacitor bank,
as shown in the following equation:

1.75

10

×

OUT MIN()

ESR

------------------------------------------------=

OUT

2 π× BW×

where
L

OUT(MIN)

current

- minimum output inductor value at full output

11

ISL6523A

ESR

- equivalent ESR of the output capacitor bank

OUT

BW - desired converter bandwidth (not to exceed 0.25 to

0.30 of the switching frequency)
The design procedure for this output should follow the

following steps:

1. Choose number and type of output capacitors to me et the
output transient requirements based on the dynamic
loading characteristics of the output.

2. Determine the equiv alent ESR of the o utput cap acitor
bank and calculate minimum output inductor value.

3. Verify that chosen inductor meets this minimum value
criteria (at full output load). It is recommended the
chosen output inductor be no more than 30% saturated
at full output load.

Oscillator Synchronization

The PWM controllers use a triangle wave for comparison
with the error amplifi er output to provide a pulse-width
modulated signal. Should the output voltage of the two
converters be programmed close to each other, then cross­talk between the converters could cause non-uniform
PHASE pulse-widths and increased output voltage ripple.
The ISL6523A avoids this pro blem by synchronizing th e two
converters 180

o

out of phase.

Component Selection Guidelines

Output Capacitor Selection

The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally , the PWM converters require an output c apacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.

PWM Output Capacitors

Modern microprocessors pr oduce tr ans ient lo ad r ates
above 1A/ns. High frequency capacitors initially supply the
transient current and slo w the load r at e-of -chan ge see n by
the bulk capacitors. The bul k fil ter capaci to r value s ar e
generally determ ine d by th e ES R (e ffect ive seri es
resistance) and voltage ra ti ng req uir e ments ra th er tha n
actual capacitance requirem ents.

edge. An aluminum electrolytic capacitor’s ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance (ESL)
of these capacitors increases with case size and can reduce
the usefulness of the capacitor to high slew-rate transient
loading. Unfortunately , ESL is not a spec ified parameter . W ork
with your capacitor supplier and measure the capa citor’s
impedance with frequency to select a suitable comp onent. In
most cases, multiple electrolytic capac itors of sm all cas e size
perform better than a single large case capacitor.

Linear Output Capacitors

The output capacitors for the linear regulators provide
dynamic load current. Thus capacitors C

OUT3

and C

OUT4

should be selected for transient loa d regul ati on.

PWM Output Inductor Selection

Each PWM converter requires an outpu t inductor . The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient. Additionally, PWM2 output inductor has to
meet the minimum value criteria for loop stability as
described in paragrap h ‘PWM2 Controller Feedback
Compensation’. The inductor value determines the
converter’s ripple current and the ripp le vo ltage is a function
of the ripple current. The ripple voltage and current are
approximated by the followi ng equ ati ons :

V

–

INVOUT

------------------------------- -

∆I

F

S

Increasing the value of induct ance re duces th e ripple c urrent
and voltage. However, large inductance values increase the
converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast cont rol loop desig n, the
ISL6523A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can m inimi ze the
output capacitance required.

V

OUT

--------------- -×=

L×

V

IN

∆ I∆ ESR×=

V

OUT

High frequency decoupling capacitors should be placed as
close to the power pins of the load as phy sically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple v oltage and
the initial voltage drop following a high slew-rate transient’ s

12

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

t

RISE

where: I

TRAN

response time to the application of load, and t

LOI

×

TRAN

------------------------------- -=
–

V

INVOUT

t

FALL

LOI

×

-------------------------------=

V

OUT

is the transient load current step, t

FALL

TRAN

RISE

is the

is the

response time to the removal of load. Be sure to check both

ISL6523A

of these equations at the minimum and maximum output
levels for the worst case response time.

Input Capacitor Selection

The important pa rameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maxim um input voltag e and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage. The maximum RMS current rating
requirement for the input capacitors of a buck regulator is
approximately 1/2 of t he DC outp ut load curren t. W orst -case
RMS current draw in a circuit employing the ISL6523A
amounts to the larges t RMS cu rren t dr aw of ei the r sw itchi ng
regulator (likely the RMS of V

). Operating at 180o out-

OUT1

of-phase, the input-side RMS current of both switchers is
less than the arithmetical sum of individual RMS input
currents.

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Smal l ceramic capacitors can be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.

For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised w ith re gard to th e ca p ac it or s urg e cu rrent
rating. These capacitors must be capable of handling the
surge current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.

MOSFET Selection/Considerations

The ISL6523A requires 5 external transistors. Three
N-channel MOSFETs are employed by the PWM convert ers.
The AGP and memory linear controllers can each drive a
MOSFET or a NPN bipolar as a pass transistor. All these
transistors should be selected based upon r
gain, saturation voltages, gate supply requirements, and
thermal management considerations.

DS(ON)

, current

The equations presented assume linear voltage-current
transitions and do not model power losses due to the lower
MOSFET’s body diode or the output capacitances
associated with either M OSFET. The gate charge losses are
dissipated by the contro ller IC (ISL 6523A) and do not
contribute to the MOSFETs’ heat rise. Ensure that both
MOSFETs are within their maximum junction temperature at
high ambient temperature by calculating the temperature
rise according to package thermal resistance specifications.
A separate heatsink may be necessary depending upon
MOSFET power , p ackage type , ambient te mperature a nd air
flow.

P

P

The r

UPPER

LOWER

DS(ON)

2

I

r

× V

O

------------------------------------------------------------

2

I

r

× VINV

O

---------------------------------------------------------------------------------=

×

DS ON()

V

IN

DS ON()

V

IN

is different for the two equations above even if

OUT

I

× tSW× FS×

OVIN

----------------------------------------------------+=

–()×

OUT

2

the same device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 12 shows the gate drive where the
upper MOSFET’s gate-to-source voltage is approximately
V

less the input supply. For +5V main power and +12VDC

CC

for the bias, the approximate gate-to-source voltage of Q1 is
7V. The lower gate drive voltage is 12V. A logic-le vel
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if it s absolute gate-to-source vo ltage rating
exceeds the maximum voltage applie d to V

+12V

ISL6523A

-

+

VCC

UGATE
PHASE

LGATE
PGND

GND

+5V OR LESS

Q1

Q2

.

CC

NOTE:
VGS ≈ VCC -5V

CR1

NOTE:

≈ V

V

GS

CC

PWM1 MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the dominant
design factors. The power dissipation includes two main loss
components: conduction losses and switching losses. These
losses are distributed between the upper and lower MOSFETs
according to the duty factor. The conduction losses are the
main component of power dissipation for the lower MOSFET s.
Only the upper MOSFET has significant switching losses, since
the lower device turns on and off into near zero voltage.

13

FIGURE 12. UPPER GATE DRIVE - DIRECT V

CC

DRIVE

Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. For best
results, the diode must be a surface-mount Schottky type to
prevent the parasitic MOSFET body diode from conducting. It
is acceptable to omit the diode and let the body diode of the
lower MOSFET clamp the negative inductor swing, but one
must ensure the PHASE node negative voltage swing does
not exceed -3V to -5V peak. The diode's rated reverse

P

ISL6523A

breakdown voltage must be equal or greater to 1.5 times the
maximum input voltage.

PWM2 MOSFET and Schottky Selection

The power di ssipation in PWM2 converter is similar to
PWM1 except that the power losses of the lower device are
dissipated in the Schottky. The equations below describe an
approximation of this power loss distribution and assume
linear voltage-current switching transitions.

2

I

r

P

P

MOS

SCH

× V

O

------------------------------------------------------------

IOVf× VINV

-------------------------------------------------------------=

×

DS ON()

V

IN

–()×

V

IN

OUT

OUT

× tSW× FS×

I

OVIN

----------------------------------------------------+=

2

Linear Controllers Transistor Selection

The ISL6523A linear controllers are compatible with both
NPN bipolar as well as N-cha nne l M OSF ET tran si sto r s. T he
main criteria for selection of pass transistors for the linear

regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is

LINEARIOVINVOUT

–()×=

Select a package and heatsink that maintains the junction
temperature below the maximum desired temperature with
the maximum expected ambient temperature.

When selecting bipolar NPN transistors for use with the
linear controllers, insure the current gain at the given
operating V

is sufficiently large to provide the desired

CE

output load current when the base is fed with the minimum
driver output current.

In order to ensure the strict timing/level requirement of
OUT4, an NPN transistor is recomm ended fo r use as a pas s
element on this output (Q5). An low gate threshold NMOS
could be used, but meeting the requirements would then
depend on the VCC bias being sufficiently high to allow
control of the MOSFET.

14

ISL6523A

ISL6523A DC-DC Converter Application
Circuit

Figure 13 shows an application circuit of a power supply for
a microprocessor computer system. The power supply
provides the micropro cessor core v olt age (V
bus voltage (V

+5V

+12V

+3.3V

GND
GND

GND

V

(VTT)

OUT2

+1.2V

R7

10kΩ

VTT

POWER GOOD

(AGP)

V

OUT3

+1.5V

(MCH)

V

OUT4

+1.8V

), the G T L bus voltage (V

OUT2

Q3

HUF76121

L2

2.0µH

+

C7

1000µF

Q4

HUF76107

+

C18

560µF

Q5

2SD1802

+

C21
560µF

C3

1nF

R2

2.2kΩ

CR1

HSM835

+

C15

10µF

PHASE2

OUT1

OUT3

OCSET2

UGATE2

VSEN2

VTTPG

VAUX

DRIVE3

VSEN3

DRIVE4

VSEN4

), the AGP

), and the

L1

1µH

C2

1µF

10

1

2

11

9

U1

ISL6523A

16

18

19

15

14

28

17

VCC

GND

memory controller hu b volt age (V

) from +3.3V , +5VDC,

OUT4

and +12VDC. For detailed information on the circuit,
including a Bill-o f-Materials and circui t board des cription, see
Application Note AN9925. Also see the Intersil web site at
www.intersil.com

+

C1

680µF

C5

23

8

27
26

25

24

22

21

20

7

6
5
4
3

12

13

OCSET1

PGOOD

UGATE1

PHASE1

LGATE1

PGND

VSEN1
FB1

COMP1

VID25

VID0
VID1
VID2
VID3

SS24

SS13

C22

0.1µF

C4

1nF

1.5kΩ

2.2nF

R3

C13

270pF

C16

Q1

HUF76139

Q2

HUF76143

3.32kΩ

R11

43kΩ

C19

0.1µF

R8

R1

10kΩ

C14

22nF

1µF

L3

1.8µH

R5

4.99kΩ

R12

267kΩ

POWER GOOD

+

C8-10

3x1000µF

R10

33Ω

V

(CORE)

OUT1

+1.050V TO 1.825V

C12

0.30µF

R9

12.1k

15

FIGURE 13.

Small Outline Plastic Packages (SOIC)

N

1

ISL6523A

N

INDEX
AREA

123

SEATING PLANE

-A­D

e

B

0.25(0.010) C AM BS

M

E

-B-

A

-C-

0.25(0.010) BM M

H

α

µ

A1

0.10(0.004)

L

h x 45

o

OTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

0. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.

M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

C

h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1. 27 6

N28 287

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMINMAXMINMAX

-

All Intersil U.S. products are manufa ct ured , asse mbled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of In tersil or its subsidi ari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

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