intersil ISL6523A DATA SHEET

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ISL6523A

Data Sheet February 2002

VRM8.5 Dual PWM and Dual Linear Power
System Controller

The ISL6523A provides the powe r control and prote ct ion for
four output voltages in high-performance microprocessor
and computer applications. The IC integrates two PWM
controllers and two linear controllers, as well as the
monitoring and protection functions into a 28-pin SOIC
package. One PWM con trol ler regu late s th e m ic ropro ce ssor
core voltage with a synchronous-rectified buck converter.
The second PWM con t rol le r supplies the computer system’s
AGTL+ 1.2V bus power with a standard buck converter. The
linear controllers regulate power for the 1.5V AGP bus and
the 1.8V power for the chipset core voltage and/or cache
memory circuits.

The ISL6523A includes an Intel VRM8.5 compatible, TTL
5-input digital-to-a nalog converter (DAC) that adjusts the
microprocessor core-targeted PWM output voltage from

1.050V to 1.825V in 25mV steps. The precision reference
and voltage-mode control provid e ±1% stati c regu lation . The
second PWM controller’s output provides a voltage level of

1.2V with ±3% accuracy. The linear regulators use external
N-channel MOSFETs or bipolar NPN pass transistors to
provide fixed o utput volt ages of 1. 5V ±3% (V
±3% (V

OUT4

).

OUT3

) and 1.8V

The ISL6523A monitors all the output voltages. A delayed­rising VTT (standard buck output) Power Good signal is
issued before the core PWM starts to ramp up. Another
system Power Good signal is issued when the core is within
±10% of the DAC setting and all other outputs are above
their under- voltage levels. Additional built-in overvoltage
protection for the core output uses the lower MOSFET to
prevent output vol tages above 115% of the DAC setting. Th e
PWM controllers’ overcurrent function monitors the output
current by using the voltage drop across the upper
MOSFET’s r

, eliminating the need for a current

DS(ON)

sensing resistor.

Ordering Information

PART NUMBER

ISL6523ACB 0 to 70 28 Ld SOIC M28.3
ISL6523EVAL1 Evaluation Board

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

FN9063

Features

• Provides 4 Regulated Voltages

- Microprocessor Core, AGTL+ Bus, AGP Bus Power,
and North/South Bridge Core

• Drives N-Channel MOSFETs

• Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors

• Simple Single-Loop Control Designs

- Voltage-Mode PWM Control

• Fast PWM Converter Transient Response

- High-Bandwidth Error Amplifiers

- Full 0% to 100% Duty Ratios

• Excellent Output Voltage Regulation

- Core PWM Output . . . . . . . . . . ±1% Over T em perature

- All Other Outputs . . . . . . . . . . . . .±3% Over Temperature

• VRM8.5 TTL-Compatible 5-Bit DAC Microprocessor Core
Output Voltage Selection

- Wide Range . . . . . . . . . . . . . . . . . . . . 1.050V to 1.825V

• Power-Good Output Voltage Monitors

- Separate delayed VTT Power Good

• Overcurrent Fault Monitors

- Switching Regulators Do Not Require Extra Current

Sensing Elements, Use MOSFET’s r

DS(ON)

• Small Converter Size

- Constant Frequency Opera tio n

- 200kHz Internal Oscillator

Applications

•

Motherboard Power Regulation for Computers

Pinout

ISL6523A (SOIC)

TOP VIEW

VCC

UGATE2
PHASE2

VID3
VID2
VID1
VID0

VID25

PGOOD

VTTPG

OCSET2

VSEN2

SS24
SS13

VSEN4

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

UGATE1
PHASE1
LGATE1
PGND
OCSET1
VSEN1
FB1
COMP1
VSEN3
DRIVE3
GND
VAUX
DRIVE4

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002. All Rights Reserved

ISL6523A

VCC

OCSET1

VSEN1

POWER-ON

VAUX

RESET (POR)

PGOOD

200µA

-

+

1.10

x

-

+

0.90

x

-

+

1.15

x

VCC

DRIVE1

UGATE1

+

OC1

PHASE1

-

LGATE1

VCC

GATE

CONTROL

PWM1

PWM

COMP1

-

+

EA1

-

+

DRIVE

SYNCH

PGND

GND

TTL D/A

CONVERTER

DACOUT

28µA

(DAC)

VID25

VID0

VID1

VID3 VID2

COMP1

FB1

4.5V

OV

SS24

200µA

OCSET2

UV3

UV4

-

-

+

+

OC2

+

-

-

+

VSEN3

VAUX

1.5V

-

+

EA3

x0.75

x0.75

+

1.8V

-

+

-

EA4

DRIVE2

VCC

PWM

INHIBIT

SOFT-

LOGIC

START

& FAULT

FAULT

COMP2

+

-

PWM2

GATE

CONTROL

VCC

EA2

-

+

UV2

-

28µA

+

SET

1.2V

x0.90

+

4.5V

FIGURE 1. BLOCK DIAGRAM

SS13

OSCILLATOR

>

D

CLK

CLR

Q

Q

VTTPG

-

DRIVE3

2

DRIVE4

VSEN4

UGATE2

PHASE2

VSEN2

+5V

+12V

ISL6523A

IN

+3.3V

V

OUT2

1.2V

+5V

Q1

V

OUT1

V

OUT2

Q3

PWM2

CONTROLLER

PWM1

CONTROLLER

Q2

ISL6523A

IN

V

OUT3

Q4

LINEAR

CONTROLLER

LINEAR

CONTROLLER

Q5

V

OUT4

FIGURE 2. SIMPLIFIED POWER SYSTEM DIAGRAM

IN

IN

L

IN

C

IN

VCC

OCSET1

PGOOD

UGATE1
PHASE1

Q1

L

OUT1

POWERGOOD

V

OUT1

1.3V to 3.5V

C

OUT2

L

OUT2

CR2

Q3

OCSET2

UGATE2
PHASE2

VTT POWERGOOD

+3.3V

IN

V

OUT3

1.5V
C

OUT3

V

OUT4

1.8V
C

OUT4

Q5

Q4

C

VSEN2

VTTPG

ISL6523A

VAUX

DRIVE3

VSEN3

DRIVE4

VSEN4

SS24

SS24

FIGURE 3. TYPICAL APPLICATION

GND

LGATE1
PGND

VSEN1

FB1

COMP1

VID3
VID2
VID1

VID0
VID25

SS13

C

SS13

Q2

C

OUT1

3

ISL6523A

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V

PGOOD, RT/FA ULT, DRIVE, PHASE, and

GAT E Voltage. . . . . . . . . . . . . . . . . . . GND - 0.3V to V

Input, Output or I/O Voltage. . . . . . . . . . . . . . . . . . G ND -0.3V to 7V

CC

+ 0.3V

ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Resistance (Typical, Note 1)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

Recommended Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Tem perature Range. . . . . . . . . . . . . . . . . . . . 0

Junction Temper ature Range. . . . . . . . . . . . . . . . . . . 0

CAUTION: Stresses above those li sted in “Abs olute Maxi mum Ratings” may cause perman ent damag e to the device. T his is a stress on ly rating an d operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

o

C to 70oC

o

C to 125oC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply Current I

CC

POWER-ON RESET

Rising VCC Threshold - - 10.4 V
Falling VCC Threshold 8.2 - - V
Rising VAUX Threshold -2.5- V
VAUX Threshold Hysteresis -0.5- V
Rising V

Threshold -1.26- V

OCSET1

OSCILLATOR

Free Running Frequency F
Ramp Amplitude ∆V

OSC

OSC

DAC AND STANDARD BUCK REGULATOR REFERENCE

DAC (VID25-VID3) Input Low Voltage --0.8V
DAC (VID25-VID3) Input High Voltage 2.0 - - V
DACOUT Voltage Accuracy -1.0 - +1.0 %
PWM2 Regulation Voltage -1.2- V
PWM2 Regulation Voltage Tolerance -3- %

1.5V AND 1.8V LINEAR REGULATORS (V

OUT3

AND V

Regulation Tolerance -3- %
VSEN3 Regulation Voltage VREG
VSEN4 Regulation Voltage VREG
VSEN3,4 Under-Voltage Level VSEN3,4
VSEN3 Under-Voltage Hysteresis VSEN3 Falling - 7 - %
Output Drive Current VAUX-V

SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER

DC Gain Note 2 - 88 - dB
Gain-Bandwidth Product GBWP Note 2 - 15 - MHz
Slew Rate SR COMP1 = 10pF, Note 2 - 6 - V/µs

PWM CONTROLLERS GATE DRIVERS

UGATE1,2 Source I
UGATE1,2 Sink R

UGATE

UGATEVGATE-PHASE

UGATE1, LGATE1, UGATE2, DRIVE3, and

-9- mA

DRIVE4 Open

185 200 215 kHz

-1.9- V

)

OUT4

3
4

VSEN3,4 Rising - 75 - %

UV

DRIVE3,4

VCC = 12V, V

> 0.6V 20 40 - mA

UGATE1

(or V

) = 6V - 1 - A

UGATE2

-1.5- V

-1.8- V

= 1V - 1.7 3.5 Ω

θ

(oC/W)

JA

o

C to 150oC

P-P

o

C

o

C

4

0

ISL6523A

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

LGATE Source I
LGATE Sink R

PROTECTION

VSEN1 Over-Voltage (VSEN1/DACOUT) VSEN1 Rising - 120 - %
OCSET1,2 Current Source I
Soft-Start Current I

POWER GOOD

VSEN1 Upper Threshold
(VSEN1/DACOUT)

VSEN1 Under-Voltage
(VSEN1/DACOUT)

VSEN1 Hysteresis (VSEN1/D AC O UT ) VSEN1 Falling - 2 - %
PGOOD Voltage Low V
VSEN2 Under-Voltage VSEN2 Rising - 1.00 - V
VSEN2 Hysteresis VSEN2 Falling - 60 - mV
VTTPG Voltage Low V

NOTE:

2. Guaranteed by design

LGATE

LGATE

OCSET

SS13,24VSS13,24

PGOODIPGOOD

VTTPGIVTTPG

VCC = 12V, V
V

= 1V - 1.4 3.0 Ω

LGATE

V

VSEN1 Rising 108 - 110 %

VSEN1 Rising 92 - 94 %

= 4.5V

OCSET

= 2.0V

= -4mA - - 0.8 V

= -4mA - - 0.8 V

= 1V - 1 - A

LGATE1

DC

DC

170 200 230 µA

-28- µA

Typical Performance Curve

140

C

= C

UGATE1

= 5V

V

IN

120

VCC = 12V

100

80

(mA)

CC

60

I

40

20

0

100 200 300 400 500 600 700 800 900 100

FIGURE 4. BIAS SUPPLY CURRENT vs FREQUENCY

= C

UGATE2

SWITCHING FREQUENCY (kHz)

LGATE1

= C

C = 4800pF

C = 3600pF

C = 1500pF

C = 660pF

Functional Pin Descriptions
VCC (Pin 28)

Provide a 12V bi as s upp ly fo r t he IC t o this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.

GND (Pin 17)

Signal ground for the IC. All voltage levels are measured
with respect to this pin.

PGND (Pin 24)

This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.

VAUX (Pin 16)

Connect this pin t o the ATX 3.3V output. The voltage present
at this pin is monitored for sequencing purposes. This pin
provides the necessary base bias for the NPN pass
transistors, as well as the current sunk through the 5kΩ VID
pull-up resistors.

SS13 (Pin 13)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the soft-start
interval of the sync hronous sw itching con verter (V
the AGP regulator (V

). A VTTPG high signal is also

OUT3

OUT1

) and

delayed by the time interval required by the charging of this
capacitor from 0V to 1.25V (see Soft-Start details).

SS24 (Pin 12)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the soft-start
interval of the st andard buck co nverter. Pulling this pin below

0.8V induces a chip reset (POR) and shutdown.

VTTPG (Pin 9)

VTTPG is an open collector output used to indicate the
status of the st andard buck regul ator output volt age. This pin
is pulled low when the output is below the under-voltage
threshold or when the SS13 pin is below 1.25V.

5