®
www.BDTIC.com/Intersil
ISL6506, ISL6506A, ISL6506B
Data Sheet May 7, 2008
Multiple Linear Power Controller with
ACPI Control Interface
The ISL6506 complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
integrates the control of the 5V
an 8 Ld EPAD SOIC p ackage. The ISL6506 operating mode
(active outputs or sleep outputs) is selectable through two
digital control pins; S3
and S5.
A completely integrated linear regulator generates the
3.3V
voltage plane from the ATX supply’s 5VSB output
DUAL
during sleep states (S3, S4/S5). In active states (during S0
and S1/S2), the ISL6506 uses an external N-Channel pass
MOSFET to connect the outputs directly to the 3.3V input
supplied by an ATX power supply, for minimal losses.
The ISL6506 powers up the 5V
the ATX 5V output through an NMOS transistor in active
states, or by switching in the ATX 5V
PNP) transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6506 and ISL6506B 5V
ISL6506A, the 5V
DUAL
DUAL
output stays on during S4/S5 sleep
states.
Functionally, the ISL6506 and ISL6506B are identical. The
ISL6506B, however, features a 2A current limit on the
internal 3.3V LDO while the ISL6506 has a 1A current limit.
The ISL6506A has a 1A current limit on the internal 3.3V
LDO.
and 3.3V
DUAL
plane by switching in
DUAL
through a PMOS (or
SB
DUAL
rails into
output is shut down. In the
FN9141.3
Features
• Provides 2 ACPI-Controlled Voltages
-5V
-3.3V
• Excellent 3.3V
USB/Keyboard/Mouse
DUAL
/3.3VSB PCI/Auxiliary/LAN
DUAL
Regulation in S3/S4/S5
DUAL
- ±2.0% Over-Temperature
- 1A Capability on ISL6506 and ISL6506A
- 2A Capability on ISL6506B
• Small Size; Very Low External Component Count
• Over-Temperature Shutdown
• Pb-Free Available (RoHS Compliant)
Applications
•
ACPI-Compliant Power Regulation for Motherboards
- ISL6506, ISL6506B: 5V
is shut down in S4/S5
DUAL
sleep states
- ISL6506A: 5V
stays on in S4/S5 sleep states
DUAL
Pinout
ISL6506
(8 LD EPSOIC)
TOP VIEW
VCC
3V3AUX
S3
S5
1
2
GND
3
4
8
7
6
5
N/C
5VDLSB
DLA
GND
Ordering Information
PART NUMBER PART MARKING
ISL6506CB* ISL 6506CB 0 to +70 8 Ld EPSOIC M8.15C
ISL6506CBZ* (Note) 6506 CBZ 0 to +70 8 Ld EPSOIC (Pb-free) M8.15C
ISL6506ACB* 6506 ACB 0 to +70 8 Ld EPSOIC M8.15C
ISL6506ACBZ *(Note) 6506 ACBZ 0 to +70 8 Ld EPSOIC (Pb-free) M8.15C
ISL6506BCB* 6506 BCB 0 to +70 8 Ld EPSOIC M8.15C
ISL6506BCBZ* (Note) 6506 BCBZ 0 to +70 8 Ld EPSOIC (Pb-free) M8.15C
ISL6506BCBZA* (Note) 6506 BCBZ 0 to +70 8 Ld EPSOIC (Pb-free) M8.15C
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
TEMP.
RANGE (°C) PACKAGE
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005, 2007, 2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
PKG.
DWG. #
Block Diagram
www.BDTIC.com/Intersil
ISL6506, ISL6506A, ISL6506B
5VDLSB
GND
DLA
3.5Ω
7.5µA
12V POR
SENSE
SOFT-START
VCC
MONITOR
AND
CONTROL
UV DETECTOR
S3
10µA
DIGITAL
()
SOFT-START
S5
10µA
TEMPERATURE
MONITOR
EA1
+
-
VCC
3V3AUX
Typical Application
5VSBY
SLP_S3
SLP_S5
1
2
3
4
ISL6506
VCC
3V3AUX
S3
S5
9
EPAD
NC
5VDLSB
DLA
GND
12VATX 5VSBY 5VATX3V3ATX
1kΩ
8
7
6
5
Q1
Cg
(OPTIONAL)
Q2
5VDUAL
Q3
3V3DUAL
2
FN9141.3
May 7, 2008
ISL6506, ISL6506A, ISL6506B
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
Supply Voltage, V
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4000V
Recommended Operating Conditions
Supply Voltage, V
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
1. θ
JA
2. For θ
3. Limits should be considered typical and are not production tested.
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
VCC SUPPLY CURRENT
Nominal Supply Current I
POWER-ON RESET
Rising 5VSB POR Threshold --4.5V
Falling 5VSB POR Threshold 3.60 - 3.95 V
Rising 12V POR Threshold 1.00kΩ resistor between DLA and 12V Rail 8.9 9.8 10.8 V
3.3V
Regulation V
3V3SB Nominal Voltage Level V
3V3SB Undervoltage Threshold V
3V3SB Overcurrent Trip I
5V
5VDLSB Output Drive Current I
TIMING INTERVAL
S0 to S3 Transition Delay -58- µs
SOFT-START
Soft-start Interval t
5VDLSB Soft-start Current Source --7.5- µA
CONTROL I/O (S3
High Level Input Threshold --2.2V
Low Level Input Threshold 0.8 - - V
S3
TEMPERATURE MONITOR
Shutdown-Level Threshold (Note 3) - 140 - °C
LINEAR REGULATOR
AUX
SWITCH CONTROLLER
DUAL
, S5 Internal Pull-down Current to GND - 10 - µA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V
Sx
unless otherwise specified. Temperature limits established by characterization and are not production tested.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
5VSB
3V3SB
3V3SB_UV
3V3SB_TRIP
5VDLSBV5VDLSB
SS
, S5)
VS3 = 5V, VS5 = 5V (S0 State) - 3.60 - mA
= 0V, VS5 = 5V (S3 State) - 4.60 - mA
V
S3
= 0V (S5 State) - 4.60 - mA
V
S5
5VSBY
ISL6506, ISL6506A (Note 3) - - 1 A
ISL6506B (Note 3) - - 2 A
Thermal Resistance (Typical)
EPSOIC Package (Notes 1, 2) . . . . . . 40 3.5
Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
= 5.0V, I
= 4V, V
= 0A - - 2.0 %
3V3SB
= 5V 20 - 35 mA
5VSB
6.55 8.2 9.85 ms
θ
(°C/W) θJC (°C/W)
JA
-3.3- V
- 2.475 - V
3
FN9141.3
May 7, 2008
ISL6506, ISL6506A, ISL6506B
www.BDTIC.com/Intersil
Functional Pin Description
VCC (Pin 1)
Provide a very well decoupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5V
provides all the bias for the IC as well as the input voltage for
the internal standby 3V3AUX LDO. The voltage at this pin is
monitored for power-on reset (POR) purposes.
GND (Pin 5, Pad)
Signal ground for the IC. These pins are also the ground
return for the internal 3V3AUX LDO that is active in
S3/S4/S5 sleep states. All voltage levels are measured with
respect to these pins.
S3 and S5 (Pins 3 and 4)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 10µA pull-down current sources on
each pin. Additional circuitry blocks illegal state transitions,
such as S4/S5 to S3. Connect S3
system’s SLP_S3
and SLP_S5 signals, respectively.
3V3AUX (Pin 2)
Connect this pin to the 3V3DUAL output. In sleep states, the
voltage at this pin is regulated to 3.3V through an internal
pass device powered from 5VSBY through the VCC pin. In
active states, ATX 3.3V output is delivered to this node
through a fully-on NMOS transistor. During S3 and S4/S5
states, this pin is monitored for undervoltage events.
DLA (Pin 6)
This pin is an open-drain output. A 1kΩ resistor must be
connected from this pin to the ATX 12V output. This resistor
is used to pull the gates of suitable N-MOSFETs to 12V,
which in active state, switch in the ATX 3.3V and 5V outputs
into the 3.3V
AUX
and 5V
outputs, respectively. This pin
DUAL
is also used to monitor the 12V rail during POR. If a resistor
other than 1kΩ is used, the POR level will be affected.
5VDLSB (Pin 7)
Connect this pin to the gate of a suitable P-MOSFET.
ISL6506 and ISL6506B: In S3 sleep state, this transistor is
switched on, connecting the ATX 5V
regulator output.
ISL6506A: In S3 and S4/S5 sleep state, this transistor is
switched on, connecting the ATX 5V
regulator output.
output. This pin
SB
and S5 to the computer
output to the 5V
SB
output to the 5V
SB
DUAL
DUAL
controller/regulator supplying the computer system’s
3.3V
5V
power, a dual switch controller supplying the
DUAL
voltage, as well as all the control and monitoring
DUAL
functions necessary for complete ACPI implementation.
Initialization
The ISL6506 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5V
input supply voltage. The ISL6506 also
SB
monitors the 12V rail to insure that the ATX rails are up
before entering into the S0 state ev en if both SLP_S3
SLP_S5
are both high.
and
Dual Outputs Operational Truth Table
Table 1 describes the truth combinations pertaining to the
3.3V
DUAL
and 5V
outputs. The internal circuitry does
DUAL
not allow the transition from an S4/S5 state to an S3 state.
TABLE 1. 5V
S5
S3 3.3AUX 5VDL COMMENTS
1 1 3.3V 5V S0/S1/S2 States (Active)
1 0 3.3V 5V S3
0 1 Note Maintains Previous State
0 0 3.3V 0V S4/S5 (ISL6506 and
0 0 3.3V 5V S4/S5 (ISL6506A)
NOTE: Combination Not Allowed.
OUTPUT TRUTH TABLE
DUAL
ISL6506B)
Functional Timing Diagrams
Figures 1 (ISL6506, ISL6506B) and 2 (ISL6506A) are simplified
timing diagrams, detailing the power-up/down sequences of all
the outputs in response to the status of the sleep-state pins (S3
S5
), as well as the status of the input ATX supply . Not shown in
these diagrams is the deglitching feature used to protect
against false sleep state tripping. Additionally, the ISL6506
features a 60µs delay in transitioning from S0 to S3 states. The
transition from the S0 state to S4/S5 state is immediate.
5VSB
S3
S5
3.3V, 5V, 12V
DLA
,
Description
Operation
The ISL6506 controls 2 output voltages, 3.3V
5V
applications requiring 3.3V, 5V, 5V
. It is designed for microprocessor computer
DUAL
, and 12V bias input
SB
DUAL
and
3V3AUX
5VDLSB
5VDL
FIGURE 1. 5V
from an ATX power supply. The IC is composed of one linear
4
AND 3.3V
DUAL
ISL6506 AND ISL6506B
AUX
TIMING DIAGRAM;
FN9141.3
May 7, 2008
ISL6506, ISL6506A, ISL6506B
www.BDTIC.com/Intersil
5VSB
S3
S5
3.3V, 5V, 12V
DLA
3V3DL
5VDLSB
5VDL
FIGURE 2. 5V
DUAL
ISL6506A
AND 3.3V
TIMING DIAGRAM;
AUX
Soft-Start
Figures 3 and 4 show the soft-start sequence for the typical
application start-up into a sleep state. At time t0, 5V
is applied to the circuit. At time t1, the 5V
surpasses POR
SB
level. Time t2, one soft-start interval after t1, denotes the
initiation of soft-start. The 3.3V
rail is brought up
DUAL
through the internal standby LDO through an internal digital
soft-start function. Figure 4 shows the 5V
rail initiating a
DUAL
soft-start at time t2 as well. The ISL6506A will draw 7.5µA
into the 5VDLSB for a duration of one soft-start period. This
current will enhance the P-MOSFET (Q
, refer to “Typical
2
Application” on page 2) in a controlled manner. At time t3,
the 3.3V
down to ground. If the 5V
of the 5V
is in regulation and the 5VDLSB pin is pulled
DUAL
rail by time t3, then the rail will experience a
SB
rail has not reached the level
DUAL
sudden step as the P-MOSFET gate is fully enhanced. The
soft-start profile of the 5V
may be altered by placing a
DUAL
capacitor between the gate and drain of the P-MOSFET.
Adding this capacitor will increase the gate capacitance and
slow down the start of the 5V
DUAL
rail.
At time t4, the system has transitioned into S0 state and the
A TX supplies have begu n to ramp-up. With the ISL65 06,
ISL6506B (Figure 3), the 5V
from the 5V
(Q
). The ISL6506A will already have the 5V
3
rail through the body diode of the N-MOSFET
ATX
regulation (Figure 4). At time t5, the 12V
rail will begin to ramp-up
DUAL
DUAL
rail has
ATX
surpassed the 12V POR level. Time t6 is three so f t-st art
cycles after the 12V POR level has been surpassed. At time
t6, three events occur simultaneously. The DLA pin is forced
to a high impedance state which allows the 12V rail to
enhance the two N-MOSFETs (Q
A TX rails to the 3.3V
DUAL
and 5V
and Q3) that connect the
1
rails. The 5VDLSB pin
DUAL
is actively pulled high, which will turn the P-MOSFET (Q
Finally , the internal LDO which regulates the 3.3V
sleep states is put in standby mode.
SB
rail in
AUX
(bias)
) off.
2
rail in
5VSB
(1V/DIV)
0V
t1 t2 t3t0 t5t4 t6
FIGURE 3. ISL6506 AND ISL6506B SOFT-ST ART INTERVAL
5VSB
(1V/DIV)
0V
5VDLSB
(5V/DIV)
t1 t2 t3t0 t5t4 t6
FIGURE 4. SOFT-ST ART INTERVAL FOR ISL6506A IN S4/S5
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
3.3VDUAL
(2V/DIV)
5VDUAL
(1V/DIV)
DLA
(10V/DIV)
TIME
IN S4/S5 STATE AND S5 TO S0 TRANSITION
5VDUAL
(1V/DIV)
3.3VDUAL
(2V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
DLA
(10V/DIV)
TIME
AND S5 TO S0 TRANSITION FOR ISL6506A AND
S3 TO S0 TRANSITION FOR ISL6506, ISL6506A,
ISL650B
Sleep to Wake State Transitions
Figures 3 and 4, starting at time t4, depict the transitions
from sleep states to the S0 wake state. Figure 3 shows the
transition of the ISL6506, ISL6506B from the S4/S5 state to
the S0 state. Figure 4 shows how the ISL6506, ISL6506B
will transition from the S3 sleep state into S0 state. Figure 3
also shows how the ISL6506A transitions from either S3 or
S4/S5 in the S0 state. For all transitions, t4 depicts the
system transition into the S0 state. Here, the ATX supplies
are enabled and begin to ramp up. At time t5, the 12V
has exceeded the POR threshold for the ISL6506, ISL6506B
and ISL6506A. Three soft-start periods after time t5, at time
t6, three events occur simultaneously. The DLA pin is forced
ATX
rail
5
FN9141.3
May 7, 2008
ISL6506, ISL6506A, ISL6506B
www.BDTIC.com/Intersil
to a high impedance state, which allows the 12V rail to
enhance the two N-MOSFETs (Q
ATX rails to the 3.3V
DUAL
and 5V
pin is actively pulled high, which will turn the P-MOSFET
(Q
) off. Finally, the internal LDO which regulates the
2
3.3V
rail in sleep states is put in standby mode.
DUAL
Internal Linear Regulator Undervoltage Protection
The undervoltage protection on the internal linear regulator
is only active during sleep states and after the initial soft-start
ramp of the 3.3V linear regulator. The undervoltage trip point
is set at 25% below nominal, or 2.475V.
When an undervoltage is detected, the 3.3V linear regulator
is disabled. One soft-start interval later, the 3.3V linear
regulator is retried with a soft-start ramp. If the linear
regulator is retried 3 times and a fourth undervoltage is
detected, then the 3.3V linear regulator is disabled and can
only be reset through a POR reset.
and Q3) that connect the
1
rails. The 5VDLSB
DUAL
12VATX
+3.3VIN
Q2
LOAD
C
3V3DUAL
C
HF3V
5VSB
5VSB
CIN
5VDUAL
C
Q3
HF5V
LOAD
Q4
5VATX
VCC
5VDLSB
C
ISL6506,
ISL6506A,
ISL6506B
3V3AUX
C
3V
GND
EPAD
5V
DLA
Internal Linear Regulator Overcurrent Protection
When an overcurrent condition is detected, the gate voltage
to the internal NMOS pass element is reduced, which
causes the output voltage of the linear regulator to be
reduced. When the output voltage is reduced to the
undervoltage trip point, the undervoltage protection is
initiated and the output will shutdown.
Layout Considerations
The typical application employing an ISL6506 is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, not excessively far
from the 3.3V
3V3AUX connection is properly sized to carry 1A without
exhibiting significant resistive losses at the load end.
Similarly, the input bias supply (5V
of current (for best results, ensure it is connected to its
respective source through an adequately sized trace and is
properly decoupled). The pass transistors should be placed
on pads capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
Placement of the decoupling and bulk capacitors should
reflect their purpose. As such, the high-frequency
decoupling capacitors should be placed as close as possible
to the load they are decoupling; the ones decoupling the
controller close to the controller pins, the ones decoupling
the load close to the load connector or the load itself (if
embedded). Even though bulk capacitance (aluminum
electrolytics or tantalum capacitors) placement is not as
island or the I/O circuitry. Ensure the
DUAL
) carries a similar level
SB
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 5. PRINTED CIRCUIT BOARD ISLANDS
critical as the high-frequency capacitor placement, having
these capacitors close to the load they serve is preferable.
Locate all small signal components close to the respective
pins of the control IC, and connect them to ground, if
applicable, through a via placed close to the ground pad.
A multi-layer printed circuit board is recommended.
Figure 5 shows the connections to most of the components
in the circuit. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. The EPAD should be
tied to the ground plane with three to five vias for good
thermal management. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Ideally, the power plane should
support both the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers to
create power islands connecting the filtering components
(output capacitors) and the loads. Use the remaining printed
circuit layers for small signal wiring.
Component Selection Guidelines
Output Capacitors Selection
The output capacitors should be selected to allow the output
voltage to meet the dynamic regulation requirements of
active state operation (S0/S1). The load transient for the
various microprocessor system’s components may require
high quality capacitors to supply the high slew rate (di/dt)
6
FN9141.3
May 7, 2008
ISL6506, ISL6506A, ISL6506B
www.BDTIC.com/Intersil
current demands. Thus, it is recommended that the output
capacitors be selected for transient load regulation, paying
attention to their parasitic components (ESR, ESL).
Also, during the transition between active and sleep states
on the 5V
output, there is a short interval of time during
DUAL
which none of the power pass elements are conducting.
During this time the output capacitors have to supply all the
output current. The output voltage drop during this brief
period of time can be easily approximated using Equation 1:
V
Δ I
OUT
⎛⎞
ESR
×=
⎜⎟
OUT
OUT
⎝⎠
----------------
+
C
t
t
OUT
(EQ. 1)
where:
ΔV
= output voltage drop
OUT
ESR
I
OUT
C
= output capacitor bank ESR
OUT
= output current during transition
= output capacitor bank capacitance
OUT
tt = active-to-sleep/sleep-to-active transition time (10µs
typical)
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
Q1, Q3
These N-Channel MOSFETs are used to switch the 3.3V and
5V inputs provided by the ATX supply into the 3.3V
5V
outputs while in active (S0, S1) state. The main
DUAL
AUX
and
criteria for the selection of these transistors is output voltage
budgeting. The maximum r
allowed at highest junction
DS(ON)
temperature can be expressed using Equation 3:
r
DS ON()max
INminVOUTmin
---------------------------------------------------
=
I
OUTmax
(EQ. 3)
V
–
where:
V
= minimum input voltage
INmin
V
OUTmin
I
OUTmax
= minimum output voltage allowed
= maximum output current
Q2
This is a P-Channel MOSFET used to switch the 5VSB
output of the ATX supply into the 5V
sleep states. The selection criteria of this device, as with the
N-Channel MOSFETs, is proper voltage budgeting. The
maximum r
, however, has to be achieved with only
DS(ON)
4.5V of gate-to-source voltage, so a true logic level
MOSFET needs to be selected.
output during
DUAL
Input Capacitors Selection
The input capacitors for an ISL6506, ISL6506A application
must have a sufficiently low ESR so as not to allow the input
voltage to dip excessively when energy is transferred to the
output capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the ISL6506, ISL6506A’ s regulation levels could
have as a result a brisk transfer of energy from the input
capacitors to the supplied outputs. At the transition between
active and sleep states, such phenomena could be
responsible for the 5V
voltage drooping excessively and
SB
affecting the output regulation. The solution to such a
potential problem is using larger input capacitors with a
lower total combined ESR.
Transistor Selection/Considerations
The ISL6506, ISL6506A usually requires one P-Channel and
two N-Channel MOSFETs. All three of these MOSFETs are
utilized as ON/OFF switching elements.
One important criteria for selection of transistors for all the
switching elements is package selection for efficient removal
of heat. The power dissipated in a switch element while on is
shown in Equation 2:
P
LOSS
2
I
×=
o
r
DS ON()
(EQ. 2)
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
7
FN9141.3
May 7, 2008
ISL6506, ISL6506A, ISL6506B
www.BDTIC.com/Intersil
Small Outline Exposed Pad Plastic Packages (EPSOIC)
N
INDEX
AREA
123
TOP VIEW
-AD
e
B
0.25(0.010) C AM BS
SIDE VIEW
123
N
P
BOTTOM VIEW
H
E
-B-
SEATING PLANE
A
-C-
A1
M
P1
0.25(0.010) BM M
L
h x 45°
α
0.10(0.004)
M8.15C
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.056 0.066 1.43 1.68 -
A1 0.001 0.005 0.03 0.13 -
B 0.0138 0.0192 0.35 0.49 9
C 0.0075 0.0098 0.19 0.25 D 0.189 0.196 4.80 4.98 3
E 0.150 0.157 3.811 3.99 4
e 0.050 BSC 1.27 BSC -
H 0.230 0.244 5.84 6.20 -
h 0.010 0.016 0.25 0.41 5
L 0.016 0.035 0.41 0.89 6
C
N8 87
α
P - 0.126 - 3.200 11
P1 - 0.099 - 2.514 11
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
0° 8° 0° 8° -
NOTESMIN MAX MIN MAX
Rev. 1 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN9141.3
May 7, 2008
Loading...