intersil ISL6505 DATA SHEET

®

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ISL6505

Data Sheet December 1, 2005

Multiple Linear Power Controller with
ACPI Control Interface

The ISL6505 complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
integrates three linear controllers/regulators, switching,
monitoring and control functions into a 20-pin wide-body
SOIC or 20-pin QFN (also known as MLF) 5x5 package.
The ISL6505’s operating mode (active or sleep outputs) is
selectable through two digital control pins, S3

One linear controller generates the 3.3V
voltage plane from the ATX supply’s 5V
the south bridge and the PCI slots through an external NPN
pass transistor during sleep states (S3, S4/S5). In active
state (during S0 and S1/S2), the 3.3V

DUAL

regulator uses an external N-channel pass MOSFET to
connect the outputs directly to the 3.3V input supplied by an
ATX power supply, f or minimal losses. Th e 3 .3 V
output is active for as long as the ATX 5V
to the chip.

A controller powers up the 5V

plane by switching in the

DUAL

ATX 5V output through an NMOS transistor in active states,
or by switching in the ATX 5V

through a PMOS (or PNP)

SB

transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6505 5V

output is either shut down or stays on,

DUAL

based on the state of the EN5 pin.
An internal linear regulator supplies the 1.2V for the voltage

identification circuitry (VID) only during active states (S0 and
S1/S2), and uses the 3V3 pin as input source for its internal
pass element.

A linear controller generates V

3.3V

/3.3VSB voltage plane, using an external NFET.

DUAL

OUT1

from the

The voltage is user-programmable to values between 1.2V
and 1.5V, using an external resistor divider. The mode is
user-selectable with the LAN pin; a logic high (or open)
selects the 10/100 LAN mode, wh er e V
(S0-S5); a logic low selects the Gigabit Ethernet mode,
where V

is only on during active modes (S0-S2).

OUT1

and S5.
/3.3VSB

DUAL

output, powering

SB

/3.3VSB linear

/3.3VSB

DUAL

voltage is applied

SB

is always on

OUT1

FN9109.3

Features

• Provides four ACPI-Controlled Voltages

-5V

-3.3V

-1.2V

-V

USB/Keyboard/Mouse

DUAL

/3.3VSB PCI/Auxiliary/LAN

DUAL

Processor VID Circuitry

VID

(1.2V - 1.5V programmable) LAN/Ethernet

OUT1

• Excellent Output Voltage Regulation

- All Outputs: ±2.0% over temperature (as applicable)

• Small Size; Very Low External Component Count

• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown

• QFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

•

ACPI-Compliant Power Regulation for Motherboards

Ordering Information

PART NUMBER

ISL6505CB* 0 to 70 20 Ld Wide SOIC M20.3
ISL6505CR* 0 to 70 20 Ld 5x5 QFN L20.5x5
ISL6505CRZ*

(Note 1)
ISL6505EVAL1 Evaluation Board (SOIC)
ISL6505EVAL2 Evaluation Board (QFN)

Add “-T” suffix for tape and reel.

NOTE:

1. Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.

TEMP.

RANGE (°C) PACKAGE

0 to 70 20 Ld 5x5 QFN

(Pb-free)

PKG.

DWG. #

L20.5x5

Pinouts - See page 6.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved

Block Diagram

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3V3DLSB

EA4

3V3

3V3DL

­+

5V

5VSB

5VSB POR

DLA

5VDLSB

2

5V MONITOR

4.5V/4.25V

EA3

DR1

FB1

+

­TO UV

DETECTOR

4.4V/3.4V

3V3 MONITOR

2.75V/2.60V

TEMPERATURE

MONITOR

(TMON)

ISL6505

MONITOR AND CONTROL

TO 3V3

EA3

+

FAULT

UV DETECTOR

UV COMP

4.10V

TO

UV DETECTOR

10µA

+

-

+

-

+

0.80V

-

-

1V2VID

+

-

10mA

VID_PG

5VDL

GND

SS

S3

S5

EN5

FIGURE 1.

LAN

VID_CT

Simplified Power System Diagram

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+5V

IN

+12V

IN

+5V

SB

+3.3V

IN

ISL6505

FAULT

Q2

3.3V

SHUTDOWN

SX, EN5, LAN

DUAL

V

/3.3V

OUT1

SB

3.3V

4

Typical Application

+5V

IN

+12V

IN

+5V

SB

+3.3V

IN

V

OUT1

1.2V - 1.5V

Q2

C

OUT1

Q3

R21

Q6

R20

R

DLA

Q6

R20

R21

3V3DLSB

ISL6505

LINEAR

CONTROLLER

LINEAR

CONTROLLER

FIGURE 2.

DR1

FB1

3V3

REGULATOR

5V

LINEAR

CONTROL

LOGIC

5VSB

1V2VID

VID_CT

C

CT_VID

1.2V

VID

1.2V

VID_PG

C

OUT2

Q5

Q4

V

OUT2

1.2V

5V

DUAL

5V

VID

VID_PG

5VDLSB

DLA

5VDL

3.3V

FAULT

SLP_S3

SLP_S5

SHUTDOWN

V

DUAL

OUT3

/3.3V

SB

C

OUT3

Q3

EN5

LAN

3V3DL

EN5

LAN

FAULT

C

SS

ISL6505

S3

S5

SS

GND

FIGURE 3.

3

C

OUT4

Q5

VID PGOOD

Q4

V

5V

OUT4

DUAL

ISL6505

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Absolute Maximum Ratings Thermal Information

Supply Voltage, V

DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V

All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V

ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . .2kV

Recommended Operating Conditions

Supply Voltage, V

Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V

Digital Inputs, V

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0

Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

3. θ

JA

Tech Brief TB379.

4. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3

VCC SUPPLY CURRENT

Nominal Supply Current I
Shutdown Supply Current I

POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS

5VSB Rising POR Threshold 4.0 4.3 4.5 V
5VSB Falling POR Threshold 3.15 3.4 3.55 V
5VSB POR Hysteresis -0.9- V
3V3 Rising Threshold 2.8 2.93 3.0 V
3V3 Falling Threshold 2.65 2.78 2.9 V
3V3 Hysteresis - 150 - mV
5V Rising Threshold 4.25 4.4 4.5 V
5V Falling Threshold 4.0 4.15 4.3 V
5V Hysteresis - 250 - mV
VID_PG Rising Threshold -1.04- V
VID_PG Hysteresis -50- mV
VID_CT Charging Current I
Soft-Start Current I
Soft-Start Shutdown Voltage Threshold V

LINEAR REGULATOR (V

Regulation V

V

OUT1

Nominal Voltage Level V

V

OUT1

Undervoltage Rising Threshold FB1 pin - 1.2 - V

V

OUT1

Undervoltage Hysteresis FB1 pin - 50 - mV

V

OUT1

DR1 Output Drive Current I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

5VSB

. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

5VSB

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V

Sx

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

; DR1 and FB1 pins)

OUT1

o

C to 70oC

o

C to 125oC

5VSB

5VSB(OFF)VSS

VID_CT

SS

SD

OUT1

DR1

V

VID_CT

OUT1

Based on external resistors - 1.5 - V

V

3V3DL

= 0.8V - 4 - mA

= 1.2V to 1.5V - - 2.0 %

= 3.3V - 10 - mA

Thermal Resistance (Typical)

SOIC Package (Note 2). . . . . . . . . . . . 65 N/A

QFN Package (Notes 3, 4) . . . . . . . . . 35 5

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

= 0V - 10 - µA

θ

(oC/W) θJC (oC/W)

JA

o

C to 150oC

-6- mA

-10- µA

--0.8V

o

C

o

C

4

ISL6505

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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

1.2V

LINEAR REGULATOR (V

VID

1V2VID Regulation --2.0%
1V2VID Nominal Voltage Level V
1V2VID Undervoltage Rising Threshold -0.92- V
1V2VID Undervoltage Hysteresis - 100 - mV
1V2VID Output Current I

3.3V

3V3DL Sleep State Regulation --2.0%
3V3DL Nominal Voltage Level V
3V3DL Undervoltage Rising Threshold -2.62- V
3V3DL Undervoltage Hysteresis - 150 - mV
3V3DLSB Output Drive Current I

5V

5VDL Undervoltage Rising Threshold -4.10- V
5VDL Undervoltage Hysteresis - 120 - mV
5VDLSB Output Drive Current I

TIMING INTERVALS

Active State Assessment Past Input UV
Thresholds (Note 5)

Active-to-Sleep Control Input Delay - 200 - µs
Falling UV Threshold Timeout (All Monitors) - 10 - µs

CONTROL I/O (S3

High Level Input Threshold S3, S5, EN5, LAN - - 2.2 V
Low Level Input Threshold S3
Internal Pull-up Current to 5VSB S3
Internal Pull-up Current to 5VSB EN5, LAN to GND - 10 - µA
Input Leakage Current to 5VSB EN5, LAN to 5VSB - - 10 mA
FAULT Current IOH (to 5VSB) FAULT = 4.6V, 5VSB = 5V - -7.5 - mA
FAULT Current IOL (to GND) FAULT = 0.4V, 5VSB = 5V - 0.75 - mA

TEMPERATURE MONITOR

Fault-Level Threshold (Note 6) 125 - ­Shutdown-Level Threshold (Note 6) - 155 -

NOTES:

5. Guaranteed by Correlation.

6. Guaranteed by Design.

/3.3VSB LINEAR REGULATOR (V

DUAL

SWITCH CONTROLLER (V

DUAL

, S5, EN5, LAN, FAULT)

OUT2

OUT4

)

OUT3

3V3DLSBV5VSB

)

1V2VID

V

1V2VID

)

3V3DL

5VDLSBV5VDLSB

= 3.3V - - 180 mA

3V3

= 5V 30 50 - mA

, S5, EN5, LAN 0.8 - - V
, S5 to GND - 50 - µA

= 4V, V

-1.2- V

-3.3- V

= 5V -20 - -40 mA

5VSB

42 53 64 ms

o

C

o

C

5

Pinouts

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ISL6505 (20 LEAD WIDE SOIC)

TOP VIEW

ISL6505

ISL6505 (5X5 QFN)

TOP VIEW

FB1

DR1

3V3DLSB

3V3DL

1V2VID

3V3

5V

EN5

S3
S5

1
2
3
4
5
6
7
8
9

10

20

19
18
17
16
15
14
13
12

11

5VSB
VID_CT
VID_PG
SS
LAN
5VDL
5VDLSB
DLA
FAULT
GND

3V3DL

1V2VID

3V3

5V

EN5

NOTE: The QFN bottom pad is electrically connected to the IC
substrate, at GND potential. It can be left unconnected, or connected
to GND; do NOT connect to another potential.

Functional Pin Description (Pin numbers for SOIC and QFN)

3V3 (Pin 6 SOIC; Pin 3 QFN)

Connect this pin to the ATX 3.3V output. This pin provides
the output current for the 1V2VID pin, and is monitored for
power quality.

5V (Pin 7 SOIC; Pin 4 QFN)

Connect this pin to the ATX 5V output. This pin is only
monitored for power quality.

5VSB (Pin 20 SOIC; Pin 17 QFN)

Provide a very well de-coupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5V

output. This pin

SB

provides all the chip’s bias as well as the base current for Q2
(see typical application diagram). The voltage at this pin is
monitored for power-on reset (POR) purposes.

GND (Pin 11 SOIC; Pin 8 QFN)

Signal ground for the IC. All voltage le vels are measured with
respect to this pin.

S3 and S5 (Pins 9, 10 SOIC; Pins 6, 7 QFN)

These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 50µA (typical) current source pull­ups to 5VSB. Internal circuitry de-glitches these pins for
disturbances lasting as long as 2µs (typically). Additional
circuitry blocks illegal state transitions (such as S4/S5 to S3),
but does allow S3 to S4/S5. Connect S3
respectively to the computer system’s SLP_S3
signals.

and S5

and SLP_S5

EN5 (Pin 8 SOIC; Pin 5 QFN)

This digital input selects whether the 5VDL output stays up
or shuts down during the S5 Sleep Mode. It has a 10µA
typical pull-up current source. A logic high (5V) or open will
keep the 5VDL on during S5; a logic low (GND) will shut it off
during S5. NOTE: This pin should be tied low or high (or
open) on the board; it was not designed to be changed
during normal operation.

LAN (Pin 16 SOIC; Pin 13 QFN)

This digital input selects between two modes for the V
regulator. It has a 10µA pull-up current source. A logic high
(5V) or open selects the 10/100 LAN mode, where V
stays on all of the time (active and sleep modes). A logic low
(GND) selects the Gigabit Ethernet mode, where V
only on during active (S0, S1) modes. Note that this
selection is independent of the voltage selection of V
(which is determined by the external resistor divider). NOTE:
This pin should be tied low or high (or open) on the board; it
was not designed to be changed during normal operation.

FAULT (Pin 12 SOIC; Pin 9 QFN)

This digital output pin is used to report the fault condition by
being pulled to 5VSB (pulled to GND if no fault). It is a
CMOS digital output; an external pull-down resistor is NOT
required. In case of an undervoltage on any of the controlled
outputs, on any of the monitored ATX voltages (3V3 or 5V;
not 12V), or in case of an overtemperature event, t his pi n is
used to report the fault condition.

3V3DLSB

DR1

FB1

20 19 18 17 16

1

2

3

4

5

678910

S3

S5

GND

5VSB

VID_CT

VID_PG

15

14

SS

13

LAN

5VDL

12

5VDLSB

11

DLA

FAULT

OUT1

OUT1

is

OUT1

OUT1

6