intersil ISL6504, ISL6504A DATA SHEET

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ISL6504, ISL6504A

Data Sheet April 13, 2004

Multiple Linear Power Controller with ACPI Control Interface

The ISL6504 and ISL6504A complement other power building blocks (voltage regulators) in ACPI-compliant designs for microprocessor and computer applications. The IC integrates three linear controllers/regulators, switching, monitoring and control functions into a 16-pin wide-body SOIC or 20-pin QFN 6x6 package. The ISL6504, ISL6504A operating mode (active outputs or sleep outputs) is selectable through two digital control pins, S3

One linear controller generates the 3.3V voltage plane from the ATX supply’s 5V the south bridge and the PCI slots through an external NPN pass transistor during sleep states (S3, S4/S5). In active state (during S0 and S1/S2), the 3.3V regulator uses an external N-channel pass MOSFET to connect the outputs directly to the 3.3V input supplied by an ATX power supply, for minimal losses.

A controller powers up the 5V ATX 5V output through an NMOS transistor in active states, or by switching in the ATX 5V transistor in S3 sleep state. In S4/S5 sleep states, the ISL6504 5V 5V the only difference between the two parts; see Table 1.

output stays on during S4/S5 sleep states. This is

DUAL

output is shut down. In the ISL6504A, the

DUAL

plane by switching in the

through a PMOS (or PNP)

and S5. /3.3VSB

DUAL

output, powering

/3.3VSB linear

FN9062.2

Features

• Provides four ACPI-Controlled Voltages

-5V

-3.3V

-1.2V

-1.5VSB ICH4 Resume Well

• Excellent Output Voltage Regulation

- All Outputs: ±2.0% over temperature (as applicable)

• Small Size; Very Low External Component Count

• Undervoltage Monitoring of All Outputs with Centralized FAULT Reporting and Temperature Shutdown

• QFN Package:

- Near Chip Scale Package Footprint; Improved PCB

Efficiency; Thinner profile

• Pb-Free Available (RoHS Compliant)

USB/Keyboard/Mouse

DUAL

/3.3VSB PCI/Auxiliary/LAN

DUAL

Processor VID Circuitry

VID

Applications

•

ACPI-Compliant Power Regulation for Motherboards

- ISL6504: 5V

- ISL6504A: 5V

is shut down in S4/S5 sleep states

DUAL

stays on in S4/S5 sleep states

DUAL

An internal linear regulator supplies the 1.2V for the voltage identification circuitry (VID) only during active states (S0 and S1/S2), and uses the 3V3 pin as input source for its internal pass element. Another internal regulator outputs a 1.5V chip-set standby supply, which uses the 3V3DL pin as input source for its internal pass element. The 3.3V and 1.5V voltage is applied to the chip.

outputs are active for as long as the ATX 5VSB

DUAL

/3.3VSB

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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All other trademarks mentioned are the property of their respective owners.

ISL6504, ISL6504A

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Pinouts

ISL6504/A (WIDE BODY SOIC)

TOP VIEW

1V5SB

3V3DL

3V3

GND

3V3DLSB

1V2VID

NOTE: SOIC layout should accomodate both wide and narrow footprints.

ISL6504/A (6

X6 QFN)

5VSB

VID_CT

VID_PG

5VDL

5VDLSB

DLA

FAULT

TOP VIEW

3V3DLSB

20 19 18 17 16

3V3DL

1V2VID

NOTE: The QFN bottom pad is electrically connected to the IC substrate, at GND potential. It can be left unconnected, or connected to GND; do NOT connect to another potential.

3V3

678910

1V5SB

GND

5VSB

FAULT

VID_CT

VID_PG

5VDL

5VDLSB

DLA

Ordering Information

TEMP.

PART NUMBER

RANGE (oC) PACKAGE

ISL6504CB 0 to 70 16 Ld SOIC M16.3 ISL6504CBZ

(Note)

0 to 70 16 Ld SOIC

(Pb-free) ISL6504CBN 0 to 70 16 Ld SOIC M16.15 ISL6504CBNZ

(Note)

0 to 70 16 Ld SOIC

(Pb-free) ISL6504CR 0 to 70 20 Ld 6x6 QFN L20.6x6 ISL6504CRZ

(Note)

0 to 70 20 Ld 6x6 QFN

(Pb-free) ISL6504EVAL1 Evaluation Board ISL6504ACB 0 to 70 16 Ld SOIC M16.3 ISL6504ACBZ

(Note)

0 to 70 16 Ld SOIC

(Pb-free) ISL6504ACBN 0 to 70 16 Ld SOIC M16.15 ISL6504ACBNZ

(Note)

0 to 70 16 Ld SOIC

(Pb-free) ISL6504ACR 0 to 70 20 Ld 6x6 QFN L20.6x6 ISL6504ACRZ

(Note)

0 to 70 20 Ld 6x6 QFN

(Pb-free) ISL6504AEVAL1 Evaluation Board Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PKG.

DWG. #

M16.3

M16.15

L20.6x6

M16.3

M16.15

L20.6x6

FN9062.2

April 13, 2004

Block Diagram

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3V3DLSB

EA4

3V3DL

3V3

5VSB POR

4.4V/3.4V

5VSB

DLA

5VDLSB

1V5SB

FAULT

EA3

UV DETECTOR

TO UV

DETECTOR

10mA

3V3 MONITOR

MONITOR AND CONTROL

1.265V

2.75V/2.60V

UV DETECTOR

TEMPERATURE

MONITOR

(TMON)

ISL6504, ISL6504A

TO 3V3

EA3

1V2VID

UV COMP

5VDL

April 13, 2004

FN9062.2

4.10V

GND

FIGURE 1.

VID_CT

VID_PG

10mA

Simplified Power System Diagram

www.BDTIC.com/Intersil

+5VIN

+12VIN

+5VSB

+3.3VIN

ISL6504, ISL6504A

1.5VSB

1.5V

3.3VDUAL /3. 3VSB

3.3V

FAULT

SHUTDOWN

Typical Application

+5VIN

+12VIN

+5VSB

+3.3VIN

VOUT1

1.5VSB COUT1

RDLA

1V5SB

3V3DLSB

LINEAR

REGULATOR

LINEAR

CONTROLLER

ISL6504/A

FIGURE 2.

3V3

LINEAR

REGULATOR

CONTROL

LOGIC

5VSB

1V2VID

VID_CT

1.2VVID

1.2V

VID_PG

5VDUAL

VOUT2

1.2VVID

COUT2

CCT_VID

3.3VDUAL/3.3VSB

FAULT

SLP_S3

SLP_S5

SHUTDOWN

VOUT3

COUT3

3V3DL

ISL6504/A

FAULT

CSS

GND

VID_PG

5VDLSB

DLA

5VDL

FIGURE 3.

COUT4

VID PGOOD

5VDUAL

VOUT4

April 13, 2004

FN9062.2

ISL6504, ISL6504A

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage, V

DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V

All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V

ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . .2kV

Recommended Operating Conditions

Supply Voltage, V

Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V

Digital Inputs, V

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0

Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ

2. θ

“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3

VCC SUPPLY CURRENT

Nominal Supply Current I Shutdown Supply Current I

POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS

Rising 5VSB POR Threshold --4.5V 5VSB POR Hysteresis -0.9- V Rising 3V3 Threshold -2.75- V 3V3 Hysteresis - 150 - mV Falling Threshold Timeout (All Monitors) -10- µs Soft-Start Current I Shutdown Voltage Threshold V VID_PG Rising Threshold -1.02- V VID_PG Hysteresis -56- mV

LINEAR REGULATOR (V

1.5V

Regulation --2.0% 1V5SB Nominal Voltage Level V 1V5SB Undervoltage Rising Threshold -1.25- V 1V5SB Undervoltage Hysteresis -75- mV 1V5SB Output Current I

LINEAR REGULATOR (V

1.2V

VID

Regulation --2.0% 1V2VID Nominal Voltage Level V 1V2VID Undervoltage Rising Threshold -0.96- V 1V2VID Undervoltage Hysteresis -60- mV 1V2VID Output Current I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

5VSB

. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

5VSB

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

)

OUT1

)

OUT2

C to 70oC

C to 125oC

5VSB

5VSB(OFF)VSS

1V5SB

1V2VID

3V3DL

3V3

= 0.8V - 4 - mA

= 3.3V 85 - - mA

= 3.3V 40 - - mA

Thermal Resistance (Typical)

SOIC Package (Note 1) . . . . . . . . . . . 70 N/A

QFN Package (Note 2) . . . . . . . . . . . . 32 4.0

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300

(SOIC - Lead Tips Only) For Recommended soldering conditions see Tech Brief TB389.

(oC/W) θJC (oC/W)

C to 150oC

JC,

-17- mA

-10- µA

--0.8V

-1.5- V

-1.2- V

the

FN9062.2

April 13, 2004

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