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ISL6431

Data Sh eet June 200 1

Advanced Pulse-Width Modulation (PWM)
Controller for Home Gateways

The ISL6431 is a high efficiency, fixed frequency,
synchronousbuck PWM controller. Itis designed for use in
applicationsthat convert5V to lower distributed voltages
required for set-top box, cable modem, DSL modem and
residential home gateway core processor, memory and
peripheral power supplies.

This device makes simple work out of implementing a
complete control and protection scheme for a D C-DC
stepdownconverter.Designed to drive N-channel MOSFETs
in a synchronous buck topology,the ISL6431 integrates the
control, output adjustment, monitoring and protection
functions into a single 8-pin package.

The ISL6431 provides simple, single feedback loop, voltage­mode control with fast transient response. The output
voltagecan be precisely regulated to as low as 0.8V,with a
maximum t olerance of ±1.5% over temperatureand l ine
voltagevariations. A fixed frequency oscillator reduces
design complexity,while balancing typical application cost
and efficiency.

The error amplifier features a 15MHz gain-bandwidth
product and 6V/µs slew rate which enables high converter
bandwidthfor fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.

Protection from overcurrent conditions is provided by
monitoringthe r

DS(ON)

operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense r esistor.

of the upper MOSFET toinhibit PWM

File Number 9018

Features

• Operates from +5V Input

•0.8VtoV

Output Range

IN

- 0.8V Internal Reference

- ±1.5% Over Line Voltage and Temperature

• Drives N-Channel MOSFETs

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast Transient Response

• Lossless, Programmable Overcurrent Protection

- Uses Upper MOSFET’s r

DS(ON)

• Small Converter Size

- 300kHz Fixed Frequency Oscillator

- InternalSoft Start

- 8 Lead SOIC Package

• High Conversion Efficiency

• Synchronous/Standard Buck Configuration

Applications

• Cable Modems, Set TopBoxes, and DSL Modems

• DSP and Core CommunicationsProcessor Supplies

• Power Supplies for Microprocessors and Embedded
Controllers

• Memory Supplies

• Personal Computer Per ipherals

• Industrial Power Supplies

Ordering Information

TEMP.RANGE

PART NUMBER

ISL6431CB 0 to 70 8 Ld SOIC M8.15
ISL6431IB -40 to 85 8 Ld SOIC M8.15
ISL6431EVAL1 Evaluation Board

(oC) PACKAGE

1

PKG.

• 5V-Input DC-DC Regulators

• Low-Voltage Distributed Power Supplies

NO.

Pinout

1

BOOT

2

UGATE

3

GND

LGATE

4

CAUTION: These devices aresensitiveto electrostatic discharge;followproperIC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil andDesign is a trademark of Intersil AmericasInc.

Copyright © Intersil Americas Inc. 2001, All Rights Reserved

8

PHASE
COMP/OCSET

7
6

FB

5

VCC

Block Diagram

ISL6431

V

CC

0.8V

FB

COMP/OCSET

Typical Application

+

-

20µA

SAMPLE

AND

HOLD

ERROR

AMP

V

CC

+

-

COMPARATOR

+

-

OC

PWM

COMPARATOR

+

-

OSCILLATOR

FIXED 300kHz

POR AND

SOFTSTART

PWM

INHIBIT

GATE

CONTROL

LOGIC

GND

BOOT

UGATE

PHASE

VCC

LGATE

R

1

R

2

C

1

R

3

C

3

COMP/OCSET

C

2

ISL6431

7

63

FB

5

VCC

GND

1

2

8

4

C

4

BOOT

UGATE

PHASE

LGATE

C

D

BOOT

C

6

L

OUT

R

4

5

+VO=0.8toV

C

7

IN

2

ISL6431

Absolute M aximum Ratings Thermal Information

Supply Voltage, VCC................................+6.0V

Absolute Boot Voltage, V
Upper Driver Supply Voltage, V

Input, Output or I/O Voltage. . . . . . . . . . . GND -0.3V to VCC +0.3V

.......................+15.0V

BOOT

BOOT-VPHASE

...........+6.0V

ESDClassification.................................Class2

Operating Conditions

SupplyVoltage,VCC............................+5V±10%

AmbientTemperatureRange...................-40

JunctionTemperatureRange.................. -40

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mountedon a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

o

Cto85oC

o

Cto125oC

Thermal Resistance (Typical, Note 1) θ

JA

(oC/W)

SOICPackage............................. 100

MaximumJunctionTemperature...................... 150

MaximumStorageTemperatureRange..........-65

o

Cto150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

o

C

o

C

Electrical Specifications Recommended OperatingConditions, Unless Otherwise Noted V

=5.0V±5% and TA=25oC

CC

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

NominalSupply I

VCC

ISL6431CB; UGATE and LGATE Open - 3.2 - mA
ISL6431IB; UGATE and LGATE Open 2.5 3.2 3.8 mA

POWER-ON RESET

Rising VCC POR Threshold POR ISL6431CB - 4.30 - V

ISL6431IB 4.17 4.30 4.50 V

VCC POR Threshold
Hysteresis

ISL6431CB - 0.20 - V
ISL6431IB 0.01 0.20 0.85 V

OSCILLATOR

Frequency f

OSC

ISL6431CB; VCC = 5V - 300 - kHz
ISL6431IB; VCC = 5V 230 300 340 kHz

Ramp Amplitude ∆V

OSC

ISL6431CB - 1.5 - V
ISL6431IB - 1.5 - V

REFERENCE

Reference Voltage Tolerance ISL6431CB - - 1.5 %

ISL6431IB - - 1.5 %

NominalReferenceVoltage V

REF

ISL6431CB - 0.800 - V
ISL6431IB - 0.800 - V

ERROR AMPLIFIER

DC Gain ISL6431CB - 82 - dB

ISL6431IB - 82 - dB

Gain-BandwidthProduct GBWP ISL6431CB 14 - - MHz

ISL6431IB 14 - - MHz

Slew Rate SR ISL6431CB; COMP = 10pF - 8.0 - V/µs

ISL6431IB; COMP = 10pF 4.5 8.0 9.2 V/µs

GATE DRIVERS

UpperGate Source Current I

UpperGate Sink Current I

UGATE-SRC

UGATE-SNK

ISL6431CB;V
ISL6431IB; V

BOOT-VPHASE

BOOT-VPHASE

ISL6431CB - 1.0 - A

=5V,V

=5V,V

=4V - 1.0 - A

UGATE

=4V - 1.0 - A

UGATE

ISL6431IB - 1.0 - A

LowerGate Source Current I

LGATE-SRC

ISL6431CB; VCC=5V,V
ISL6431IB; V

CC

=5V,V

=4V - 1.0 - A

LGATE

=4V - 1.0 - A

LGATE

P-P
P-P

3

ISL6431

Electrical Specifications Recommended OperatingConditions, Unless Otherwise Noted V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

LowerGate Sink Current I

PROTECTION / DISABLE

OCSET Current Source I

DisableThreshold V

LGATE-SNK

OCSET

DISABLE

Functional Pin Descriptions

VCC (Pin 5 )

This is the main bias supply for the ISL6431, as well as the
lower MOSFET’s gate. Connect a well-decoupled 5V supply
to this pin.

FB (Pin 6)

This pin is the inverting input of the internal error amplifier.
Use this pin, in combination with the COMP/OCSET pin, to
compensate the voltage-control feedback loop of the
converter.

GND (Pin 3)

This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.

PHASE (Pin 8)

Connect this pin to the upper MOSFET source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection. This pin i s also monitored by the
continuously adaptive shoot-through protection circuitry to
determine when the upper MOSFET has turned off.

UGATE (Pin 2)

Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlledgate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot­through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, a s it may
interfere with the internal adaptive shoot-through protection
circuitryand render it ineffective.

BOOT (Pin 1)

This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuitis used to create a
voltagesuitable to drive a logic-level N-channel MOSFET.

COMP/OCSET (P in 7)

This is a multiplexedpin. During a short period of time
followingpower-onreset (POR), this pin is usedto determine
the overcurrent threshold of the converter. Connect a
resistor (R
MOSFET (V

) from this pin to the drain of the upper

OCSET

CC

). R

, an internal 20µA current source

OCSET

ISL6431CB - 2.0 - A
ISL6431IB - 2.0 - A

ISL6431CB 17 20 22 µA
ISL6431IB 14 20 24 µA
ISL6431CB - - 0.8 V
ISL6431IB - - 0.8 V

(I

), and the upper MOSFET on-resistance (r

OCSET

set the converter overcurrent(OC) trip pointaccording to the
following equation:

I

OCSETxROCSE T

----- ----------- ----------- ----------- ---------- -

=

I

PEAK

r

DS O N()

Internal circuitry of the ISL6431 will not recognize a voltage
drop across R
across R

OCSET

OCSET

that is greater than 0.5V will set the

overcurrent trip point to:

PEAK

r

DS ON()

0.5V

----- ----------- ------

=

I

An overcurrent trip cycles the soft-start function.
Pulling OCSET to a level below 0.8V will di sable the

controller. Disabling the ISL6431 causes the oscillator to
stop,the LGATEand UGATE outputs to be held low,and the
softstart circuitry to re-arm.

During soft-start, and all the time during normal converter
operation, this pin represents the output of the error
amplifier. Use this pin, in combination with t he FB pin, to
compensate the voltage-control feedback loop of the
converter.

LGATE (Pin 4)

Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot­through protection circuitry to determine when the lower
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the lower MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitryand r ender it ineffective.

Functional Descriptions

Initialization

The ISL6431 automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the
Overcurrent Protection (OCP) sampling and hold operation
after the supply voltage exceeds its POR threshold. Upon

=5.0V±5% and TA=25oC (Continued)

CC

DS(ON)

larger than 0.5V. Any voltage drop

)

4

ISL6431

completion of the OCP sampling and hold operation, the POR
function initiates the Soft Startoperation.

Over Current Protection

Theovercurrentfunctionprotects the converterfrom a shorted
output by using the upper MOSFET’s on-resistance, r
to monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.

14A

12A

10A

8A

6A

4A

OUTPUT INDUCTOR

2A

0A

TIME (50µs/DIV.)

FIGURE 1. OVERCURRENT OPERATION

The overcurrent function cycles the soft-start function in a
hiccup m ode to provide fault protection. A resistor
(R

) progr ams the overcurrent trip level (see Typical

OCSET

Application diagram).

DS(ON)

in the normal operating load range, find the R

OCSET

resistor

from the equation above with:

1. Themaximumr

2. The minimum I

,

3. Determine I

DS(ON)
OCSET

PEAK

atthe highestjunctiontemperature.
from the specification table.

I

for ,

PEAKIOUT MAX()

∆I()

------ ----+>
2

where ∆I is the output inductor ripple current.

For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.

Soft Start

The POR function initiates the soft start sequence after the
overcurrent set point has been sampled. Soft start clamps the
error amplifier output (COMP pin) and reference input (non­inverting terminal of the error amp) to the internally generated
Soft Startvoltage. Figure 2 shows a typical soft start interval.
Initially the clamp on the error amplifier (COMP/OCSET pin)
controls the converter’s output voltage. The oscillator’s
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitor(s). With sufficient output voltage,
the clamp on the reference input controls the output voltage.
When the internally generated Soft Start voltage exceeds the
feedback (FB pin) voltage, the output voltage is in regulation.
This method provides a rapid and controlled output voltage rise.

Immediately following POR, the ISL6431 initiates the
Overcurrent Protection sampling and hold operation. First,
the internal error amplifieris disabled. This allows an internal
20µA current sink to develop a voltage across R

OCSET

.The
ISL6431 then samples this voltage at the COMP pin. This
sampled voltage, which is referenced to the VCC pin, is held
internallyas the Overcurrent Set Point.

Whenthe voltage across the upper MOSFET, which is also
referenced to the VCC pin, exceeds the Overcurrent Set
Point, the overcurrent function initiates a soft-start sequence.
Figure 1 shows this operationwith an overload condition.This
current is repeated with a 21ms period. Note that the inductor
current increases to over 14A during the Soft Start interval and
causes an overcurrent trip. The converter dissipates very little
power with this method. The measured input power for the
conditionsof Figure 1 is only 0.25W.

The overcurrent function will trip at a peak inductor current
(I

I

where I

PEAK)

PEAK

determined by:

I

OCSETxROCSET

----- ----------- ----------- ----------- ----------- --- -

=

r

DS ON()

is the internal OCSET current source (20µA

OCSET

typical).The OC trip point varies mainly due t o the
MOSFET’s r

DS(ON)

variations.Toavoid overcurrent tripping

V

OUT

500mV/DIV.

0V

TIME (1ms/DIV.)

FIGURE 2. SOFT START INTERVAL

Application Guidelines

Layout Considerations

As in any high frequency switching converter,layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.

5

ISL6431

V

IN

ISL6431

UGATE
PHASE

LGATE

Q

1

Q

2

RETURN

L

O

V

OUT

C

IN

C

O

LOAD

FIGURE 3. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
Please note that the capacitors C

and COmay each

IN

represent numerous physical capacitors. Locate the ISL6431
within 3 inches of the MOSFETs,Q

and Q2. The circuit traces

1

for the MOSFETs’ gate and source connections from the
ISL6431 must be sized to handle up to 1A peak current.

Figure 4 shows the circuit traces that require additional layout
consideration.Usesinglepointandgroundplaneconstruction
for the circuits shown. Minimize any leakage current paths on
the COMP/OCSET pin and locate the resistor, R

OSCET

close
to the COMP/OCSET pin because the internal current source
isonly 20µA. ProvidelocalV
GND pins. Locate the capacitor, C

decoupling between VCC and

CC

as closeas practical

BOOT

to the BOOT and PHASE pins. All components used for
feedback compensation should be located as close to the IC a
practical.

+V

IN

Q

L

1

O

C

Q

2

V

OUT

O

+5V

OCSET

R

ISL6431

COMP/OCSET

GND

BOOT

C

BOOT

PHASE
VCC

+5V

D

1

C

VCC

FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

Feedback Compensation

Figure 5 highli ghts the voltage-mode control l oop fo r a
synchronous-rectified buck converter. The output voltage
(V

) is regulated to the R ef er ence voltage level. The

OUT

error a mpli f ier (Error Amp) output (V
the oscillator (OSC) triangul ar wave to provide a pulse-

) is compared with

E/A

width modulated (PWM) w ave with an amplitude of V

IN

at
the PHASE node. The PWM waveis smoothedby the output
filter (L

∆V

and CO).

O

V

FB

Z

FB

IN

L

O

PHASE

ESR

(PARASITIC)

Z

IN

C

R

3

R

1

OSC

OSC

PWM

COMPARATOR

-

+

Z

FB

V

E/A

-

+

ERROR
AMP

DETAILED COMPENSATION COMPONENTS

COMP

ISL6431

DRIVER

DRIVER

Z

REFERENCE

C

2

C

R

1

2

-

+

REFERENCE

IN

FIGURE 5. VOLTAGE-MODEBUCK CONVERTER

COMPENSATION DESIGN

V

OUT

C

O

V

OUT

3

The modulator transfer function is the small-signal transfer
function of V

OUT/VE/A

Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage(V
peak-to-peakoscillator voltage ∆V

. This function is dominated by a DC

and CO), with a double pole

O

andazeroatF

LC

OSC

. The DC Gain of

ESR

) divided by the

IN

.

Modulator Break Frequency Equations

F

LC

=

2π xL

OxCO

F

ESR

=

1

------ ----------- ----------- ----------- -- -

The compensation network consists of the error amplifier

LOAD

(internalto the ISL6431) and the i mpedance networks Z
and ZFB. The goal of the compensation network is to provide
a closed l oop transfer function with the highest 0dB crossing
frequency(f

) and adequatephase margin. Phase margin

0dB

is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’spoles, zeros and gain to the components(R
R

3,C1,C2

,andC3) in Figure 7. Use these guidelines for

locating the poles and zeros of the compensation network:

1. Pick Gain (R

2. Place1

3. Place 2

4. Place 1

5. Place 2

ST

ND
ST
ND

) for desired converter bandwidth.

2/R1

Zero Below Filter’s Double Pole (~75% FLC).

Zero at Filter’s Double Pole.

Pole at the ESR Zero.

Pole at Half t he Switching Frequency.

1

------ ----------- ----------- ----------- ----

2π xESRxC

O

IN

and

0dB

,

1,R2

6

ISL6431

6. Check Gain against Error Ampl ifier’s Open-Loop Gain.

7. Estimate Phase Margin - Repeat if Necessary.

Compensation Break Frequency Equations

1

----- ----------- ----------- -------- -

=

F

Z1

2π xR

----- ----------- ----------- ----------- ----------- ----- -

F

=

Z2

2π xR

2xC1

1

+()xC

1R3

3

------ ----------- ----------- ----------- ----------- ------ -

=

F

P1

2π xR

------ ----------- ----------- ------- -

F

=

P2

2π xR

Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peakdue to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
looperror amplifier gain bounds the compensation gain.
Check the compensation gain at F

with the capabilities of

P2

the error amplifier. The Closed Loop Gain is constructedon
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensationtransfer function and plottingthe gain.

The compensation gain uses external impedance networks

and ZINto provide a stable,highbandwidth (BW) overall

Z

FB

loop. A stable control loop has a gain crossing with

-20dB/decadeslope and a phase margin greater than 45
degrees. Include worst case component variations when
determiningphase margin.

Refer to the evaluation board application note (available
soon) for a complete reference design schematic and bill of
materials for a typical Residential Gateway application.

100

80

60

40

20LOG
(R

)

2/R1

20

GAIN (dB)

0

MODULATOR

-20

-40

-60

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

GAIN

F

F

F

P1

Z2

Z1

F

LC

F

FREQUENCY (Hz)

(V

ESR

F

P2

20LOG

/DV

IN

1

C



1xC2

------ ----------- ---- -

x



2

C1C2+



1

3xC3

OPEN LOOP
ERROR AMP GAIN

)

OSC

COMPENSATION

GAIN

CLOSEDLOOP

GAIN

10M1M100K10K1K10010

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to f ilter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.

The load transient requirementsare a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.

Highfrequency capacitorsinitially supply the transientand
slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the
ESR (Effective Series Resistance) and voltage rating
requirements rather thanactual capacitance requirements.

High frequency decoupling capacitors should be placed as
closeto the power pins of the load as physicallypossible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
casesize with lower ESR available in largercase sizes.
However,the EquivalentSeries Inductance (ESL)of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
mostcases, multiple electrolytic capacitors of smallcase size
perform betterthan a single largecase capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to t he load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximatedby the following equations:

V

IN-VOUT

∆I =

FsxL

Increasingthe valueof inductancereduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.

One o f the parameters limiting the converter’s response to
a load transient is the ti me required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6431 will provi de either 0% or 100% d ut y cycle in
response to a loa d transient. The response time i s the time
required to slew the inductor current from an ini tial current
value to the transient current level. During thi s interval the
difference between the inductor current and the transient
current level must be supplied by the o utput capacitor.
Minimizing the response time can minimize the output
capacitance r equir ed.

V

OUT

x

V

IN

∆V

OUT

= ∆IxESR

7

ISL6431

The response time to a transient i s different for the
applicationof load and the removal of load. The following
equations give the approximate response time interval for
applicationand removal of a transient load:

LxI

t

=

RISE

where: I

TRAN

VIN-V

OUT

is the transient load current step, t

TRAN

t

FALL

response time t o the application of load, and t

LxI

TRAN

=

V

OUT

is the

RISE

is the

FALL

response time t o the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equationsat the
minimum and maximum output levels for the worst case
response time.

Input C apacitor Selection

Use a mix of input bypass capacitorsto control the voltage
overshoot across the MOSFETs.Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q

turnson. Placethe

1

small ceramic capacitors physically close to the MOSFETs
and between the drain of Q

and the source of Q2.

1

The important parameters for the bulk inputcapacitorare the
voltagerating and the RMS current rating. For reliable
operation, select the bulk capacitorwith voltage and current
ratings above the maximum input voltage and largest RMS
current requiredby the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator i s approximately
1/2 the DC load current.

For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.

MOSFET Selection/Considerations

The ISL6431 requires two N-Channel power MOSFETsfor use
in a synchronous buck configuration.These should be selected
based upon r
management requirements.

, gate supply requirements, and thermal

DS(ON)

across the lowe r MOSFET clamps the switching node
before the synchronous rectifier turns on.

These e quat i ons
assume linear voltage-current tr ansi tio ns and do not
adequately model power loss due the reverse-reco v ery of
the lower MOSFET’s bod y diode. The gate-charge losses
are dissi pated by the ISL6431 and don' t heat the
MOSFETs. However, large gate-charge increases the
switching interval, t

which increases the

SW

upper MOSFET
switching l osses. Ensure that both M O SFETs are within
their maxi mum juncti on temper atur e at high ambient
temperature by calculating the temper atur e rise according
to package thermal-resi stance specificat i ons. A separate
heatsink may be necessary depending upon MOSFE T
power, package type, ambient t em per atur e and air flow.

1

P
P

UPPER

LOWER

=Io2xr

=Io2xr

DS(ON)

DS(ON)

xD+

x(1-D)

Where: D is the duty cycle = V

is the switch ON time, and

t

SW

is the switching frequency.

F

S

Io x V

2

OUT/VIN

INxtSWxFS

,

Given the reduced available gate bias voltage (5V), logic­level or sub-logic-level transistors have to be used for both
N-MOSFETs. Caution should be exercised with devices
exhibitingvery low V

GS(ON)

characteristics, as the low gate
thresholdcould be conducive to some shoot-through(due to
the Miller effect),in spite of the counteracting circuitry
present aboard the ISL6431.

+5V

VCC

ISL6431

-

+

FIGURE 7. UPPER GATE DRIVE BOOTSTRAP

D

BOOT

+VD-

BOOT

UGATE
PHASE

LGATE

GND

C

BOOT

Q1

Q2

+5V

NOTE:
V

G-S

NOTE:
V

G-S

≈ VCC-V

≈ V

CC

D

In hig h-cur r ent applicat io ns, the MOSFET power
dissipation, package selec tion and heatsink are the
dominant design factors. The pow er dissipation includes
two loss components; conduc tion loss and switching loss.
The condu ct ion losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses ar e distributed between the two MOSFETs
according t o duty factor (see the equations b elo w). Only
the upper MOS FET has switching losses, since the lower
MOSFETs body diod e or an external Schottky r ect ifier

8

Figure 7 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V

. The boot capacitor, C

CC

BOOT

,
develops a floating supply voltage referenced to the PHASE
pin. The supply is refreshed to a voltage of V
diode drop (V

) each time the lower MOSFET, Q2, turnson.

D

less the boot

CC

ISL6431

ISL6431 DC-DC Converter Application Circuit

Figure 8 shows an application circuit of a DC-DC Converter.
Detailed information on the circuit, including a complete Bill­of-Materials and circuit board description is available.

+5V

VCC

MONITOR

AND

PROTECTION

+

-

OSC

5

+

-

3

GND

COMP/OCSET

FB

ISL6431

7

REF

6

U

1

+

C

IN

D

1

1

BOOT

UGATE

2

Q

8

4

PHASE

LGATE

1

Q

2

L

1

V

OUT

+

C

OUT

FIGURE 8. DC-DC CONVERTER

9

Small Outline Plastic Packages (SOIC)

ISL6431

N

INDEX
AREA

123

-A­D

e

B

0.25(0.010) C AM BS

E

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

H

α

µ

A1

0.10(0.004)

L

hx45

o

C

NOTES:

1. Symbolsaredefinedin the “MO SeriesSymbol List” in Section2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension“D” does not includemoldflash,protrusionsor gate burrs.
Moldflash,protrusionandgate burrsshallnot exceed 0.15mm(0.006
inch) per side.

4. Dimension“E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminalnumbersare shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controllingdimension: MILLIMETER.Converted inch dimensions
are not necessarilyexact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC ­H 0.2284 0.2440 5.80 6.20 ­h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

All Intersil products are manufactured, assembled and tested utilizingISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautionedto verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How­ever,no responsibilityis assumed by Intersil or its subsidiaries for its use; nor for any infringementsof patents or other rights of third partieswhich may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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