intersil ISL6424 DATA SHEET

®

www.BDTIC.com/Intersil

ISL6424

Data Sheet

Dual Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-Top Box Designs

The ISL6424 is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of two antenna
ports. The device is comprised of two independent current­mode boost PWMs and two low-noise linear regulators along
with the circuitry required for 22kHz tone generation,
modulation and I
total LNB supply design simple, efficient and compact with
low external component count.

Two independent current-mode boost converters provide the
linear regulators with input voltages that are set to the final
output voltages, plus typically 1.2V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drops across each linear pass element
while permitting adequate voltage range for tone injection.

The final regulated output voltages are available at two
output terminals to support simultaneous operation of two
antenna ports for dual tuners. The outputs for each PWM are
set to 13V or 18V by independent voltage select commands
(VSEL1, VSEL2) through the I
compensate for the voltage drop in the coaxial cable, the
selected voltage may be increased by 1V with the line length
compensation (LLC) feature. All the functions on this IC are
controlled via the I
Register (SR, 8 bits). The same register can be read back,
and two bits will report the diagnostic status. Separate enable
commands sent on the I
mode control for each PWM and linear combination, disabling
the output into shutdown mode.

2

C device interface. The device makes the

2

C bus. Additionally, to

2

C bus by writing 8 bits on System

2

C bus provide independent standby

September 13, 2005

FN9175.3

Features

• Single Chip Power Solution

- True Dual Operation for 2-Tuner/2-Dish Applications

- Both Outputs May be Enabled Simultaneously at
Maximum Power

- Integrated DC-DC Converter and I

• Switch-Mode Power Converter for Lowest Dissipation

- Boost PWMs with > 92% Efficiency

- Selectable 13V or 18V Outputs

- Digital Cable Length Compensation (1V)

2

•I

C Compatible Interface for Remote Device Control

- Registered Slave Address 0001 00XX

- Full 3.3V/5V Operation up to 400kHz

• External Pins to Select 13V/18V Option

• DSQIN1&2 and SEL18V1&2 pins 2.5V Logic Compatible

• Built-In Tone Oscillator Factory Trimmed to 22kHz

- Facilitates DiSEqC (EUTELSAT) Encoding

• Internal Over-Temperature Protection and Diagnostics

• Internal Overload and Overtemp Flags (Visible on I

• LNB Short-Circuit Protection and Diagnostics

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline

- Near Chip-Scale Package Footprint

• Pb-Free Plus Anneal Available (RoHS Compliant)

2

C Interface

2

C)

Applications

• LNB Power Supply and Control for Satellite Set-Top Box

References

• Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available
on the Intersil website, www.intersil.com

Each output channel is capable of providing 750mA of
continuous current. The overcurrent limit can be digitally
programmed. The SEL18V pin allows the 13V to 18V
transition with an external pin, overriding the I

The ISL6424 is offered in a 32 Ld 5x5 QFN.

1

2

C input.

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Ordering Information

PAR T # *

ISL6424ER ISL6424ER -20 to 85 32 Ld 5x5 QFN L32.5x5

ISL6424ERZ (Note) ISL6424ERZ -20 to 85 32 Ld 5x5 QFN

*Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PAR T

MARKING

Copyright Intersil Americas Inc. 2004-2005. All Rights Reserved

TEMP.

(°C) PACKAGE

(Pb-free)

PKG.

DWG. #

L32.5x5

Pinout

www.BDTIC.com/Intersil

PGND2

CS2

ISL6424 (QFN)

TOP VIEW

NC

COMP2

VSW2

FB2

GATE2

32 31 30 29 28 27 26 25

1

2

VCC

CPVOUT

24

23

ISL6424

CPSWOUT

TCAP2

SGND

SEL18V1

SEL18V2

BYP

PGND1

GATE1

3

4

FB1

ISL6424ER

VSW1

COMP1

NC

SDA

5

6

7

8

910111213141516

CS1

ADDR

DSQIN2

22

VO2

21

AGND

20

VO1

19

DSQIN1

18

TCAP1

17

SCL CPSWIN

2

FN9175.3

September 13, 2005

Block Diagram

www.BDTIC.com/Intersil

4

14 15 16

COUNTER

GATE1

8

3

PGND1

7

CS1

9

COMP1

11

FB1

10

VSW1

12

VO1

19

OVERCURRENT

PROTECTION

LOGIC SCHEME 1

ILIM1

CS
AMP

PWM

LOGIC

Q

S

∑

COMPENSATION

OLF1

DCL

OC1

CLK1

+

SLOPE

-

­+

VREF1

SEL18V1

BAND GAP

RE F VOLTAG E

REF

VOLTAGE

ADJ1

+

-

SDA

SDA

ISEL1

EN1

ENT1

OTF

LLC1 VSEL1 VSEL2 LLC2

CLK1

BGV

WAVE SHAPING

TONE

INJ

CKT 1

OLF2

OLF1

I2C

INTERFACE

OSC.

220kHz

10 &

÷

22kHz
TONE

ENT2

CLK2

ADDR

SCLADDR

TONE

INJ

CKT 2

SCL

ISEL2

EN2

ENT2

DCL

OLF2

DCL

OC2

CLK2

BGV

REF

VOLTAGE

ADJ2

+

-

OVERCURRENT

PROTECTION

LOGIC SCHEME 2

PWM

LOGIC

Q

S

-

ILIM2

+

∑

SLOPE

COMPENSATION

+

-

VREF2

COUNTER

CS

AMP

GATE2

PGND2

CS2

COMP2

FB2

SEL18V2

VSW2

VO2

32

1

2

30

ISL6424

31

5

29

21

VCC

27

SGND

3

September 13, 2005

FN9175.3

ON CHIP

LINEAR

UVLO

POR

SOFT-START

BYPASS

6

INT 5V

SOFT-START

EN1/EN2

AGND

20

TCAP1

17 18

ENT1

DSQIN1

DSQIN2

22

OTF

TCAP2

23 24

THERMAL

SHUTDOWN

CHARGE PUMP

CPVOUT

CPSWOUT

CPSWIN

26

25

Typical Application Schematic

www.BDTIC.com/Intersil

P1

VIN

P2

GND

E

4

L3

100nH

C25
1µF

E

VOUT1

GND

+5V/+3.3V

C4

1µF

P3

STPS2L40U

P4

P7

C27A

10µF

D3

E

C27B

10µF

0.1µF

C21

+

E

R9
100

C1A
56µF

C9

0.047µF
C2

E

1µF

C8

1µF

D

1737383635346

GATE1
CS1
PGND
COMP1
FB1
VSW1
VO1
DSQIN1

EP

E

TCAP1

SCL

161415313

8
9

7
11
10
12
19
18

33

E

NC

VCC

CPSWIN

CPVOUT

U1

ISL6424

SDA

ADDR

SGNDNCAGND

C10

1000pF

4.7µF

BYP

CPSWOUT

SEL18V1

4

20

D

C21

23

COMP2

DSQIN2

S

5

C1B

10µF

L1
33µH

C3

R1

5.1

1500pF

D1

STPS2L40U

+

C5
56µF

E

C5

33pF

SP1

E

OUT

E

8
7
6
5

FDS6612A

C24

100pF

R3

68K

VL

Q1

0.10

R2

1500pF

0.01µF

1
2
3
4

C7

C30

C15A

56µF

C12

1µF

TCAP2
GATE2

CS2

PGND2

FB2

VSW2

VO2

V

8

1

L

E

+

C15
10µF

L2

8
7
6
5

C24

100pF

C13

R14
100K

33µH

STPS2L40U

R4

0.10

R5

68K

R16
100K

C15

D2

R17
100K

+

E

C14
33pF

C17
56µF

SP2

R15
100K

R6

5.1

C28A
10µF

C28B
10µF

E

C18
1µF

L4

100nH

C26
1µF

E

ISL6424

P5

VOUT2

C19

0.1µF

E

VL

IN

D4
STPS2L40U

P6

E

GND

E

Q2

1

E

2
3

D

4

FDS6612A

R10

32

100

2
1
30
31
29
21
22

2

R13
100K

1500pF

C31

0.01µF

E

SCL
GND
GND
SDA

J1

1x4

1
2
3
4

C29

0.1µF

1
2
3
4

D

R12
10K

R11
10K

R7

100

R8

100

September 13, 2005

FN9175.3

SW1
1
2
3
4
5
6

D

DIP_SW5_SPST

12
11
10
9
8
7

DISQ1
DISQ2
SEL18V1
SEL18V2
ADDR

P9

P8

SEL18V1

SEL18V2