intersil ISL6423B DATA SHEET

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ISL6423B

Data Sheet

Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

The ISL6423B is a highly integrated voltage regulator and interface IC, specifically designed for supplying power and control signals from advanced satellite set-top box (STB) modules to the low noise blocks (LNBs) of singe antenna ports. The device consists of a current-mode boost PWM and a low-noise linear regulator along with the circuitry required for 22kHz tone generation, modulation and I device interface. The device makes the total LNB supply design simple, efficient and compact with low external component count.

The current-mode boost converters provides the linear regulator with input voltage that is set to the final output voltages, plus typically 0.8V to insure minimum power dissipation across each linear regulator. This maintains constant voltage drop across the linear pass element while permitting adequate voltage range for tone injection.

The final regulated output voltage is available at output terminals to support the operation of an antenna port for single tuners. The outputs for each PWM can be controlled in two ways, full control from I bits or set the I switch to higher range i.e., 18V/19V, with the SELVTOP pin. All the functions on this IC are controlled via the I writing 8 bits words onto the System Registers (SR). The same register can be read back, and five I the diagnostic status. Separate enable command sent on the

C bus provides for standby mode control for the PWM and linear combination, disabling the output and forcing a shutdown mode. The output channel is capable of providing 750mA of continuous current. The overcurrent limit can be digitally programmed to four levels.

The External modulation input EXTM can accept a modulated Diseqc command and transfer it symmetrically to the output. Alternatively the EXTM pin can be used to modulate the continuos internal tone.

The FLT any condition turns OFF the LNB controller (Over Temperature, Overcurrent, Disabled). The nature of the Disable can be read of the I

C to the lower range i.e., 13V/14V, and

pin serves as an interrupt for the processor when

C using the VTOP and VBOT

C bits will report

C registers.

C bus by

April 10, 2007

FN6412.1

Features

• Single Chip Power solution

- Operation for 1-Tuner/1-Dish Applications

- Integrated DC/DC Converter and I

• Switch-Mode Power Converter for Lowest Dissipation

- Boost PWMs with >92% Efficiency

- Selectable 13.3V or 18.3V Outputs

- Digital Cable Length Compensation (1V)

-I

C and Pin Controllable Output

• Output Back Bias Capability of 28V

C Compatible Interface for Remote Device Control

•I

• Registered Slave Address 0001 00XX

• 2.5V, 3.3V, 5V Logic Compatible

• External Pin to Toggle Between V and H Polarization

• Built-In Tone Oscillator Factory Trimmed to 22kHz

- Facilitates DiSEqC (EUTELSAT) Encoding

- External Modulation Input

• Internal Over-Temperature Protection and Diagnostics

• Internal OV, UV, Overload and Overtemp Flags (Visible on I

signal

•FLT

• LNB Short-Circuit Protection and Diagnostics

• QFN, EPTSSOP Packages

• Pb-Free Available (RoHS Compliant)

C Interface

Applications

• LNB Power Supply and Control for Satellite Set-Top Box

Ordering Information

PART

NUMBER*

ISL6423BERZ (Note)

ISL6423BEVEZ (Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Add “-T” suffix for tape and reel.

PART

MARKING

6423BERZ -20 to +85 24 Ld 4x4 QFN

ISL6423BEVEZ -20 to +85 28 Ld EPTSSOP

TEMP.

(°C) PACKAGE

(Pb-free)

PKG.

DWG . #

L24.4x4D

M28.173B

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Pinouts

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VCC

FLT SGND SGND

TCAP ADDR0 ADDR1

BYPASS

PGND

GATE

VSW

NC CS

ISL6423B

(28 LD EPTSSOP)

TOP VIEW

1 2 3 4 5 6 7 8

9 10 11 12 13 14

ISL6423B

(24 LD QFN)

TOP VIEW

CPSWIN

CPSWOUT

CPVOUT

EXTM

SDA

SCL

TDOUT

TDIN

21 20

VO NC

AGND

17 16

SELVTOP TXT

SGND

TCAP

ADDR0

ADDR1

BYPASS

PGND

SGND

FLT

VCC

CPSWIN

TXT

24 23 22 21 20 19

789101112

GATE

VSW

CPSWOUT

SELVTOP

CPVOUT

AGND

EXTM

SDA

SCL

TDOUT

TDIN

FN6412.1

April 10, 2007

Block Diagram

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CLK1

SLOPE

OLF/BCF

DCL

OC1

VREF1

SELVTOP

BAND GAP

REF VOLTAGE

REF

VOLTAGE

ADJ1

COUNTER

GATE

PGND

TDOUT

TONE

DECODER

TDIN

VSW

OVERCURRENT

PROTECTION

LOGIC SCHEME 1

ILIM1

CS AMP

PWM

LOGIC

∑

COMPENSATION

TXT

TTH

SDA

ISELL&H EN ENT

VTOP

BGV

TONE

INJ

CKT

SCL

VBOT

CLK1

OLF/BCF

I2C

INTERFACE

OSC.

DIV &

WAVE SHAPING

INT

TONE

ADDR0

316

ADDR0

ADDR1

OUVF

OTF

TTH DCL

FLT

THERMAL

SHUTDOWN

AGND

VCC

SGND

April 10, 2007

FN6412.1

NOTE:

ON CHIP

LINEAR

UVLO

POR

SOFT-START

BYPASS

INT 5V SOFT-START

EN1/EN2

TXT

1. Pinouts shown are for the QFN package.

TCAP

MSEL1

EXTM

EXT TONE CKT

ENT1

CPSWOUT

CPSWIN

20 21

CHARGE PUMP

CPVOUT

Typical Application Schematic QFN

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VIN

RTN

C24 1µF

1 2 3 4 5 6

SGND TCAP ADDR0 ADDR1 BYPASS PGND

L5 15µH

C23 56µF

1234

TPC6002 Q2

R10

0.1

R9 470

C21

100pF

C27

C26

0.22µF

1µF

C29 1n

FLT

VCC

SGND

ISL6423ER

VSW

GATE

8CS9

C25 47n

CPSWIN

CPVOUT

EXTM

CPSWOUT

SDA

TDOUT

TDIN

TXT10AGND

SELVTOP

SCL

18 17 16 15 14 13

C16

10n

CMS06

C28

0.1µF

R11 100

R12

CMS06

R13 4.7k

R22

47k

100

R23

10k

R24

4.7k

220µH

1 2

C15

0.22µF

NDS356AP

Q4 2N2222A

FLT BAR

EXTM

SDA SCL

VLNB

1.5KE24

RTN

TXT

TDOUT

SELVTOP

CMS06

April 10, 2007

FN6412.1

C22 56µF

C18 10µF

4.7µH

1 2

C19 10µF

C20 10µF

NOTE : SDA and SCL require pull up to the required logic level.

Absolute Maximum Ratings Thermal Information

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Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V

Logic Input Voltage Range

(SDA, SCL, ENT, DSQIN 1 and 2, SEL18V 1 and 2) . -0.5V to 7V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

3. For θ

4. +150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150°C junction may

, the "case temp" location is the center of the exposed metal pad on the package underside.

trigger the shutdown of the device even before +150°C, since this number is specified as typical.

Thermal Resistance (Typical, Notes 2, 3) θJA (°C/W) θJC (°C/W)

QFN Package (Notes 2, 3). . . . . . . . . . 38 4.5

EPTSSOP Package (Notes 2, 3) . . . . . 35 2.5

Maximum Junction Temperature (Note 4) . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-40°C to +150°C

Operating Temperature Range . . . . . . . . . . . . . . . . .-20°C to +85°C

Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Operating Supply Voltage Range 81214 V Standby Supply Current EN = L - 1.5 3.0 mA Supply Current I

UNDERVOLTAGE LOCKOUT

Start Threshold 7.5 - 7.95 V Stop Threshold 7.0 - 7.55 V Start to Stop Hysteresis 350 400 500 mV

SOFT-START

COMP Rise Time (Note 5) (Note 5) - 8196 - Cycles Output Voltage (Note 5) V

Line Regulation DV

Load Regulation DV

Dynamic Output Current Limiting I

Dynamic Overload Protection Off Time TOFF DCL = 0, Output Shorted (Note 8) - 900 - ms Dynamic Overload Protection On Time TON - 51 - ms Static Output Current Limiting I Cable Fault CABF Threshold I

= 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN = H, VTOP

VBOT = L, ENT = L, DCL = L, I access to the system.

EN = VTOP = VBOT = ENT = H, No Load - 4.0 8.0 mA

(Refer to Table 1) 13.04 13.3 13.56 V (Refer to Table 1) 14.02 14.3 14.58 V (Refer to Table 1) 17.94 18.3 18.66 V (Refer to Table 1) 19.00 19.3 19.68 V VIN = 8V to 14V; VO = 13.3V - 4.0 40.0 mV

O1,

= 8V to 14V; VO = 18.3V - 4.0 60.0 mV

IO = 0mA to 350mA - 50 80 mV

= 0mA to 750mA - 100 200 mV

DCL = 0, ISEL H = 0, ISEL L = 0 (Note 8) 275 305 345 mA DCL = 0, ISEL H = 0, ISEL L = 1 (Note 8) 515 570 630 mA DCL = 0, ISEL H = 1, ISEL L = 0 (Note 8) 635 705 775 mA DCL = 0, ISEL H = 1, ISEL L = 1 (Note 8) 800 890 980 mA

DCL = 1 (Note 8) - 1000 - mA EN = 1, VO = 19V, No Tone. 2 10 20 mA

V V V

MAX

MAX CAB

O1 O1 O1 O1

= 12mA, unless otherwise noted. See software description section for I2C

OUT

FN6412.1

April 10, 2007

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