intersil ISL6422 DATA SHEET

®
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ISL6422
Data Sheet
Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs
The ISL6422 is a highly integrated voltage regulator and interface IC, specifically designed for supplying power and control signals from advanced satellite set-top box (STB) modules to the low noise blocks (LNBs) of two antenna ports. The device is consists of two independent current-mode boost PWMs and two low-noise linear regulators along with the circuitry required for 22kHz tone generation, modulation and I makes the total LNB supply design simple, efficient and compact with low external component count.
Two independent current-mode boost converters provide the linear regulators with input voltages that are set to the final output voltages, plus typically 0.8V to insure minimum power dissipation across each linear regulator. This maintains constant voltage drops across each linear pass element while permitting adequate voltage range for tone injection.
The final regulated output voltages are available at two output terminals to support simultaneous operation of two antenna ports for dual tuners. The outputs for each PWM can be controlled in two ways:
• Full control from I and VBOT12 bits, or
• Set the I higher range (18V/19V) with the SELVTOP1 or SELVTOP2 pin.
All the functions on this IC are controlled via the I writing 8-bit words onto the System Registers (SR). The same register can be read back, and 4-bits per output will report the diagnostic status. Sepa ra t e en a b le c om m a n d s s en t on the I each PWM and linear combination, disabling the output into shut d ow n m od e . Each output channel is capable of providing 750mA of continuous current. The overcurrent limit can be digitally programmed.
The External modulation input EXTM1, EXTM2 can accept a modulated Diseqc command and transfer it symmetrically to the output. Alternatively, the EXTM1 or EXTM2 pin can be used to modulate the continuous internal tone.
The FLT an over temperature, overcurrent or backwards overcurrent fault conditions is detected by the LNB controller or when both channels are disabled by the I nature of the fault can be read of the I
2
C to the lower range (13V/14V) and switch to the
2
C bus provide independent standby mode control for
pin serves as an interrupt for the processor when
2
C using the VTOP1, VTOP2, VBOT1,
2
C device interface. The device
2
C bus by
2
C EN bits set low. The
2
C registers.
August 10, 2007
FN9190.2
Features
• Single Chip Power Solution
- True Dual Operation for 2-Tuner/2-Dish Applications
- Both Outputs May be Enabled Simultaneously at Maximum Power
- Integrated DC/DC Converter and I
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with >92% Efficiency
- Selectable 13.3V or 18.3V Outputs
- Digital Cable Length Compensation (1V)
2
C and Pin controllable output
-I
• Output Back Bias Capability of 28V
2
C Compatible Interface for Remote Device Control
•I
• Four level Slave Address 0001 00XX
• 2.5V, 3.3V, 5V Logic Compatible
• External Pins to Toggle Between V and H Polarization.
• Supports DiSEqC 2.0 Protocol
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
- External Modulation Input
• Internal Over-Temperature Protection and Diagnostics
• Internal OV, UV, Overload and Over-Temperature Flags (Visible on I
Signal
•FLT
• LNB Short-Circuit Protection and Diagnostics
• QFN, EPTSSOP Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
2
C)
2
C Interface
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
Ordering Information
PART NUMBER
(Note)
ISL6422ERZ* ISL6422 ERZ -20 to +85 40 Ld 6x6 QFN L40.6x6 ISL6422EVEZ* ISL6422 EVEZ -20 to+ 85 38 Ld EPTSSOP M38.173B
*Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG . #
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
Pinouts
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EXTM2
SGND
NC
FLT
SDA
SCL
ADDR0
ADDR1
EXTM1
BYP
ISL6422
(40 LD QFN)
TOP VIEW
SELVTOP2
TXT2
CS2
NC
NC
VSW2
ISL6422ERZ
CS1
VSW1
TXT1
SELVTOP1
GATE2
PGND2
39 38 37 36 35 34 33 32 31
40
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20
GATE1
PGND1
TCAP1 TCAP2
NC
AGND
VOUT2
VOUT1
ISL6422
VOUT2
30
29
TDIN2
28
TDOUT2
27
CPVOUT
26
CPSWOUT
CPSWIN
25
24
VCC
23
TDOUT1
TDIN1
22
VOUT1
21
CS2 VSW2 VSW2
GATE2
PGND2
EXTM2
SGND
FLT
SDA
SCL
ADDR0 ADDR1
EXTM1
BYP
PGND1
GATE1
VSW1 VSW1
CS1
ISL6422
(38 LD EPTSSOP)
TOP VIEW
1 2 3 4 5 6 7 8 9
ISL6422EVEZ
10 11 12 13 14 15 16 17 18 19
TXT2
38
SELVTOP2
37
TCAP2
36
NC
35
VOUT2
34
TDIN2
33
TDOUT2
32
CPVOUT
31 30
CPSWOUT CPSWIN
29
VCC
28
TDOUT1
27 26
TDIN1 VOUT1
25
AGND
24
TCAP1
23
SELVTOP1
22 21
NC TXT1
20
2
FN9190.2
August 10, 2007
Block Diagram
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17
5
8
4
76
COUNTER
GATE1
12
3
PGND1
11
CS1
15
TDOUT1
23
TONE
DECODER
TDIN1
22
VSW1
14
19
24
2
NOTE:
VOUT1
AGND
VCC
SGND
20, 21
August 10, 2007
FN9190.2
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
ILIM1
CS AMP
ON CHIP
LINEAR
UVLO
POR
SOFT-START
BYP
10
PWM
LOGIC
Q
S
COMPENSATION
TXT1
INT 5V SOFT-START
EN1/EN2
OLF1
DCL1
OC1
CLK1
+
SLOPE
TXT1
16
-
­+
VREF1
SELVTOP1
+
-
BAND GAP
REF VOLTAGE
REF
VOLTAGE
ADJ1
SCL
SDA
SDA
SCL
ISEL1L AND ISEL1H
EN1 ENT1 OTF
VTOP1
BGV
TONE
INJ
CKT 1
MSEL1
TCAP1
18
EXTM1
OLF1
FLT
FLT
ADDR0
OLF2
ADDR1
ADDR1
I2C
INTERFACE
VBOT1 VBOT2
CLK1
MSEL2
EXT TONE CKT
9
OSC.
1.1MHz
DIV AND
WAVE SHAPING
INT
TONE
ENT1
EXTM2
1
CLK2
ENT2
ADDR0
OUVF11
ISEL2L AND
TCAP2
33
OUVF1
OUVF2
ISEL2H
VTOP2
TONE
INJ
CKT 2
OUVF2
EN2
ENT2
DCL
OTF
TXT2
35
OLF2
DCL2
OC2
CLK2
BGV
REF
VOLTAGE
ADJ2
THERMAL
SHUTDOWN
OVERCURRENT
PROTECTION
LOGIC SCHEME 2
PWM
LOGIC
Q
S
­+
SLOPE
COMPENSATION
+
VREF2
+
-
CHARGE PUMP
ILIM2
-
CPVOUT
27
COUNTER
PGND2
CS
AMP
SELVTOP2
TXT2
TDOUT2
TONE
DECODER
CPSWIN
CPSWOUT
26
GATE2
CS2
VSW2
VOUT2
TDIN2
39
40
36
ISL6422
34
37
30, 31
28
29
25
1. Pinouts shown are for the QFN package.
Typical Application Schematic QFN
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4
ISL6422
August 10, 2007
FN9190.2
ISL6422
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ENT, DSQIN1 and DSQIN2,
SEL18V1 and SEL18V2) . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES:
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
2. θ
JA
Tech Brief TB379.
3. For θ
4. The device junction temperature should be kept below +150°C. Thermal shut-down circuitry turns off the device if junction temperature exceeds
, the "case temp" location is the center of the exposed metal pad on the package underside.
JC
+150°C typically.
Thermal Resistance (Typical, Notes 2, 3) θ
EPTSSOP Package. . . . . . . . . . . . . . . 29 4
QFN Package. . . . . . . . . . . . . . . . . . . . 34 6
Maximum Junction Temperature (Note 4) . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . . .-40°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.aspOperating
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-20°C to +85°C
(°C/W) θJC (°C/W)
JA
Electrical Specifications V
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage Range 81214 V Standby Supply Current EN1 = EN2 = L 1.5 3.0 mA Supply Current I
UNDERVOLTAGE LOCKOUT
Start Threshold 7.5 7.95 V Stop Threshold 7.0 7.55 V Start to Stop Hysteresis 350 400 500 mV
SOFT-START
COMP Rise Time (Note 5) (Note 5) 8196 Cycles Output Voltage (Note 5) V
Line Regulation DV
Load Regulation DV
= 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN1 = EN2 = H,
CC
VTOP1 = VTOP2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, I noted. See “ISL6422 Software Description” on page 12 for I
EN1 = EN2 = VTOP1 = VTOP2 = VBOT1 = VBOT2 = ENT1 = ENT2 = H, No Load
(Refer to Table 11) 13.04 13.3 13.56 V (Refer to Table 11) 14.02 14.3 14.58 V (Refer to Table 11) 17.94 18.3 18.66 V (Refer to Table 11) 19.00 19.3 19.68 V (Refer to Table 15) 13.04 13.3 13.56 V (Refer to Table 15) 14.02 14.3 14.58 V (Refer to Table 15) 17.94 18.3 18.66 V (Refer to Table 15) 19.00 19.3 19.68 V VIN = 8V to 14V; V
= 8V to 14V; V
V
IN
IO = 12mA to 350mA 50 80 mV
= 12mA to 750mA 100 200 mV
I
O
OUT1 OUT1
, V
, V
OUT2 OUT2
V V V V V V V
DV
DV
IN
OUT1 OUT1 OUT1 OUT1 OUT2 OUT2 OUT2 OUT2
OUT1,
OUT2
OUT1,
OUT2
2
C access to the system.
= 13V 4.0 40.0 mV = 18V 4.0 60.0 mV
= 12mA, unless otherwise
OUT
4.0 8.0 mA
5
FN9190.2
August 10, 2007
ISL6422
www.BDTIC.com/Intersil
Electrical Specifications V
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Dynamic Output Current Limiting (Note 8)
Dynamic Overload Protection Off Time t Dynamic Overload Protection On Time t Static Output Current Limiting I Cable Fault CABF Asserted High I
TONE OSCILLATOR
Tone Frequency f Tone Amplitude V Tone Duty Cycle dc Tone Rise or Fall Time t
TONE DECODER
Input Amplitude Vtdin 200 1000 mV Frequency Capture Range Ftdin 17.5 26.5 kHz Input Impedance Z Detector Output Voltage V Detector Output Leakage I Tone Decoder Rx Threshold V Tone Decoder Tx Threshold V
LINEAR REGULATOR
Drop-out Voltage I Output Backward Leakage Current I Output Backward Leakage Current I Output Backward Current Threshold I Output Backward Voltage I Output Undervoltage
(Asserted high during soft-start) Output Overvoltage
(Asserted high during soft-start)
= 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN1 = EN2 = H,
CC
VTOP1 = VTOP2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, I noted. See “ISL6422 Software Description” on page 12 for I
I
MAX
OFF
ON MAX CAB
tone
tone
tone
, t
r
DET
TDOUT_L
TDOUT_H
RXth TXth
OBK OBK
OBKTH
OBK
DCL = 0, ISEL1H and ISEL2H = 0, ISEL1L and ISEL2L = 0, ISEL1R and ISEL2R = 0
DCL = 0, ISEL1H and ISEL2H = 0, ISEL1L and ISEL2L = 0, ISEL1R and ISEL2R = 1
DCL = 0, ISEL1H and ISEL2H = 0, ISEL1L and ISEL2L = 1, ISEL1R and ISEL2R = 1
DCL = 0, ISEL1H and ISEL2H = 1, ISEL1L and ISEL2L = 0, ISEL1R and ISEL2R = 1
DCL = 0, ISEL1H and ISEL2H = 1, ISEL1L and ISEL2L = 1, ISEL1R and ISEL2R = 1
DCL = L, Output Shorted (Note 8) 900 ms
DCL = 1 (Note 8) 990 mA EN1 and EN2 = 1; 2 10 20 mA
ENT1 and ENT2 = H 20.0 22.0 24.0 kHz ENT1 and ENT2 = H, I ENT1 and ENT2 = H 40 50 60 % ENT1 and ENT2 = H 5 10 14 μs
f
Tone Present, I Tone absent, VO = 6V 10 μA TXT1 and TXT2 = L 100 150 200 mV TXT1 and TXT2 = H 400 450 500 mV
= 750mA 0.8 1.0 V
OUT
EN1 and EN2 = 0; V EN1 and EN2 = 0; V EN1 and EN2 = 1; V EN1 and EN2 = 0 27 V OUVF1, OUVF2 bit is asserted high,
measured from the typ output set value OUVF1, OUVF2 bit is asserted high,
measured from the typ output set value
LOAD
= 5mA 500 680 800 mV
OUT
= 3mA 0.4 V
= 27V 2.0 3.0 mA
OBK
= 28V 15.0 17.0 mA
OBK
= 19V (Note 7) 125 mA
OFAULT
2
C access to the system. (Continued)
270 305 345 mA
350 388 422 mA
515 570 630 mA
635 705 775 mA
800 890 980 mA
-6 2 %
+2 +6 %
= 12mA, unless otherwise
OUT
20 ms
8.6 kΩ
6
FN9190.2
August 10, 2007
ISL6422
www.BDTIC.com/Intersil
Electrical Specifications V
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
TXT1 AND TXT2, EXTM1 AND EXTM2, SELVTOP1 AND SELVTOP2, ADDR0 AND ADDR1 INPUT PINs (Note 8)
Asserted LOW 0.8 V Asserted HIGH 1.7 V Input Current 25 μA
CURRENT SENSE (CS pin)
Input Bias Current I Overcurrent Threshold V
ERROR AMPLIFIER
Open Loop Voltage Gain A Gain Bandwidth Product
PWM
Maximum Duty Cycle 90 93 % Minimum Pulse Width 20 ns
OSCILLATOR
Oscillator Frequency f Thermal Shutdown Temperature Shutdown Threshold 150 °C Temperature Shutdown Hysteresis 20 °C
FLT
FLT (released) VO = 6V 10 µA
(asserted) I
FLT
NOTES:
5. Internal digital soft-start.
6. The EXTM1 and EXTM2, SELVTOP1 and SELVTOP2, TXT1 and TXT2, and ADDR0 and ADDR1 pins have 200k internal pull-downs.
7. On exceeding this dynamic back current limit threshold for a period of 100µs, the device enters the dynamic current limit mode, and the BCF I bit is set. The dynamic back current limit duty during a BCF is ON = 100µs or OFF = 5ms.
8. In the dynamic back current limit mode, the output is ON for 20ms and OFF for 900ms, but remains continuously ON in the Static mode. When tone is ON, the minimum current limit is 50mA lower than the values indicated in the table. While in the dynamic mode of current limit, the trip level is momentarily increased to 990mA during the 20ms ON time to facilitate recovery from overload conditions.
= 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN1 = EN2 = H,
CC
VTOP1 = VTOP2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, I noted. See “ISL6422 Software Description” on page 12 for I
BIAS
CS
OL
GBP
Static current mode, DCL = H 325 450 500 mV
o
Fixed at (20) (f
= 3.2mA (1.5k pull-up resistor to 5V) 0.4 V
SINK
) 396 440 484 kHz
tone
2
C access to the system. (Continued)
= 12mA, unless otherwise
OUT
700 nA
88 dB 14 MHz
2
C
7
FN9190.2
August 10, 2007
Tone Waveform
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ENT1/2
2
C
I
MSEL1/2
2
C
I
EXTM1/2
PIN
VOUT1/2
PIN
22kHz 22kHz 22kHz 22kHz22kHz 22kHz
ISL6422
Internal Tone
= 10µs typ
t
r
= 10µs typ
t
r
Returns to nominal V after the last EXTM rising edge
OUT
~1 period
= 10µs typInternal Tone
t
r
Internal Tone
t >55µs
FIGURE 1. TONE WAVEFORM
NOTES:
9. The logic presented to the signal pins TXT1 and TXT2 changes the decoder threshold during tone Transmit and Receive. TTH1 and TTH2 allow threshold control through the I
2
C provided that TXT1 and TXT2 = 0.
10. The tone rise and fall times are not shown due to resolution of graphics. It is 10µs typ for 22kHz.
11. The EXTM1 and EXTM2 pins have input thresholds of V
IL(max)
= 0.8V and V
IH(min)
= 1.7V
Typical Performance Curves
IN A
OUT
I
0.82
0.81
0.80
0.79
0.81
0.76
IN A
OUT
I
0.71
0.78 020406080
TA (°C)
FIGURE 2. OUTPUT CURRENT DERATING 38 LD HTSSOP:
I
_max vs T
OUT
A
0.66 020406080
FIGURE 3. OUTPUT CURRENT DERATING 40 LD 6x6 QFN:
NOTE: With both channels in simultaneous operation at rated output.
\
8
I
OUT
_max vs T
T
(°C)
A
A
FN9190.2
August 10, 2007
ISL6422
www.BDTIC.com/Intersil
Functional Pin Descriptions
SYMBOL FUNCTION
2
SDA Bidirectional data from/to I
2
OUT
C bus.
.
SCL Clock from I VSW1 and VSW2 Input of the linear post-regulator. PGND1 and PGND2 Dedicated ground for the output gate driver of respective PWM. CS1 and CS2 Current sense input; connect the sense resistor Rsc at this pin for desired overcurrent value for respective PWM. SGND Small signal ground for the IC. TCAP1 and TCAP2 Capacitor for setting rise and fall time of the output of LNB A and LNB B respectively. Typical value is 0.22µF. BYP Bypass capacitor for internal 5V. TXT1 and TXT2 TXT1 and TXT2 are the Tone T ransmit signal inputs used to change the tone decoder threshold. The threshold is 200mV
max for the Rx mode when the TXT1 and TXT2 are set low. The threshold is 400mV min in the Tx mode when TXT1 and TXT2 are set high. If Tx/Rx mode is set by I
(5V) by an on-chip driver. VCC Main power supply to the chip. GATE1 and GATE2 These are the device outputs of PWM A and PWMB respectively. These high current driver outputs are capable of
VOUT1 and VOUT2 Output voltage for LNB A and LNB B respectively. ADDR0 and ADDR1 Address pins select four different device addresses per Table 19. EXTM1 and EXTM2 These pins can be used in two ways:
FLT This is an open drain output from the controller. When the FLT goes low, it indicates that an Over-Temperature has
CPVOUT, CPSWIN, CPSWOUT
SELVTOP1 and SELVTOP2
TDIN1 and TDIN2 TDOUT1 and TDOUT2
AGND Analog ground for the IC.
driving the gate of a power FET. These outputs are actively held low when V
1. As an input for externally modulated DiSEqC tone signal that is transferred symmetrically onto V
2. Alternatively apply a DiSEqC modulation envelope that modulates an internal tone and then transfers it symmetrically onto V
occurred. The processor should then look at the I indicates that the device is functioning normally.
A 47nF charge pump cap is connected to CPVOUT. Connect a 1.5nF capacitor between CPSWIN and CPSWOUT.
The following description applies to both pins and both bits. When this pin is low, the V When this pin is high, the 18V/19V range is selected by the I The voltage select pin voltage VSPEN1 and VSPEN2 I to be active. Setting VSPEN1 and VSPEN2 high disables these pins and voltage selection will be done using the I bits VBOT1 and VBOT2 and VTOP1 and VTOP2 only.
TDIN1 and TDIN2 are the tone decoder inputs for Channels 1 and 2. TDOUT1 and TDOUT2 are the tone detector outputs for Channels 1 and 2. TDOUT1 and TDOUT2 are open drain ou tputs.
C bus.
2
C bit TTH(1 ,2), when TTH(1, 2) = 1, then TXT(1, 2) will be driven high
is below the UVLO threshold.
CC
2
C register to get the actual cause of the error. A high on the FLT
is in the 13V/14V range selected by the I2C bit VBOT1 and VBOT2.
OUT
2
C bit VTOP1 and VTOP2.
2
C bit must be set low for the SELVTOP1 and SELVTOP2 pins
OUT
.
2
C
9
FN9190.2
August 10, 2007
ISL6422
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Functional Description
The ISL6422 dual output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. Both supply and control voltage outputs for two low-noise blocks (LNBs) are available simultaneously in any output configuration. The device utilizes built-in DC/DC step up converters that, from a single supply source ranging from 8V to 14V, generate the voltages that enable the linear post-regulators to work with a minimum of dissipated power. An undervoltage lockout circuit disables the device when VCC drops below a fixed threshold (7.5V typical).
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of 22kHz in accordance with DiSEqC (EUTELSAT) standards. No further adjustment is required. The tone oscillator can be controlled either by the I a dedicated pin (EXTM1 or EXTM2) that allows immediate DiSEqC data encoding separately for each LNB. All the functions of this IC are controlled via the I the system registers. The same registers can be read back, and four bits will report the diagnostic status. The internal oscillator operates the converters at twenty times the 22k tone frequency . The device offers full I supports 2.5V, 3.3V or 5V logic, and up to 400kHz operation.
If the Tone Enable bits (ENT1 and ENT2) are set LOW and the MSEL1 and MSEL2 bits set LOW through I EXTM1 and EXTM2 terminal activates the internal tone signal, modulating the DC output with a 680mV symmetrical tone waveform. The presence of this signal usually provides the LNB with information about the band to be received.
Burst coding of the tone can be accomplished due to the fast response of the EXTM1 and EXTM2 input and rapid tone response. This allows implementation of the DiSEqC (EUTELSAT) protocols.
When the ENT1 or ENT2 bit is set HIGH, a continuous 22kHz tone is generated regardless of the EXTM1 and EXTM2 pin logic status for the corresponding regulator channel (LNB-A or LNB-B). The ENT1 or ENT2 bit must be set LOW when the EXTM1 and/or EXTM2 pin is used for DiSEqC encoding.
The EXTM1 and EXTM2 pins also accept an externally modulated tone command when the MSEL1 or MSEL2 I bit is set high.
DiSEqC Decoder
TDIN1 and TDIN2 are the inputs to the tone decoders of Channels 1 and 2 respectively. They accept the tone signal derived from the V capacitor. The detector threshold can be set to 200mV maximum in the Receive mode and to 400mV minimum in the Transmit mode by means of the logic presented to the
2
C interface (ENT1 or ENT2 bit) or by
2
C bus by writing to
2
C compatibility and
through the 10nF decoupling
OUT
2
C, then the
typ
P-P
2
C
TXT1 or TXT2 pin. If tone is detected, the open drain pin TDOUT1 or TDOUT2 is asserted low. This also enables the tone diagnostics to be performed, apart from the normal tone detection function.
Linear Regulator
The output linear regulator will sink and source current. This feature allows full modulation capability into capacitive loads as high as 0.75µF. In order to minimize the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout.
When the device is put in the shutdown mode (EN1 and EN2 = LOW), both PWM power blocks are disabled (that is, when EN1 = 0, PWM1 is disabled, and when EN2 = 0, PWM2 is disabled).
When the regulator blocks are active (EN1 and EN2 = HIGH, and VSPEN1 and VSPEN2 = LOW), the output can be controlled via I between 18V and 19V (typical) by means of the Voltage Select bits (VTOP1, VTOP2, VBOT1, and VBOT2) for remote controlling of non-DiSEqC LNBs.
When the regulator blocks are active (EN1 and EN2 = HIGH, and VSPEN1 and VSPEN2 = HIGH), the VBOT1 and VBOT2 bits and the SELVTOP1 and SELVTOP2 pins will control the output between 13V and 14V and the VTOP1 and VTOP2 and the SEL VT OP1 and SELVTOP2 pins will control the output between 18V and 19V.
2
C logic to be between 13V and 14V or
Output Timing
The output voltage rise and fall times can be set by an the external capacitor on the TCAP1 and TCAP2 pins. The output rise and fall times is given by Equation 1:
270()t
---------------- -
C
=
ΔV
where:
• C is the TCAP value in nF
• t is the required slew rate in ms, and
ΔV is the differential transition voltage from low output voltage range to the high output range in Volts.
Rise and fall time will typically be the same. The maximum recommended value for TCAP1 and TCAP2
would be the base on the maximum transition time allowed in the system application. Too small a value of TCAP1 and TCAP2 can cause high peak currents in the boost circuit. For example, a 10V/ms slew on a 80µF VSW capacitor with an inductor of 15µH can cause a peak inductor current of approximately 2.3A.
(EQ. 1)
10
FN9190.2
August 10, 2007
ISL6422
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Current Limiting
The dynamic back current limit block has five thresholds that can be selected by the following bits of the SR.
• ISEL1H and ISEL2H
• ISEL1L and ISEL2L
• ISEL1R and ISEL2R See Table 8 and Table 9 for threshold selection using these
bits. The DCL1 and DCL2 bits have to be set to low for this mode of operation. In this mode, the overcurrent protection circuit works dynamically 23µs after an overload is detected, and the output is shutdown for a time t Simultaneously, the OLF1 or OLF2 bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time t device output will be current limited to a 990mA typ level. If the overload is still detected, the protection circuit will cycle again through t no overload is detected, normal operation is resumed and the OLF1 or OLF2 bit is reset to LOW. Typical t time is 920ms as determined by an internal timer. This dynamic operation can greatly reduce the po wer dissipation in a short circuit condition, still ensuring excellent power-on start-up in most conditions.
However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (DCL = HIGH) and then switching to the dynamic mode (DCL = LOW) after a chosen amount of time. When in static mode, the OLF1 or OLF2 bit goes HIGH when the peak current sense threshold is reached and returns LOW when the overload condition is cleared. The OLF1, OLF2, BCF1, and BCF2 bits will be LOW at the end of initial power-on soft-start. In the static mode the output current through the linears is limited to 990mA typ.
When a 19.3V line is connected onto a VOUT1 or VOUT2 pin that has been set to 13.3V, the linear will then enter a dynamic back current limit state. When a dynamic back current limit of greater that 125mA typ is sensed at the lower FET of the linear for a period greater that 100µs, the output is disabled for a period of 5ms and the BCF1 and BCF2 bits are set. If the 19.3V remains connected, the output will cycle through the ON = 100µs/OFF = 5ms. The output will recover when the fault is removed.
and tON. At the end of a full tON, in which
OFF
= 20ms. During tON, the
ON
, typically 900ms.
OFF
ON+tOFF
Thermal Protection
This IC is protected against overheating. When the junction temperature exceeds +150°C (typical), the step-up converter and the linear regulator are shut off and the OTF bit of the SR is set HIGH. Normal operation is resumed and the OTF bit is reset LOW when the junction is cooled down to +130°C (typical).
The FLT an over temperature, overcurrent or backwards overcurrent fault is detected by the LNB controller or when both channels are disabled by the I Should the I to ground), it is designed to power up with all control bits set to 0 (particularly the EN1 and EN2 bits). This prevents the device from coming back up in a state not desired by the host controller. If the host controller sees a FLT should read the I When it desires one or both to be high, it should re-write the
2
I
pin serves as an interrupt for the processor when
2
2
C lose power (for example by shorting BYP pin
C to the desired state.
C EN1 and EN2 bits being set low.
2
C bits and find both EN1 and EN2 bits low.
low, it
External Output Voltage Selection
The output voltage can be selected by the I2C bus. Additionally, the package offers two pins (SELVTOP1 and SELVTOP2) for independent 13 through 19V output voltage selection.
TABLE 1.
VSPEN1, VSPEN2
0 X 0 0 13.3V 0 X 1 0 14.3V 0 0 X 1 18.3V 0 1 X 1 19.3V 1 0 0 X 13.3V 1 0 1 X 14.3V 1 1 0 X 18.3V 1 1 1 X 19.3V
VTOP1,
VTOP2
VBOT1,
VBOT2
SELVTOP1,
SELVTOP2
VOUT1,
VOUT12
I2C Bus Interface for ISL6422
(Refer to Phillips I2C Specification, Rev. 2.1) Data transmission from the main microprocessor to the
ISL6422 and vice versa takes place through the two-wire I bus interface, consisting of the two lines SDA and SCL. Both SDA and SCL are bidirectional lines. They are connected to a positive supply voltage via a pull-up resistor. (Pull-up resistors to positive supply voltage must be externally connected). When the bus is free, both lines are HIGH. The output stages of ISL6422 will have an open drain/open collector in order to perform the wired-AND function. Data on the I transferred up to 100kbps in the standard mode or up to 400kbps in the fast mode. The level of logic “0” and logic “1” depends on the value of V Specifications” table on page5. One clock pulse is generated for each data bit transferred.
as per the “Electrical
DD
2
C bus can be
2
C
11
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August 10, 2007
ISL6422
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Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can change only when the clock signal on the SCL line is LOW. Refer to Figure 4.
SDA
SCL
DATA LINE
STABLE
DATA VALID
FIGURE 4. DATA VALIDITY
CHANGE OF DATA
ALLOWED
START and STOP Co nditions
As shown in Figure 5, the START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition.
SDA
The ISL6422 will not generate the acknowledge if the POWER OK signal from the UVLO is LOW.
SCL
8
9
ACKNOWLEDGE
FROM SLAVE
SDA
START
1
MSB
FIGURE 6. ACKNOWLEDGE ON THE I2C BUS
2
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the microprocessor can use a simpler transmission; it waits one clock pulse without checking the slave acknowledging and sends the new data. Although, this approach is less protected from error and decreases the noise immunity.
ISL6422 Software Description
Interface Protocol
The interface protocol is comprised of the following, as shown in Table 2:
• Start condition (S)
SCL
SP
START
CONDITION
FIGURE 5. START AND STOP WAVEFORMS
STOP
CONDITION
Byte Format
Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 6). The peripheral that acknowledges has to pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. (Set-up and hold times must also be taken into account).
The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer.
• Chip address byte (MSB on left; the LSB bit determines read (1) or write (0) transmission) (the assigned I
2
C slave
address for the ISL6422 is 0001 00XX)
• Sequence of data (1 byte + Acknowledge)
• Stop condition (P)
TABLE 2. INTERFACE PROTOCOL
S0001000R/WACK Data (8 bits) ACKP
System Register Format
• R, W = Read and Write bit
• R = Read-only bit
• X = Unused
All bits reset to 0 at Power-On
TABLE 3. STATUS REGISTER 1 (SR1)
R, W R, W R, W R R R R R
SR1H SR1M SR1L OTF CABF1 OUVF1 OLF1 BCF1
TABLE 4. TONE REGISTER 2 (SR2)
R, W R, W R, W R, W R, W R, W R, W R, W
SR2H SR2M SR2L ENT1 MSEL1 TTH1 X X
TABLE 5. COMMAND REGISTER 3 (SR3)
R, W R, W R, W R, W R, W R, W R, W R, W
SR3H SR3M SR3L DCL1 VSPEN1 ISEL1RXISEL1H ISEL1L
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August 10, 2007
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TABLE 6. CONTROL REGISTER 4 (SR4)
R, W R, W R, W R, W R, W R, W R, W R, W
SR4H SR4M SR4L EN1 X X VTOP1 VBOT1
TABLE 7. STATUS REGISTER 5 (SR5)
R, WR, WR, WXRRRR
SR5H SR5M SR5L X CABF2 OUVF2 OLF2 BCF2
TABLE 8. TONE REGISTER 6 (SR6)
R, W R, W R, W R, W R, W R, W R, W R, W
SR6H SR6M SR6L ENT2 MSEL2 TTH2 X X
R, W R, W R, W R, W R, W R, W R, W R, W
SR7H SR7M SR7L DCL2 VSPEN2 ISEL2R ISEL2H ISEL2L
R, W R, W R, W R, W R, W R, W R, W R, W
SR8H SR8M SR8L EN2 X X VTOP2 VBOT2
Transmitted Data (I
When the R/W bit in the chip is set to 0, the main microprocessor can write on the system registers (SR1 through SR8) of the ISL6422 via I
TABLE 9. COMMAND REGISTER 7 (SR7)
TABLE 10. CONTROL REGISTER 8 (SR8)
2
C bus WRITE mode)
written by the microprocessor as shown in the following. The spare bits of registers can be used for other functions.
TABLE 11. STATUS REGISTER SR1 CONFIGURATION
SR1H SR1M SR1L OTF CABF1 OUVF1 OLF1 BCF1 FUNCTION
000XXXXXSR1 is selected 000XXX0XI 000XXX1XI 000XXXX0I 000XXXX1I 000XX0XXV 000XX1XXV 0 0 0 X 0 X X X Cable is connected, I 0 0 0 X 1 X X X Cable is open, I 0000XXXXT 0001XXXXT
NOTE: X indicates “Read Only” and is a “Don’t Care” for the Write mode.
set limit, Normal Operation
OUT
>Static/Dynamic Limiting Mode/Power blocks disabled
OUT
set limit, Normal Operation
OBCK
>Dynamic Limiting Mode/Power blocks disabled
OBCK
IN/VOUT IN/VOUT
J J
within specified range is not within specified range
is >20mA
OUT
<2mA
OUT
≤+130°C, Normal operation >+150°C, Power blocks disabled
2
C bus. These will be
TABLE 12. TONE REGISTER SR2 CONFIGURATION
SR2H SR2M SR2L ENT1 MSEL1 TTH1 X X FUNCTION
001XXXXXSR2 is selected 00100XXXInternal Tone = 22kHz, modulated by EXTM1, t 00101XXXExt 22k modulated input, tr, tf = 10µs typ 00110XXXInternal Tone = 22kHz, modulated by the ENT1 bit, t 0 0 1 X X 0 X X TXT = 0; Decoder Rx threshold is set at 200mV max 0 0 1 X X 1 X X TXT = 0; Decoder Tx threshold is set at 400mV min
NOTE: X is a “Don’t Care” for the Write mode.
13
, tf = 10µs typ
r
, tf = 10µs typ
r
August 10, 2007
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ISL6422
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TABLE 13. COMMAND REGISTER SR3 CONFIGURATION
SR3H SR3M SR3L DCL1 VSPEN1 ISEL1R ISEL1H ISEL1L FUNCTION
0 1 0 X X X X X SR3 is selected 0100X0XXI 0100X100I 0100X101I 0100X110I 0100X111I 0 1 0 1 X X X X Dynamic current limit NOT selected 0 1 0 0 X X X Dynamic current limit selected 0 1 0 X 0 X X X SELVTOP H/W pin Enabled 0 1 0 X 1 X X X SELVTOP H/W pin Disabled
NOTE: X is a “Don’t Care” for the Write mode.
TABLE 14. CONTROL REGISTER SR4 CONFIGURATION
SR4H SR4M SR4L EN1 X X VTOP1 VBOT1 FUNCTION
0111XX00SR4 is selected 0 1 1 1 X X 0 0 VSPEN1 = SELVTOP1 = 0, V
0 1 1 1 X X 0 1 VSPEN1 = SELVTOP1 = 0, V
0 1 1 1 X X 1 0 VSPEN1 = SELVTOP1 = 0, V
0 1 1 1 X X 1 1 VSPEN1 = SELVTOP1 = 0, V
0 1 1 1 X X 0 0 VSPEN1 = 0, SELVTOP1 = 1, V
0 1 1 1 X X 0 1 VSPEN1 = 0, SELVTOP1 = 1, V
0 1 1 1 X X 1 0 VSPEN1 = 0, SELVTOP1 = 1, V
0 1 1 1 X X 1 1 VSPEN1 = 0, SELVTOP1 = 1, V
0 1 1 1 X X 0 0 VSPEN1 = 1, SELVTOP1 = X, V
0 1 1 1 X X 0 1 VSPEN1 = 1, SELVTOP1 = X, V
0 1 1 1 X X 1 0 VSPEN1 = 1, SELVTOP1 = X, V
0 1 1 1 X X 1 1 VSPEN1 = 1, SELVTOP1 = X, V
0110XXXXPWM and Linear for Channel 1 disabled
NOTE: X is a “Don’t Care” for the Write mode.
= 275mA maximum
OUT1
= 350mA maximum
OUT1
= 515mA maximum
OUT1
= 635mA maximum
OUT1
= 800mA maximum
OUT1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
= 13V + V
= 14V + V
= 13V + V
= 14V + V
= 18V + V
= 18V + V
= 19V + V
= 19V + V
= 13V + V
= 14V + V
= 18V + V
= 19V + V
V
V
V
V
V
V
V
V
V
V
V
V
OUT1
DROP
OUT1
DROP
OUT1
DROP
OUT1
DROP
OUT1
DROP
OUT1
DROP
OUT1
DROP
OUT1
DROP
OUT1
DROP
OUT1
DROP
OUT1
DROP
OUT1
DROP
= 13V,
= 14V,
= 13V,
= 14V,
= 18V,
= 18V,
= 19V,
= 19V,
= 13V,
= 14V,
= 18V,
= 19V,
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TABLE 15. STATUS REGISTER SR5 CONFIGURATION
SR5H SR5M SR5L CABF2 OUVF2 OLF2 BCF2 FUNCTION
1 0 0 X X X X X SR5 is selected 100XXX0XI 100XXX1XI 100XXXX0I 100XXXX1I 100XX0XXV 100XX1XXV 1 0 0 X 0 X X X Cable is connected, I 1 0 0 X 1 X X X Cable is open, I
NOTE: X indicates “Read Only” state.
TABLE 16. TONE REGISTER SR6 CONFIGURATION
SR6H SR6M SR6L ENT2 MSEL2 TTH2 X X FUNCTION
1 0 1 X X X X X SR2 is selected 1 0 1 0 0 X X X Int Tone = 22kHz, modulated by EXTM2, T 1 0 1 0 1 X X X Ext 22k modulated input, T 1 0 1 1 0 X X X Int Tone = 22kHz, modulated by ENT2 bit, T 1 0 1 X X 0 X X TXT2 = 0; Decoder Rx threshold is set at 200mV max 1 0 1 X X 1 X X TXT2 = 0; Decoder Tx threshold is set at 400mV min
NOTE: X is a “Don’t Care” for the Write mode.
set limit, Normal Operation
OUT
> Static/Dynamic Limiting Mode/Power blocks disabled
OUT
set limit, Normal Operation
OBCK
> Dynamic Limiting Mode/Power blocks disabled
OBCK
IN/VOUT IN/VOUT
within specified range is not within specified range
is >20mA
OUT
<2mA
OUT
, Tf = 10µs typ
r
r
, Tf = 10µs typ
, Tf = 10µs typ
r
TABLE 17. COMMAND REGISTER SR7 CONFIGURATION
SR7H SR7M SR7L DCL2 VSPEN2 ISEL2R ISEL2H ISEL2L FUNCTION
1 1 0 X X X X X SR7 is selected 1100X0XXI 1100X100I 1100X101I 1100X110I 1100X111I 1 1 0 1 X X X X Dynamic current limit NOT selected 1 1 0 0 X X X X Dynamic current limit selected 1 1 0 X 0 X X X SELVTOP H/W pin Enabled 1 1 0 X 1 X X X SELVTOP H/W pin Disabled
NOTE: X is a “Don’t Care” for the Write mode.
1 = 275mA max.
OUT
1 = 350mA max.
OUT
1 = 515mA max.
OUT
1 = 635mA max.
OUT
1 = 800mA max.
OUT
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TABLE 18. CONTROL REGISTER SR8 CONFIGURATION
SR8H SR8M SR8L EN2 X X VTOP2 VBOT2 FUNCTION
1 1 1 1 X X 0 0 SR4 is selected 1 1 1 1 X X 0 0 VSPEN2 = SELVTOP2 = 0, V
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
= 13V + V
= 14V + V
= 13V + V
= 14V + V
= 18V + V
= 18V + V
= 19V + V
= 19V + V
= 13V + V
= 14V + V
= 18V + V
= 19V + V
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
V
1 1 1 1 X X 0 1 VSPEN2 = SELVTOP2 = 0, V
V
1 1 1 1 X X 1 0 VSPEN2 = SELVTOP2 = 0, V
V
1 1 1 1 X X 1 1 VSPEN2 = SELVTOP2 = 0, V
V
1 1 1 1 X X 0 0 VSPEN2 = 0,SELVTOP2 = 1, V
V
1 1 1 1 X X 0 1 VSPEN2 = 0, SELVTOP2 = 1, V
V
1 1 1 1 X X 1 0 VSPEN2 = 0, SELVTOP2 = 1, V
V
1 1 1 1 X X 1 1 VSPEN2 = 0, SELVTOP2 = 1, V
V
1 1 1 1 X X 0 0 VSPEN2 = 1, SELVTOP2 = X, V
V
1 1 1 1 X X 0 1 VSPEN2 = 1, SELVTOP2 = X, V
V
1 1 1 1 X X 1 0 VSPEN2 = 1, SELVTOP2 = X, V
V
1 1 1 1 X X 1 1 VSPEN2 = 1, SELVTOP2 = X, V
V
1 1 1 0 X X X X PWM and Linear for channel 1 disabled
NOTE: X is a “Don’t Care” for the Write mode.
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
= 13V,
= 14V,
= 13V,
= 14V,
= 18V,
= 18V,
= 19V,
= 19V,
= 13V,
= 14V,
= 18V,
= 19V,
Received Data (I
2
C bus READ MODE)
The ISL6422 can provide to the master a copy of the system register information via the I
2
C bus in read mode. The read mode is master-activated by sending the chip address with the R/W bit set to 1. At the following master-generated clock bits, the ISL6422 issues a byte on the SDA data bus line (MSB transmitted first).
At the ninth clock bit, the MCU master can:
• Acknowledge the reception, thus starting the transmission
of another byte from the ISL6422.
• Not acknowledge, thus stopping the read mode
communication.
While the whole register is read back by the microprocessor, the following read-only bits convey diagnostic information about the ISL6422.
• OUC1 and OUC2 (Over or Undercurrent bits)
• UV1 and UV2 (Over or Undervoltage bits)
• TPR1 and TPR2 (Tone present bits)
• OTF (Over-temperature fault bit).
Power–On I2C Interface Reset
The I2C interface built into the ISL6422 is automatically reset at power-on. The I logic signal from the UVLO circuit. This signal will go HIGH when chip power is OK. As long as this signal is LOW, the interface will not respond to any I system register SR1 and SR2 are initialized to all zeros, thus keeping the power blocks disabled. Once the V above UVLO, the POWER OK signal given to the I interface block will be HIGH, the I operative and the SRs can be configured by the main microprocessor. About 400mV of hysteresis is provided in the UVLO threshold to avoid false triggering of the power-on reset circuit. (I the same time as (or later than) all other I PWM becomes valid).
2
C interface block will receive a Power OK
2
C commands and the
rises
CC
2
2
C interface becomes
2
C comes up with EN = 0; EN goes HIGH at
2
C data for that
C
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ADDR0 and ADDR1 Pins
Connecting either ADDR0 or ADDR1 to GND, the chip I2C interface address is 0001000, but it is possible to choose between four different addresses simply by setting the logic as indicated in Table 19.
TABLE 19. ADDRESS PIN CHARACTERISTICS
V
ADDR
V
-1
ADDR
“0001000”
V
-2
ADDR
“0001001”
-3
V
ADDR
“0001010”
-4
V
ADDR
“0001011”
ADDR1 ADDR0
00
01
10
11
I2C Electrical Characteristics
TABLE 20. I2C SPECIFICATIONS
PARAMETER TEST CONDITION MIN TYP MAX
Input Logic High, VIH SDA, SCL 2.0V Input Logic Low, VIL SDA, SCL 0.8V Input Logic Current, IIL SDA, SCL;
0.4V < V Input Hysterisis SDA, SCL 165mV 200mV 235mV SCL Clock Frequency 0 100kHz 400kHz
DD
< 3.3V
10μA
I2C Bit Description
TABLE 21.
BIT NAME DESCRIPTION
EN1 and EN2 ENable Output for Channels 1 and 2 VTOP1 and VTOP2 Voltage TOP Select (that is, 18V/19V for Channels 1 and 2) VBOT1 and VTOP2 Voltage BOTtom Select (that is, 13V/14V for Channels 1 and 2) ENT1 and ENT2 ENable Tone for Channels 1 and 2 MSEL1 and MSEL2 Modulation SELect for Channels 1 and 2 TFR1 and TFR2 Tone Frequency and Rise time select for Channels 1 and 2 DCL1 and DCL2 Dynamic Current Limit select for Channels 1 and 2 VSPEN1 and VSPEN2 Voltage Select Pin ENable for Channels 1 and 2 ISEL1H and ISEL2H, ISEL1L and
ISEL2L, ISEL1R and ISEL2R OTF Over-Temperature Fault bit CABF1, CABF2 CABle Fault or open status bit for Channels 1 and 2 OUVF1, OUVF2 Over and Undervoltage Fault status bit for Channels 1 and 2 OLF1, OLF2 Over Load Fault status bit for Channels 1 and 2 BCF1, BCF2 Backward Current Fault Bit for Channels 1 and 2 TTH1, TTH2 Tone THreshold is the OR of the signal pin TXT1 or TXT2
Current limit “I” SELect high and low bits for Channels 1 and 2
17
FN9190.2
August 10, 2007
Package Outline Drawing
www.BDTIC.com/Intersil
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06
6.00
6
PIN 1
INDEX AREA
ISL6422
A
B
6.00
4X
4.5
0.50
36X
31
30
40
6
PIN #1 INDEX AREA
1
4 . 10 ± 0 . 15
(4X)
( 5 . 8 TYP )
( 4 . 10 )
0.15
TOP VIEW
TYPICAL RECOMMENDED LAND PATTERN
0 . 90 ± 0 . 1
( 36X 0 . 5 )
( 40X 0 . 23 )
( 40X 0 . 6 )
21
20
40X 0 . 4 ± 0 . 1
BOTTOM VIEW
SIDE VIEW
C
0 . 2 REF
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
5
10
4
0 . 23 +0 . 07 / -0 . 05
SEE DETAIL "X"
C
0.10
BASE PLANE
SEATING PLANE
B0.1011MAC
C
0.08
C
NOTES:
Dimensions are in millimeters.1. Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
2.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension b applies to the metallized terminal and is measured
4. between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
The configuration of the pin #1 identifier is optional, but must be
6. located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
18
FN9190.2
August 10, 2007
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Thin Shrink Small Outline Exposed Pad Plastic Packages (EPTSSOP)
N
INDEX AREA
123
TOP VIEW
0.05(0.002)
-A­D
e
b
0.10(0.004) C AM BS
123
N
P
BOTTOM VIEW
E1
E
-B-
SEATING PLANE
A
-C-
A1
M
P1
0.25(0.010) BM M
GAUGE PLANE
0.25
0.010
α
0.10(0.004)
A2
M38.173B
38 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.047 - 1.20 -
L
c
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0106 0.17 0.27 9
c 0.0035 0.0079 0.09 0.20 -
D 0.378 0.386 9.60 9.80 3
E1 0.169 0.177 4.30 4.50 4
e 0.0197 BSC 0.500 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N38 387
o
α
P - 0.256 - 6.5 11
P1 -0.126-3.2 11
NOTES:
1. These package dimensions are within allowable dimensions of JEDEC MO-153-BD-1, Issue F.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact. (Angles in degrees)
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced variations. Values shown are maximum size of exposed pad within lead count and body size.
0
o
8
o
0
o
8
NOTESMIN MAX MIN MAX
-
Rev. 0 9/06
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
FN9190.2
August 10, 2007
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