intersil ISL6421A DATA SHEET

®

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ISL6421A

Data Sheet

Single Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-top Box Designs

The ISL6421A is a highly integrated solution for providing
power and control signals from advanced satellite set-top
box (STB) modules to the low noise block (LNB). The
internal architecture of this device contains a current-mode
boost PWM and a low-noise linear regulator, along with the
circuitry required for I
DiSEqC™ standard control signals to the LNB.

A regulated output voltage is available at the output terminal
(VOUT) to support the operation of the antenna port in
advanced satellite STB applications. The regulated output
may be set to either 13V or 18V by use of the voltage select
command bit (VSEL) through the I
compensate for the voltage drop in the coaxial cable, the
voltage may be increased by 1V with the line length
compensation bit (LLC) feature. The device can be put into a
standby mode by means of the enable bit (EN), this disables
the PWM and Linear regulator combination and helps
conserve power.

The input to the linear regulator is derived from the current
mode boost converter, such that the required voltage is the
sum of the output voltage and the linear regulator drop (1.0V
typical). This ensures that the power dissipation is minimized
and maintains a constant voltage drop across the linear pass
element, while permitting an adequate voltage range for tone
injection.

The device is capable of providing 450mA (typical). The
overcurrent limit is either digitally or resistor programmable.

2

C device interfacing and for providing

2

C bus. Additionally, to

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Features

• Switch-Mode Power Converter for Lowest Dissipation

- Boost PWM with >92% Efficiency

- Selectable 13V or 18V Outputs

- Digital Cable Length Compensation (1V)

- Vsw tracks Vout ensures low dissipation

2

C Compatible Interface for Remote Device Control

•I

- Registered Slave Address 0001 00XX

- Fully Functional 3.3V, 5V Operation up to 400kHz

• Built-In Tone Oscillator Factory Trimmed to 22kHz

- Facilitates DiSEqC™ (EUTELSAT) Encoding

- External Modulation input DSQIN

• Internal Over Temperature Protection and Diagnostics

• Internal Overload and Over Temperature Flags
(Visible on I

2

C)

• Output Back-Bias Protection to 24V

• LNB Short-Circuit Protection and Diagnostics

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

No Leads - Product Outline

- Near Chip-Scale Package Footprint

• External Pins to Select 13V/18V Options

• Pb-Free Available (RoHS Compliant)

Applications

• LNB Power Supply and Control for Satellite Set-Top Box

Pinout

ISL6421A (QFN) TOP VIEW

References

• Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available
on the Intersil website, www.intersil.com

Ordering Information

PART

NUMBER*

ISL6421AER ISL6421AER -20 to 85 32 Ld 5x5 QFN L32.5x5

ISL6421AERZ
(Note)

*Add -T for tape and reel package.

NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PGND

NC

SGND

SEL18V

NC

BYPASS

PGND

GATE

NC

COMP

NC

VSW

NC

SDA

NC

NC

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

9 10111213141516

FB

CS

VCC

NC

1

CPVOUT

ADDR

SCL CPSWIN

24

CPSWOUT

23

NC

22

NC

21

NC

20

AGND

19

VOUT

18

DSQIN

17

TCAP

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

TEMP.

PART

MARKING

ISL6421AERZ -20 to 85 32 Ld 5x5 QFN

Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved

RANGE

(°C) PACKAGE

(Pb-free)

PKG.

DWG. #

L32.5x5

Block Diagram

www.BDTIC.com/Intersil

COUNTER

OVERCURRENT

PROTECTION

LOGIC SCHEME 1

SEL18V

OLF

DCL

PWM

ILIM

LOGIC

Q

S

∑

SLOPE

COMPENSATION

2

GATE

PGND

CS

CS

COMP

FB

VSW

VOUT

AMP

CLK

OC

+

-

­+

VREF

BAND GAP

REF VOLTAGE

REF

VOLTAGE

ADJ

+

-

ISEL

EN

ENT

OTF

BGV

OLF

INTERFACE

LLC VSEL

TONE

INJ

CKT

OTF

I2C

CLK

220kHz

÷ 10 AND

WAVE SHAPING

THERMAL

SHUTDOWN

SDA

ADDR

SCL

OSC.

22kHz
TONE

SDA

ADDR

SCL

DCL

ISL6421A

ENT

DSQIN

VCC

SGND

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ON CHIP

LINEAR

UVLO

POR

SOFT-START

BYPASS

INT 5V
SOFT-START

EN

AGND

TCAP

CHARGE PUMP

CPSWOUT

CPVOUT

CPSWIN

Typical Application Schematic

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3

ISL6421A

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NOTE: SGND and PGND to be shorted as close to U1 at layout

ISL6421A

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V

Logic Input Voltage Range (SDA, SCL, ENT) . . . . . . . . -0.5V to 7V

Output Current . . . . . . . . . . . . . . . . . . . . Externally/Internally Limited

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

JA

Tech Brief TB379.

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance (Notes 1, 2) θJA (°C/W) θJC (°C/W)

QFN Package. . . . . . . . . . . . . . . . . . . . 35 6

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . . -40°C to 150°C

For recommended soldering conditions, see Tech Brief TB389.

NOTE: The device junction temperature should be kept below
150°C. Thermal shut-down circuitry turns off the device if junction
temperature exceeds +150°C typically.

Electrical Specifications VCC = 12V, T

ENT = L, DCL = L, DSQIN = L, Iout = 12mA, unless otherwise noted. See software description section for I
access to the system.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Operating Supply Voltage Range 8 12 14 V

Standby Supply Current EN = L - 1.5 3.0 mA

Supply Current I

UNDERVOLTAGE LOCKOUT

Start Threshold 7.5 - 7.95 V

Stop Threshold 7.0 - 7.55 V

Start to Stop Hysteresis 350 400 500 mV

SOFT-START

COMP Rise Time (Note 3) (Note 5) - 1024 - Cycles

OUTPUT VOLTAGE

Output Voltage (Note 4) V

Line Regulation DV

Load Regulation DV

Dynamic Output Current Limiting I

Dynamic Overload Protection Off Time T

Dynamic Overload Protection On Time T

Output Backward Current I

22kHz TONE

Tone Frequency f

Tone Amplitude V

Tone Duty Cycle dc

Tone Rise or Fall Time T

= -20°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. EN = H, LLC = L,

A

IN

OUT

V

OUT

V

OUT

V

OOU

OUT

OUTIO

MAX

OFF

ON

OBK

tone

tone

tone

, T

r

EN = LLC = VSEL = ENT = H, No Load - 4.0 8.0 mA

VSEL = L, LLC = L 12.74 13.0 13.26 V

VSEL = L, LLC = H 13.72 14.0 14.28 V

VSEL = H, LLC = L 17.64 18.0 18.36 V

VSEL = H, LLC = H 18.62 19.0 19.38 V

VIN = 8V to 14V; V

= 8V to 14V; V

V

IN

= 12mA to 450mA - 50 80 mV

DCL = L 500 - 625 mA

DCL = L, Output Shorted (Note 5) - 900 - ms

EN = 0; V

ENT = H 20.0 22.0 24.0 kHz

ENT = H 500 680 900 mV

ENT = H 405060 %

ENT = H 5 8 14 µs

f

= 24V - 2.0 3.0 mA

OBK

= 13V - 4.0 40.0 mV

OUT

= 18V - 4.0 60.0 mV

OUT

-20- ms

2

C

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Electrical Specifications VCC = 12V, T

ENT = L, DCL = L, DSQIN = L, Iout = 12mA, unless otherwise noted. See software description section for I
access to the system. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

LINEAR REGULATOR

Drop-out Voltage Iout = 450mA (Note 5) - 1.2 - V

DSQIN PIN

DSQIN pin logic Low - - 1.5V V

DSQIN pin Logic HIGH 3.5 - - V

DSQIN pin Input Current -1-µA

CURRENT SENSE

Input Bias Current I

Overcurrent Threshold Static current mode, DCL = H 325 400 500 mV

ERROR AMPLIFIER

Open Loop Voltage Gain A

Gain Bandwidth Product

PWM

Maximum Duty Cycle 90 93 - %

Minimum Pulse Width (Note 5) - 20 - ns

OSCILLATOR

Oscillator Frequency f

THERMAL PROTECTION

Thermal Shutdown

Temperature Shutdown Threshold (Note 5) - 150 - °C

Temperature Shutdown Hysteresis (Note 5) - 20 - °C

NOTES:

3. Internal digital soft-start.

4. Voltage programming signals VSEL and LLC are implemented via the I
IO1 = IO2 = 500mA.

5. Guaranteed by design.

= -20°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. EN = H, LLC = L,

A

BIAS

OL

GBP

o

(Note 5) 70 88 - dB

(Note 5) 10 - - MHz

Fixed at (10)(f

) 200 220 240 kHz

tone

2

C bus.

- 700 - nA

2

C

Functional Pin Description

SYMBOL FUNCTION

2

SDA Bidirectional data from/to I

2

SCL Clock from I

VSW Input of the linear post-regulator.

PGND Dedicated ground for the output gate driver of the PWM.

CS Current sense input; connect Rsc at this pin for desired overcurrent value for the PWM.

SGND Small signal ground for the IC.

AGND Analog ground for the IC.

TCAP Capacitor for setting rise and fall time of the output of the LNB. Use a capacitor value of 1µF or higher.

BYPASS Bypass capacitor for internal 5V.

DSQIN When HIGH this pin enables the internal 22kHz modulation for the LNB, Use this pin for tone enable function for the

LNB.

C bus.

C bus.

5

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Functional Pin Description (Continued)

SYMBOL FUNCTION

VCC Main power supply to the chip.

GATE This is the device output of the PWM. This high current driver output is capable of driving the gate of a power FET.

This output is actively held low when Vcc is below the UVLO threshold.

VOUT Output voltage for the LNB.

ADDRESS Address pin to select two different addresses per voltage level at this pin.

COMP Error amp output used for compensation.

FB Feedback pin for the PWM.

CPVOUT, CPSWIN,

CPSWOUT

SEL18V When connected HIGH, this pin will change the output of the PWM to 18V. Only available on the QFN package option.

Charge pump connections.

Functional Description

The ISL6421A is a single output voltage regulator controlled

2

by an I
satellite set-top box and personal video recorder
applications. Both supply and control voltage outputs for a
low noise block (LNB) are available simultaneously in any
output configuration. The device utilizes a built-in DC/DC
step-converter which, from a single supply source ranging
from 8V to 14V, generates the voltage that enables the linear
post-regulator to work with a minimum of dissipated power.
An undervoltage lockout circuit disables the circuit when
V

DiSEqC Encoding

The internal oscillator is factory-trimmed to provide a tone of
22kHz in accordance with DiSeqC standards. No further
adjustment is required. The 22kHz oscillator can be
controlled either by the I
dedicated pin (DSQIN) that allows immediate DiSEqC data
encoding for the LNB. All the functions of this IC are
controlled via the I
(SR). The same registers can be read back, and two bits will
report the diagnostic status. The internal oscillator operates
the converters at ten times the tone frequency. The device
offers full I
400kHz operation.

If the Tone Enable (ENT) bit is set LOW through I
the DSQIN terminal activates the internal tone signal,
modulating the dc output with a 0.3V, 22kHz, symmetrical
waveform. The presence of this signal usually gives the LNB
information about the band to be received.

Burst coding of the 22kHz tone can be accomplished due to
the fast response of the DSQIN input and rapid tone
response. This allows implementation of the DiSEqC
(EUTELSAT) protocols.

When the ENT bit is set HIGH, a continuous 22kHz tone is
generated regardless of the DSQIN pin logic status. The

C bus, making it an ideal choice for advanced

drops below a fixed threshold (7.5V typ).

CC

2

C interface (ENT bit) or by a

2

C bus by writing to the system registers

2

C compatible functionality, 3.3V or 5V, and up to

2

C, then

ENT bit must be set LOW when the DSQIN pin is used for
DiSEqC encoding.

Linear Regulator

The output linear regulator will sink and source current. This
feature allows full modulation capability into capacitive loads
as high as 0.25µF. In order to minimize the power
dissipation, the output voltage of the internal step-up
converter is adjusted to allow the linear regulator to work at
minimum dropout.

When the device is put in the shutdown mode (EN = LOW),
the PWM power block is disabled. When the regulator block
is active (EN = HIGH), the output can be logic controlled to
be 13V or 18V (typical) by means of the VSEL bit (Voltage
Select) for remote controlling of non-DiSEqC LNBs.
Additionally, it is possible to increment by 1V (typical) the
selected voltage value to compensate for the excess voltage
drop along the coaxial cable (LLC bit HIGH).

Output Timing

The programmed output voltage rise and fall times can be
set by an external capacitor. The output rise and fall times
will be approximately 3400 times the TCAP value. For the
recommended range of 0.47µF to 2.2µF, the rise and fall
time would be 1.6ms to 7.6ms. Using a 0.47µF capacitor
insures the PWM stays below its overcurrent threshold when
charging a 120µF VSW filter cap during the worst case 13V
to 19V transition. A typical value of 1.0µF is recommended.
This feature affects the programmed voltage rise and fall
times.

Current Limiting

The current limiting block can operate either statically
(simple current clamp) or dynamically. The threshold is
between 500mA and 625mA. When the DCL (Dynamic
Current Limiting) bit is set to LOW, the overcurrent protection
circuit works dynamically. That is, as soon as an overload is
detected, the output is shut down for a time T

, typically

OFF

6

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900ms. Simultaneously the overload flag (OLF) bit of the
system register is set to HIGH. After this time has elapsed,
the output is resumed for a time T

= 20ms. During TON,

ON

the device output will be current limited to between 500mA
and 625mA. At the end of T
detected, the protection circuit will cycle again through T
and T

. At the end of a full TON, during which no overload

ON

, if the overload is still

ON

OFF

is detected, normal operation is resumed and the OLF bit is
reset to LOW. Typical T

ON

+ T

time is 920ms as

OFF

determined by an internal timer. This dynamic operation can
greatly reduce the power dissipation in a short circuit
condition, still ensuring excellent power-on start-up in most
conditions.

However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up,
when the dynamic protection is chosen. This can be solved
by initiating a power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a chosen amount of time. When in static mode, the OLF bit
goes HIGH when the current clamp limit is reached and
returns LOW when the overload condition is cleared. The
OLF bit will be LOW at the end of initial power-on soft-start.

The static mode limit serves only to limit the peak current
through the switching FET and cannot precisely set an
average current limit. The sense resistor is calculated by the
equation

0.4

=

R

-------- -

SC

I

PK

where I

is the peak current through the FET. This value

PK

should be greater that the normal operating peak current.

I2C Bus Interface for ISL6421A

(Refer to Philips I2C Specification, Rev. 2.1)

Data transmission from the main microprocessor to the
ISL6421A and vice versa takes place through the 2 wires

2

I

C bus interfaces, which consists of the two lines SDA and
SCL. Both SDA and SCL are bidirectional lines, connected
to a positive supply voltage via a pull up resistor. (Pull up
resistors to positive supply voltage must be externally
connected). When the bus is free, both lines are HIGH. The
output stage of ISL6421A will have an open drain/open
collector in order to perform the wired-AND function. Data on

2

the I

C bus can be transferred up to 100kbits/s in the
standard-mode or up to 400kbits/s in the fast-mode. The
level of logic “0” and logic “1” is dependent of associated
value of Vdd as per electrical specification table. One clock
pulse is generated for each data bit transferred.

Data Validity

The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 1.

SDA

SCL

DATA LINE

STABLE

DATA VALID

CHANGE
OF DATA

ALLOWED

Thermal Resistance

This IC is protected against overheating. When the junction
temperature exceeds 150°C (typical), the step-up converter
and the linear regulator are shut off and the overtemp flag
(OTF) bit of the SR is set HIGH. Normal operation is
resumed and the OTF bit is reset LOW, when the junction is
cooled down to 130°C (typical).

External Output Voltage Selection

The output voltage can be selected by the I2C bus.
Additionally, the QFN package offers a pin (SEL18V) for
independent 13V/18V output voltage selection. When using
this pin, the I

2

C bits should be initialized to 13V status.

TAB L E 1 .

2

I

C BITS SEL18V O/P VOLTAGE

13V Low 13V

13V High 18V

FIGURE 1. DATA VALIDITY

START and STOP Conditions

As shown in the Figure 2, START condition is a HIGH to
LOW transition of the SDA line, while SCL is HIGH. The
STOP condition is a LOW to HIGH transition on the SDA
line, while SCL is HIGH. A STOP condition must be sent
before each START condition.

SDA

SCL

SP

START

CONDITION

FIGURE 2. START AND STOP WAVEFORMS

STOP

CONDITION

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Byte Format

Every byte put on the SDA line must be 8-bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).

Acknowledge

The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull the SDA line
down (LOW) during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)

The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6421A will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.

SCL

8

9

ACKNOWLEDGE

FROM SLAVE

SDA

START

1

MSB

FIGURE 3. ACKNOWLEDGE ON THE I2C BUS

2

Transmission Without Acknowledge

Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.

TABLE 2. INTERFACE PROTOCOL

S0001000R/WACK Data (8 bits) ACKP

TABLE 3. SYSTEM REGISTER 1 (SR1)

R, W R, W R, W R, W R, W R, W R, W R

SR1 DCL X ENT LLC VSEL EN OLF

TABLE 4. SYSTEM REGISTER 2 (SR2)

R, W R, W R, W R, W R, W R, W R R

SR2 X X XXXOTFX

System Register Format

• R, W = Read and Write bit

• R = Read-only bit

All bits reset to 0 at Power-On

Transmitted Data (I

When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system registers (SR1/SR2)
of the ISL6421A via I
microprocessor as shown below. The spare bits of SR1/SR2
can be used for other functions.

TABLE 5. SYSTEM REGISTER (SR1 AND SR2)

CONFIGURATION

SR DCL - ENT LLC VSEL EN OLF FUNCTION

0 X 0 0 1 SR1 is selected

0 X 0 0 1 Vout1 = 13V,

0 X 0 1 1 Vout1 = 18V,

0 X 1 0 1 Vout1 = 14V,

0 X 1 1 1 Vout1 = 19V,

2

C bus WRITE mode)

2

C bus. These will be written by the

Vboost1 = 13V + Vdrop

Vboost1 = 18V + Vdrop

Vboost1 = 14V + Vdrop

Vboost1 = 19V + Vdrop

This approach, though, is less protected from error and

0 X 0 1 22kHz tone is controlled

decreases the noise immunity.

ISL6421A Software Description

0 X 1 1 22kHz tone is ON,

Interface Protocol

The interface protocol is comprised of the following, as
shown below in Table 2:

• A start condition (S)

• A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I
address for the ISL6421A is 0001 00XX)

• A sequence of data (1 byte + Acknowledge)

• A stop condition (P)

8

2

C slave

0 1 X 1 Dynamic current limit

0 0 X 1 Dynamic current limit

0 X X X X X 0 PWM and Linear for

SR-----OTF- FUNCTION

1 XXXXX X XSR2 is selected; to read

by the DSQIN pin input

DSQIN pin input is
disabled

NOT selected

selected

channel 1 disabled

OTF flag.

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ISL6421A

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Received Data (I

2

C Bus Read Mode)

The ISL6421A can provide to the master a copy of the
System Register information via the I

2

C bus in read mode.
The read mode is Master activated by sending the chip
address with R/W bit set to 1. At the following Master
generated clock bits, the ISL6421A issues a byte on the
SDA data bus line (MSB transmitted first).

At the ninth clock bit the MCU master can:

• Acknowledge the reception, starting in this way the

transmission of another byte from the ISL6421A.

• Not acknowledge, stopping the read mode

communication.

While the whole register is read back by the microprocessor,
only the two read-only bits, OLF and OTF, convey diagnostic
information about the ISL6421A.

TABLE 6. READING SYSTEM REGISTERS

DCL ISEL ENT LLC VSEL EN OTF OLF FUNCTION

These bits are read as they were
after the last write operation.

0Tj ≤ 130°C, Normal

operation

1 Tj > 150°C, Power

blocks disabled

0 Iout < Imax, Normal

operation

1 Iout > Imax, Overload

protection triggered

Power-On I2C Interface Reset

The I2C interface built into the ISL6421A is automatically
reset at power-on. The I
Power OK logic signal from the UVLO circuit. This signal will
go HIGH when chip power is OK. As long as this signal is
LOW, the interface will not respond to any I
and the system register SR is initialized to all zeros, thus
keeping the power blocks disabled.

Once Vcc rises above the UVLO level, the POWER OK
signal given to the I
interface becomes operative and the SR can be configured
by the main microprocessor. About 400mV of hysteresis is
provided in the UVLO threshold to avoid false triggering of
the Power-On reset circuit.

2

(I

C comes up with EN = 0, EN goes HIGH at the same time
as (or later than) all other I
valid).

2

C interface block will receive a

2

C commands

2

C interface block will be HIGH, the I2C

2

C data for the PWM becomes

ADDRESS Pin

Connecting this pin to GND forces the chip I2C interface
address to 0001000; applying a voltage >2.7V forces the
address to 0001001, as shown below.

TABLE 7. ADDRESS PIN CHARACTERISTICS

Vaddr MIN TYP MAX

Vaddr-1

“0001000”

Vaddr-2

“0001001”

0V - 2.0V

2.7V - 5.0V

I2C Electrical Specifications

TABL E 8 . I2C SPECIFICATIONS

PARAMETER TEST CONDITION MINIMUM TYPICAL MAXIMUM

Input Logic High, VIH SDA, SCL 0.7 x V

Input Logic Low, VIL SDA, SCL 0.3 x V

Input Logic Current, IIL SDA, SCL; 0.4V < Vin < 4.5V 10µA

SCL Clock Frequency 0 100kHz 400kHz

NOTE: V

= 5.0V/3.3V.

DD

DD

DD

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Typical Performance Curves

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ISL6421A

89

88

18.0V

87

86

85

14.0V

84

EFFICIENCY (%)

83

82

81

150.0 450.0250.0

I

OUT

(mA)

550.0350.050.0

89

88

8.0

200mA

450mA

10.0 14.012.0

87

86

85

EFFICIENCY (%)

84

83

FIGURE 4. EFFICIENCY vs LOAD CURRENT FIGURE 5. EFFICIENCY vs VIN

TONE &

VOUT (1V/DIV)

V

(V)

IN

22kHz TONE

(0.1V/DIV)

VOUT

(20mV/DIV)

VPWM

(20mV/DIV)

DSQIN

(1V/DIV)

10µs/DIV

0.2ms/DIV

FIGURE 6. 22kHz TONE FIGURE 7. 22kHz TONE MODULATED BY DSQIN

VOUT

(20mV/DIV)

VPWM

(20mV/DIV)

2µs/DIV

FIGURE 8. RIPPLE VOUT = 14.0V FIGURE 9. RIPPLE VOUT = 18.0V

10

2µs/DIV

FN9167.3

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Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL6421A

VOUT (1V/DIV)

VPWM (1V/DIV)

IOUT (0.2A/DIV)

0.5ms/DIV

FIGURE 10. DYNAMIC RESPONSE VOUT = 19.0V FIGURE 11. DYNAMIC RESPONSE VOUT = 14.0V

VGATE (2V/DIV)

VDRAIN (10V/DIV)

VOUT (1V/DIV)

VPWM (1V/DIV)

IOUT (0.2A/DIV)

0.5ms/DIV

VGATE (2V/DIV)

VDRAIN (10V/DIV)

2µs/DIV

FIGURE 12. GATE AND DRAIN WAVEFORMS VOUT = 19.0V FIGURE 13. GATE AND DRAIN WAVEFORMS VOUT = 14.0V

2µs/DIV

11

FN9167.3

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ISL6421A

www.BDTIC.com/Intersil

Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)

L32.5x5

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 ­A1 - - 0.05 ­A2 - - 1.00 9
A3 0.20 REF 9

b 0.18 0.23 0.30 5,8

D 5.00 BSC ­D1 4.75 BSC 9
D2 2.95 3.10 3.25 7,8

E 5.00 BSC ­E1 4.75 BSC 9
E2 2.95 3.10 3.25 7,8

e 0.50 BSC ­k0.25 - - ­L 0.30 0.40 0.50 8

L1 - - 0.15 10

N322
Nd 8 3
Ne 8 8 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

NOTESMIN NOMINAL MAX

Rev. 1 10/02

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

12

FN9167.3

March 9, 2006