intersil ISL6414 DATA SHEET

®

www.BDTIC.com/Intersil

O

F

D

E

D

N

E

M

T

O

N

IB

Data Sheet August 2004

S

S

O

P

D

O

R

P

M

O

C

E

R

B

U

S

E

L

I

:

T

C

U

W

E

N

R

T

U

T

I

T

S

2

1

4

6

L

S

D
E

G

I

S

E

S

N

ISL6414

FN9128.1

Triple Output, Low-Noise LDO Regulator
with Integrated Reset Circuit

The ISL6414 is an ultra low noise triple output LDO regulator
with microprocessor reset circuit and is optimized for
powering wireless chip sets. The IC accepts an input voltage
range of 3.0V to 3.6V and provides three regulated output
voltages: 1.8V (LDO1), 2.84V (LDO2), and another ultra
clean 2.84V (LDO3). On chip logic provides sequencing
between LDO1 and LDO2 for BBP/MAC and I/O supply
voltage outputs. LDO3 features ultra low noise that does not
typically exceed 30µV RMS to aid VCO stability. High
integration and the thin Quad Flat No-lead (QFN) package
makes ISL6414 an ideal choice to power many of today’s
small form factor industry standard wireless cards, such as
PCMCIA, mini-PCI and Cardbus-32.

The ISL6414 uses an internal PMOS transistor as the pass
device. The SHDN pin controls LDO1 and LDO2 outputs
whereas SHDN3 controls LDO3 output. Internal voltage
sequencing insures that LDO1 output (1.8V supply) is
always stabilized before LDO2 is turned on. When powering
down, power to the LDO2 is removed before the LDO1
output goes off. The ISL6414 also integrates RESET
function, which eliminates the need for additional RESET IC
required in WLAN applications. The IC asserts a RESET
signal whenever the V
threshold, keeping it asserted for at least 25ms after V
risen above the reset threshold. An output fault detection
circuit indicates loss of regulation on LDO1. Other features
include an overcurrent protection, thermal shutdown and
reverse battery protection.

supply voltage drops below a preset

IN

IN

has

Ordering Information

TEMP.

PART NUMBER

ISL6414IR -40 to +85 16 Ld QFN L16.4x4

ISL6414IR-T5K 16 Ld QFN Tape and Reel L16.4x4

ISL6414IR-TK 16 Ld QFN Tape and Reel L16.4x4

ISL6414IRZ (Note) -40 to +85 16 Ld QFN

ISL6414IRZ-TK
(Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

RANGE (°C) PACKAGE

(Pb-free)

16 Ld QFN Tape and Reel
(Pb-free)

PKG.

DWG. #

L16.4x4

L16.4x4

Features

• Small DC/DC Converter Size

- Three LDOs and RESET Circuitry in a Low-Profile
4x4mm QFN Package

• High Output Current

- LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA

- LDO2, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA

- LDO3, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA

• Ultra-Low Dropout Voltage

- LDO2, 2.84V. . . . . . . . . . . . . . . 125mV (typ.) at 300mA

- LDO3, 2.84V. . . . . . . . . . . . . . . 100mV (typ.) at 200mA

• Ultra-Low Output Voltage Noise

-<30µV

• Stable with Smaller Ceramic Output Capacitors

• Voltage Sequencing for BBP/MAC and Analog Supplies

• Extensive Protection and Monitoring Features

- Overcurrent and short circuit protection

- Thermal shutdown

- Reverse battery protection

- FAULT indicator

• Logic-Controlled Dual Shutdown Pins

• Integrated Microprocessor Reset Circuit

- Programmable Reset Delay

- Complimentary Reset Outputs

• Proven Reference Design for Total WLAN System
Solution

• QFN Package Option

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

No Leads - Product Outline

- Near Chip-Scale Package Footprint Improves PCB

Efficiency and Is Thinner in Profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

(typ.) for LDO3 (VCO Supply)

RMS

Applications

• PRISM® 3, PRISM GT™, and PRISM WWR Chipsets

•WLAN Cards

- PCMCIA, Cardbus32, MiniPCI Cards

- Compact Flash Cards

• Hand-Held Instruments

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2003-2005. All Rights Reserved.

Pinout

www.BDTIC.com/Intersil

ISL6414 (QFN)

TOP VIEW

RESET

FAULT

VIN

1516 14 13

ISL6414

VIN

RESET

CT

SHDN

SHDN3

1

2

3

4

6578

CC3

OUT3

GND3

12

11

10

9

GND

Typical Application Schematic

+3.3V

V

IN

+

C8

3.3µF

1

RESET

2

CT

3
4

SHDN
SHDN3

V

OUT3

+2.84V

C7

0.01µF

C5

3.3µF

OUT1

CC1

OUT2

CC2

16

RESET

ISL6414

CC3

OUT3

5

6

14

15

FAULT

GND3

7

E

C6

0.033µF

VIN

GND

8

13

VIN

OUT1

OUT2

CC1

CC2

E

+1.8V

V

OUT1

12
11
10

9

C4

0.033µF

C3

0.033µF

C2

3.3µF

C1

3.3µF

+2.84V

V

OUT2

2

Functional Block Diagram

www.BDTIC.com/Intersil

VIN

15

FAU LT

BAND

GAP

REF.

1.2V

THERMAL

SHUT

DOWN

150°C

ISL6414

WINDOW

COMP

Gm

Gm

13

VIN

14

VIN

+

-

LDO1

+

-

LDO2

OUT1

OUT2

12

11CC1

10

VIN

CONTROL

LOGIC

3

SHDN

4

SHDN3

ENABLES

2

CT

16

RESET

1

RESET

8

GND

RESET

POR

POR

Gm

+

-

LDO3

CC2

OUT3 5

CC3

GND3

9

6

7

3

ISL6414

www.BDTIC.com/Intersil

Absolute Maximum Ratings (Note 1) Thermal Information

VIN, SHDN/SHDN3 to GND/GND3 . . . . . . . . . . . . . . . -7.0V to 7.0V

SET, CC, FAULT to GND/GND3 . . . . . . . . . . . . . . . . . -0.3V to 7.0V

Output Current (Continuous)

LDO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA

LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA

LDO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. All voltages are with respect to GND.

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

2. θ

JA

Tech Brief TB379.

3. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379.

JC

Thermal Resistance (Typical Notes 2, 3) θ

QFN Package. . . . . . . . . . . . . . . . . . . . 46 8.0

Maximum Junction Temperature (Plastic Package) . -55°C to 150°C

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

Operating Temperature Range . . . . . . . . . . . . . . . . . . -40°C to 85°C

(°C/W) θJC (°C/W)

JA

Electrical Specifications V

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

GENERAL SPECIFICATIONS

V

Voltage Range (Note 7) 3.0 3.3 3.6 V

IN

Operating Supply Current I

Shutdown Supply Current SHDN/SHDN3 = GND - 5 15 µA

SHDN/SHDN3 Input Threshold V

FAULT Output Low Voltage I

Thermal Shutdown Temperature (Note 6) 145 150 160 °C

Thermal Shutdown Hysteresis - 20 - °C

Start-up Time C

Input Undervoltage Lockout (Note 6) Rising 75mV Hysteresis 2.2 2.45 2.65 V

LDO1 SPECIFICATIONS

Output Voltage (V

Output Voltage Accuracy I

Line Regulation V

Load Regulation I

Maximum Output Current (I

Output Current Limit (Note 6) 0.55 0.6 1.0 A

Output Voltage Noise 10Hz < f < 100kHz, C

LDO2 SPECIFICATIONS

Output Voltage (V

Output Voltage Accuracy I

Maximum Output Current (I

Output Current Limit (Note 6) 330 770 - mA

Dropout Voltage (Note 4) I

Line Regulation V

Load Regulation I

) -1.8- V

OUT1

OUT1

) -2.84- V

OUT2

OUT2

= +3.3V, Compensation Capacitor = 33nF, TA = 25°C, Unless Otherwise Noted.

IN

= 0mA - 600 850 µA

OUT

, VIN = 3V to 3.6V 2.0 - - V

IH

V

, VIN = 3V to 3.6V - - 0.4 V

IL

= 2mA - - 0.25 V

SINK

= 10µF, V

OUT

value

= 10mA -1.5 - 1.5 %

OUT

= 3.0V to 3.6V, I

IN

= 10mA to 500mA -1.5 - 1.5 %

OUT

) (Note 6) 500 - - mA

= 50mA

I

OUT

= 10mA -1.5 - 1.5 %

OUT

) (Note 6) VIN = 3.6V 300 - - mA

= 300mA - 125 220 mV

OUT

= 3.0V to 3.6V, I

IN

= 10mA to 300mA - 0.2 1.0 %

OUT

= 90% of final

OUT

OUT

OUT

OUT

- 120 - µs

= 10mA -0.15 0.0 0.15 %/V

= 4.7µF,

= 10mA -0.15 0.0 0.15 %/V

-115-µV

RMS

4