intersil ISL6412 DATA SHEET

®

www.BDTIC.com/Intersil

ISL6412

Data Sheet March 20, 2007

Triple Output, Low-Noise LDO Regulator
with Integrated Reset Circuit

The ISL6412 is an ultra low noise triple output LDO regulator
with microprocessor reset circuit and is optimized for
powering wireless chip sets. The IC accepts an input voltage
range of 3.0V to 3.6V and provides three regulated output
voltages: 1.8V (LDO1), 2.8V (LDO2), and another ultra-clean

2.8V (LDO3). On chip logic provides sequencing between
LDO1 and LDO2 for the BBP/MAC and the I/O supply
voltage outputs. LDO3 features ultra low noise that does not
typically exceed 30µV RMS to aid VCO stability. High
integration and the thin Quad Flat No-lead (QFN) package
makes the ISL6412 an ideal choice to power many of today’s
small form factor industry standard wireless cards such as
PCMCIA, mini-PCI and Cardbus-32.

The ISL6412 uses an internal PMOS transistor as the pass
device. The ISL6412 also integrates a reset function, which
eliminates the need for the additional reset IC required in
WLAN applications. The IC asserts a RESET
whenever the VIN supply voltage drops below a preset
threshold, keeping it asserted for a time set by a capacitor to
GND after VIN has risen above the reset threshold. FAULT1
indicates the loss of regulation on LDO1.

signal

Ordering Information

PART

NUMBER

ISL6412IR ISL6412IR -40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6412IR-TK ISL6412IR -40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6412IR-T5K ISL6412IR -40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6412IRZ

(Note 2)
ISL6412IRZ-TK

(Notes 1, 2)

NOTES:

1. T ape and Reel available. Add “-T” suffix for Tape and Reel Packing
Option

2. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

PART

MARKING

6412IRZ -40 to +85 16 Ld 4x4 QFN

6412IRZ -40 to +85 16 Ld 4x4 QFN

TEMP.

RANGE

(°C) PACKAGE

(Pb-free)

(Pb-free)

PKG.

DWG. #

L16.4x4

L16.4x4

FN9067.1

Features

• Small DC/DC Converter Size

- Three LDOs and Reset Circuitry in a Low-Profile
4x4mm QFN Package

• High Output Current

- LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA

- LDO2, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA

- LDO3, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA

• Ultra-Low Dropout Voltage

- LDO2, 2.8V. . . . . . . . . . . . . . . . 125mV (typ.) at 225mA

- LDO3, 2.8V. . . . . . . . . . . . . . . . 100mV (typ.) at 125mA

• Ultra-Low Output Voltage Noise

-<30μV

• Stable with Small Ceramic Output Capacitors

• Extensive Protection and Monitoring Features

- Over current protection

- Short circuit protection

- Thermal shutdown

- FAULT indicator

• Logic-Controlled Shutdown Pin

• Integrated Microprocessor Reset Circuit

- Programmable Reset Delay

• Proven Reference Design for a Total WLAN System
Solution

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

No Leads - Product Outline

- Near Chip-Scale Package Footprint Improves PCB

Efficiency and Is Thinner in Profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

(typ.) for LDO3 (VCO Supply)

RMS

Applications

• PRISM® 3 Chipsets – ISL37106P

•WLAN Cards

- PCMCIA, Cardbus32, MiniPCI Cards

- Compact Flash Cards

• Liberty Chipset

• Hand-Held Instruments

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Copyright © Intersil Americas Inc. 2004, 2007. All Rights Reserved. All Rights Reserved.

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Pinout

www.BDTIC.com/Intersil

ISL6412

ISL6412 (16 LD QFN)

TOP VIEW

NC

FAULT1

VIN

1516 14 13

VIN

Typical Application Schematic

+3.3V

V

IN

+

C4

3.3μF

1

RESET

2
3

C8

4

NC

V

0.01μF

+2.8V

OUT3

CT
SHDN

RESET

CT

SHDN

NC

16

ISL6412

OUT3

5

NC

6

15

CC3

7

FAULT1

1

2

3

4

6578

CC3

OUT3

13

14

VIN

VIN

OUT1

CC1

OUT2

CC2

GND3

GND

8

GND3

12
11
10

9

0.033μF

OUT1

12

CC1

11

OUT2

10

CC2

9

GND

C5 C6

0.033μF

C2

3.3μF

C1

3.3μF

+1.8V

+2.8V

V

V

OUT1

OUT2

C3

3.3μF

C7

0.033μF

Typical Bill Of Materials

REFERENCE

DESIGNATOR VALUE PACKAGE MANUFACTURER

C1, C2, C3, C4 3.3µF, X7R 1206 TDK C3216X7R1A106M

C5, C6, C7 0.033µF, X7R 0603 TDK/ANY C1608X7R1A333K

C8 0.01µF, X7R 0603 TDK/ANY C1608X7R1A103K
U1 ISL6412IR QFN16 Intersil ISL6412IR

2

MANUFACTURER’S

PART NUMBER

FN9067.1

March 20, 2007

Functional Block Diagram

www.BDTIC.com/Intersil

15

FAULT1

THERMAL SHUTDOWN

CONTROL

LOGIC

WINDOW
COMP

150°C

BAND GAP REF.

1.2V

EN

VREF

ISL6412

LDO1

EN

EN

LDO2

VREF

EN

EN

13

VIN

14

VIN

+

-

VIN

OUT2

CC2

OUT1

OUT2

CC2

12

11CC1

10

9

32SHDN

CT

1

RESET

8

GND

RESET

EN

LDO3

VREF

EN

CC3

VIN

OUT3

OUT3

CC3

GND3

5

6

7

3

FN9067.1

March 20, 2007