intersil ISL6412 DATA SHEET

®

www.BDTIC.com/Intersil

ISL6412

Data Sheet March 20, 2007

Triple Output, Low-Noise LDO Regulator
with Integrated Reset Circuit

The ISL6412 is an ultra low noise triple output LDO regulator
with microprocessor reset circuit and is optimized for
powering wireless chip sets. The IC accepts an input voltage
range of 3.0V to 3.6V and provides three regulated output
voltages: 1.8V (LDO1), 2.8V (LDO2), and another ultra-clean

2.8V (LDO3). On chip logic provides sequencing between
LDO1 and LDO2 for the BBP/MAC and the I/O supply
voltage outputs. LDO3 features ultra low noise that does not
typically exceed 30µV RMS to aid VCO stability. High
integration and the thin Quad Flat No-lead (QFN) package
makes the ISL6412 an ideal choice to power many of today’s
small form factor industry standard wireless cards such as
PCMCIA, mini-PCI and Cardbus-32.

The ISL6412 uses an internal PMOS transistor as the pass
device. The ISL6412 also integrates a reset function, which
eliminates the need for the additional reset IC required in
WLAN applications. The IC asserts a RESET
whenever the VIN supply voltage drops below a preset
threshold, keeping it asserted for a time set by a capacitor to
GND after VIN has risen above the reset threshold. FAULT1
indicates the loss of regulation on LDO1.

signal

Ordering Information

PART

NUMBER

ISL6412IR ISL6412IR -40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6412IR-TK ISL6412IR -40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6412IR-T5K ISL6412IR -40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6412IRZ

(Note 2)
ISL6412IRZ-TK

(Notes 1, 2)

NOTES:

1. T ape and Reel available. Add “-T” suffix for Tape and Reel Packing
Option

2. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

PART

MARKING

6412IRZ -40 to +85 16 Ld 4x4 QFN

6412IRZ -40 to +85 16 Ld 4x4 QFN

TEMP.

RANGE

(°C) PACKAGE

(Pb-free)

(Pb-free)

PKG.

DWG. #

L16.4x4

L16.4x4

FN9067.1

Features

• Small DC/DC Converter Size

- Three LDOs and Reset Circuitry in a Low-Profile
4x4mm QFN Package

• High Output Current

- LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA

- LDO2, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA

- LDO3, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA

• Ultra-Low Dropout Voltage

- LDO2, 2.8V. . . . . . . . . . . . . . . . 125mV (typ.) at 225mA

- LDO3, 2.8V. . . . . . . . . . . . . . . . 100mV (typ.) at 125mA

• Ultra-Low Output Voltage Noise

-<30μV

• Stable with Small Ceramic Output Capacitors

• Extensive Protection and Monitoring Features

- Over current protection

- Short circuit protection

- Thermal shutdown

- FAULT indicator

• Logic-Controlled Shutdown Pin

• Integrated Microprocessor Reset Circuit

- Programmable Reset Delay

• Proven Reference Design for a Total WLAN System
Solution

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

No Leads - Product Outline

- Near Chip-Scale Package Footprint Improves PCB

Efficiency and Is Thinner in Profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

(typ.) for LDO3 (VCO Supply)

RMS

Applications

• PRISM® 3 Chipsets – ISL37106P

•WLAN Cards

- PCMCIA, Cardbus32, MiniPCI Cards

- Compact Flash Cards

• Liberty Chipset

• Hand-Held Instruments

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Copyright © Intersil Americas Inc. 2004, 2007. All Rights Reserved. All Rights Reserved.

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Pinout

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ISL6412

ISL6412 (16 LD QFN)

TOP VIEW

NC

FAULT1

VIN

1516 14 13

VIN

Typical Application Schematic

+3.3V

V

IN

+

C4

3.3μF

1

RESET

2
3

C8

4

NC

V

0.01μF

+2.8V

OUT3

CT
SHDN

RESET

CT

SHDN

NC

16

ISL6412

OUT3

5

NC

6

15

CC3

7

FAULT1

1

2

3

4

6578

CC3

OUT3

13

14

VIN

VIN

OUT1

CC1

OUT2

CC2

GND3

GND

8

GND3

12
11
10

9

0.033μF

OUT1

12

CC1

11

OUT2

10

CC2

9

GND

C5 C6

0.033μF

C2

3.3μF

C1

3.3μF

+1.8V

+2.8V

V

V

OUT1

OUT2

C3

3.3μF

C7

0.033μF

Typical Bill Of Materials

REFERENCE

DESIGNATOR VALUE PACKAGE MANUFACTURER

C1, C2, C3, C4 3.3µF, X7R 1206 TDK C3216X7R1A106M

C5, C6, C7 0.033µF, X7R 0603 TDK/ANY C1608X7R1A333K

C8 0.01µF, X7R 0603 TDK/ANY C1608X7R1A103K
U1 ISL6412IR QFN16 Intersil ISL6412IR

2

MANUFACTURER’S

PART NUMBER

FN9067.1

March 20, 2007

Functional Block Diagram

www.BDTIC.com/Intersil

15

FAULT1

THERMAL SHUTDOWN

CONTROL

LOGIC

WINDOW
COMP

150°C

BAND GAP REF.

1.2V

EN

VREF

ISL6412

LDO1

EN

EN

LDO2

VREF

EN

EN

13

VIN

14

VIN

+

-

VIN

OUT2

CC2

OUT1

OUT2

CC2

12

11CC1

10

9

32SHDN

CT

1

RESET

8

GND

RESET

EN

LDO3

VREF

EN

CC3

VIN

OUT3

OUT3

CC3

GND3

5

6

7

3

FN9067.1

March 20, 2007

ISL6412

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

VIN, SHDN to GND/GND3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V

SET, CC, FAULT to GND/GND3 . . . . . . . . . . . . . . . . . -0.3V to 7.0V

Output Current (Continuous)

LDO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA

LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA

LDO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

3. θ

JA

Tech Brief TB379.

4. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance (Typical) θ

QFN Package (Notes 3, 4). . . . . . . . 46 9

Maximum Junction Temperature (Plastic Package) -55°C to +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

(°C/W) θJC (°C/W)

JA

Electrical Specifications V

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

GENERAL SPECIFICATIONS

Voltage Range 3.0 3.3 3.6 V

V

IN

Operating Supply Current I
Shutdown Supply Current SHDN = GND - 5 10 μA
SHDN Input Threshold V

Thermal Shutdown Temperature (Note 7) 145 150 160 °C
Thermal Shutdown Hysteresis (Note 7) - 20 - °C
Start-up Time (Note 7) C

Input Undervoltage Lockout Rising 75mV Hysteresis 2.4 2.45 2.6 V

LDO1 SPECIFICATIONS

Output Voltage (V
Output Voltage Initial Accuracy I
Line Regulation V
Load Regulation I
Maximum Output Current (I
Output Current Limit (Note 7) 500 600 1105 mA
Output Voltage Noise (Note 7) 10Hz < f < 100kHz, C

LDO2 SPECIFICATIONS

Output Voltage (V
Output Voltage Accuracy I
Maximum Output Current (I
Output Current Limit (Note 7) 330 - 900 mA
Dropout Voltage (Notes 5, 7) I
Line Regulation V
Load Regulation I

) -1.8- V

OUT1

OUT1

) -2.8- V

OUT2

OUT2

= +3.3V, Compensation Capacitor = 33nF, TA = +25°C, unless otherwise noted.

IN

= 0mA - 830 1125 μA

OUT

, VIN = 3V to 3.6V 2.0 - - V

IH

VIL, VIN = 3V to 3.6V - - 0.4 V

= 10μF, V

OUT

value

= 10mA, TA = -40°C to 85°C -2.0 - 2.0 %

OUT

= 3.0V to 3.6V, I

IN

= 10mA to 330mA -1.5 - 1.5 %

OUT

) (Note 7) 330 - - mA

= 50mA

I

OUT

= 10mA, TA = -40°C to 85°C -2.0 - 2.0 %

OUT

) (Note 7) VIN = 3.6V 225 - - mA

= 225mA - 125 160 mV

OUT

= 3.0V to 3.6V, I

IN

= 10mA to 225mA - 0.2 1.0 %

OUT

= 90% of final

OUT

OUT

OUT

OUT

- 120 - μs

= 10mA -0.15 0.0 0.15 %/V

= 4.7μF,

= 10mA -0.15 0.0 0.15 %/V

-115-μV

RMS

4

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ISL6412

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Electrical Specifications V

= +3.3V, Compensation Capacitor = 33nF, TA = +25°C, unless otherwise noted. (Continued)

IN

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Output Voltage Noise (Note 7) 10Hz < f < 100kHz, I

= 2.2μF-65-μV

C

OUT

C

= 10μF-60-μV

OUT

OUT

= 10mA

LDO3 SPECIFICATIONS

Output Voltage (V
Output Voltage Accuracy I
Maximum Output Current (I

) -2.8- V

OUT3

= 10mA, TA = -40°C to +85°C -2.0 - 2.0 %

OUT

) (Note 7) VIN = 3.6V 225 - - mA

OUT3

Output Current Limit (Note 7) 300 450 840 mA
Dropout Voltage (Notes 5, 7) I
Line Regulation V
Load Regulation I
Output Voltage Noise (Note 7) 10Hz < f < 100kHz, I

= 125mA - 100 160 mV

OUT

= 3.0V to 3.6V, I

IN

= 10mA to 125mA - 0.2 1.0 %

OUT

= 2.2μF-30-μV

C

OUT

C

= 10μF-20-μV

OUT

= 10mA -0.15 0.0 0.15 %/V

OUT

= 10mA

OUT

RESET BLOCK SPECIFICATIONS

Reset Threshold 2.564 2.630 2.66 V
Reset Threshold Hysteresis (Note 7) 6.3 - - mV

to Reset Delay VCC = VTH to VTH - 100mV - 20 - μs

V

IN

RESET Active Timeout Period (Notes 6, 7) CT = 0.01µF 50 - - ms

FAULT1

Rising Threshold % of V
Falling Threshold % of V

OUT
OUT

+5.5 +8.0 +10.5 %

-10.5 -8.0 -5.5 %

NOTES:

5. The dropout voltage is defined as V

6. The RESET

time is linear with CT at a slope of ~5ms/nF. Thus, at 10nF (0.01μF) the RESET time is 50ms.

OUT

, when V

IN

is 50mV below the value of V

OUT

OUT

for VIN = V

OUT

+ 0.5V.

- V

7. Guaranteed by design, not production tested.

RMS
RMS

RMS
RMS

Typical Performance Curves The test conditions for the Typical Operating Performance are: V

Unless Otherwise Noted

SHDN

1V/DIV

VOUT2
1V/DIV

100µs/DIV

VOUT1
1V/DIV

VOUT1
1V/DIV

VOUT3

1V/DIV

FIGURE 1. START-UP SEQUENCE FIGURE 2. SHUTDOWN SEQUENCE

5

100µs/DIV

= 3.3V, TA = +25°C,

IN

SHDN

1V/DIV

VOUT2
1V/DIV

VOUT3
1V/DIV

March 20, 2007

FN9067.1

ISL6412

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Typical Performance Curves The test conditions for the Typical Operating Performance are: V

= 3.3V, TA = +25°C,

IN

Unless Otherwise Noted (Continued)

SHDN

2V/DIV

VOUT1
2V/DIV

RESET
2V/DIV

FAULT
2V/DIV

20ms/DIV

VOUT1

50mV/DIV

IOUT1

200mA/DIV

1ms/DIV

FIGURE 3. SHUTDOWN, FAULT, and RESET OPERATION FIGURE 4. LDO1 TRANSIENT RESPONSE (10mA to 330mA)

VOUT2

100mV/DIV

VOUT3

100mV/DIV

IOUT2

100mA/DIV

1ms/DIV

IOUT3

50mA/DIV

1ms/DIV

FIGURE 5. LDO2 TRANSIENT RESPONSE (10mA to 200mA) FIGURE 6. LDO3 TRANSIENT RESPONSE (10mA to 100mA)

VIN

0.5V/DIV

VIN

0.5V/DIV
RESET

0.5V/DIV

0.5V/DIV

20ms/DIV

CT

CT

0.5V/DIV

RESET

0.5V/DIV

100ms/DIV

FIGURE 7. RESET DELAY DURING START-UP (CT = 0.01µF) FIGURE 8. RESET DELAY DURING START-UP (CT = 0.1µF)

6

FN9067.1

March 20, 2007

ISL6412

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Typical Performance Curves The test conditions for the Typical Operating Performance are: V

Unless Otherwise Noted (Continued)

-10

-20

-30

FAULT
1V/DIV

VOUT1/2/3

1V/DIV

FIGURE 9. THERMAL SHUTDOWN OPERATION FIGURE 10. LDO1 POWER SUPPLY REJECTION

500ms/DIV

VIN

0.5V/DIV

VIN = 2.7V

-40

PSRR (dB)

-50

-60
10 1k

(IOUT1 = 100mA, COUT = 10µF MLCC)

100

FREQUENCY (A)

= 3.3V, TA = +25°C,

IN

10k 100k

1M

VOUT1

0.5V/DIV

FAULT

0.5V/DIV

FIGURE 11. VOUT1 REGULATION DOWN TO VIN = 2.7V; FAULT MONITORS VOUT1 ONLY

Pin Descriptions

OUT1 - This pin is the output for LDO1. Bypass with a
minimum of 2.2µF, low ESR capacitor to GND for stable
operation.

V

- Supply input pins. Connect to input power source.

IN

Bypass with a minimum 2.2μF capacitor to GND. Both V
pins must be tied together on the PC board, close to the IC.

GND - Ground for LDO1 and LDO2.
CC1 - Compensation Capacitor for LDO1. Connect a

0.033µF capacitor from CC1 to GND.
SHDN - Shutdown input for all LDOs. Connect to V

normal operation. Drive this pin LOW to turn off all LDOs.

IN

IN

for

OUT2 - This pin is the output for LDO2. Bypass with a
minimum of 2.2µF, low ESR capacitor to GND for stable
operation.

CT - Timing pin for the RESET circuit pulse width.
CC2 - Compensation capacitor for LDO2. Connect a

0.033µF capacitor from CC2 to GND.
OUT3 - This pin is output for LDO3. Bypass with a minimum

of 2.2µF, low ESR capacitor to GND3 for stable operation.

GND3 - Ground pin for LDO3.
CC3 - Compensation capacitor for LDO3. Connect a

0.033µF capacitor from CC3 to GND3.
FAULT1 - This is the power good indicator for LDO1. When

the 1.8V output is out of regulation this pin goes LOW. This

7

FN9067.1

March 20, 2007

ISL6412

www.BDTIC.com/Intersil

pin also goes LOW during thermal shutdown or an
overcurrent event on LDO1. Connect this pin to GND, if
unused.

RESET

- This pin is the active-LOW output of the push-pull
output stage of the integrated reset supervisory circuit. The
reset circuit monitors V
pin, if V
output remains LOW, while the V
reset threshold, and for at least 25ms, after V
the RESET threshold.

falls below the RESET threshold. The RESET

IN

and asserts a RESET output at this

IN

pin voltage is below the

IN

rises above

IN

Functional Description

The ISL6412 is a 3-in-1 multi-output, low dropout, regulator
designed for wireless chipset power applications. It supplies
three fixed output voltages 1.8V, 2.8V and 2.8V. Each LDO
consists of a 1.2V reference, error amplifier, MOSFET driver,
P-Channel pass transistor, dual-mode comparator and
internal feedback voltage divider.

The 1.2V band gap reference is connected to the error
amplifier’s inverting input. The error amplifier compares this
reference to the selected feedback voltage and amplifies the
difference. The MOSFET driver reads the error signal and
applies the appropriate drive to the P-Channel pass transistor.
If the feedback voltage is lower then the reference voltage, the
pass transistor gate is pulled lower, allowing more current to
pass and increasing the output voltage. If the feedback
voltage is higher then the reference voltage, the pass
transistor gate is driven higher , allowing less current to pass to
the output. The output voltage is fed back through an internal
resistor divider connected to OUT1/OUT2/OUT3 pins.

Additional blocks include an output overcurrent protection,
thermal sensor, fault detector, RESET
shutdown logic.

Internal P-Channel Pass Transistors

The ISL6412 features a typical 0.5Ω r
MOSFET pass transistors. This provides several advantages
over similar designs using PNP bipolar pass transistors. The
P-Channel MOSFET requires no base drive, which reduces
quiescent current considerably. PNP based regulators waste
considerable current in dropout when the pass transistor
saturates. They also use high base drive currents under
large loads. The ISL6412 does not suffer from these
problems.

function and

P-channel

DS(ON)

The voltage at the CT pin is compared to the 1.2V bandgap
voltage. The charging of the CT capacitor behaves like an
RC network and the RESET

Td = -R*C*ln(1-1.2V/VIN)
Where C is the capacitor at CT, and R is 11.1MΩ for

VIN = 3.3V. With no capacitor on the CT pin the RESET
delay will be close to zero. Figure 12 shows the RESET
delay vs CT capacitance.

500

400

300

200

DELAY (ms)

100

0

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0

FIGURE 12. RESET DELAY vs CT CAPACITANCE

delay can be approximated by:

CT (µF)

Output Voltages

The ISL6412 provides fixed output voltages for use in
Wireless Chipset applications. Internal trimmed resistor
networks set the typical output voltages as shown here:

V

OUT1

= 1.8V; V

OUT2

= 2.8V; V

OUT3

= 2.8V.

Shutdown

Pulling the SHDN pin LOW puts the complete chip into
shutdown mode, and supply current drops to 5μA typical.
This input has an internal pull-up resistor, so that in normal
operation the outputs are always enabled; external pull-up
resistors are not required.

Current Limit

The ISL6412 monitors and controls the pass transistor’s
gate voltage to limit the output current. The current limit for
LDO1 is 500mA, LDO2 is 330mA and LDO3 is 300mA. The
output can be shorted to ground without damaging the part
due to the current limit and thermal protection features.

Integrated Reset for MAC/Baseband Processors

The ISL6412 includes a microprocessor supervisory block.
This block eliminates the extra reset IC and external
components needed in wireless chipset applications. This
block performs a single function; it asserts a RESET
whenever the V
threshold, keeping it asserted for a programmable time (set
by external capacitor CT) after the V
above the reset threshold. The reset threshold for the
ISL6412 is 2.63V typical.

supply voltage decreases below a preset

IN

pin voltage has risen

IN

8

signal

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March 20, 2007

ISL6412

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Thermal Overload Protection

Thermal overload protection limits total power dissipation in
the ISL6412. When the junction temperature (T

) exceeds

J

+150°C, the thermal sensor sends a signal to the shutdown
logic, turning off the pass transistor and allowing the IC to
cool. The pass transistor turns on again after the IC’s
junction temperature typically cools by 20°C, resulting in a
pulsed output during continuous thermal overload
conditions. Thermal overload protection protects the
ISL6412 against fault conditions. For continuous operation,
do not exceed the absolute maximum junction temperature
rating of +150°C.

Operating Region and Power Dissipation

The maximum power dissipation of ISL6412 depends on the
thermal resistance of the IC package and circuit board, the
temperature difference between the die junction and ambient
air, and the rate of air flow. The power dissipated in the
device is:

PT = P1 + P2 + P3, where
P1 = I
P2 = I
P3 = I

OUT1
OUT2
OUT3

(VIN – V
(VIN – V
(VIN- V

OUT1
OUT2

OUT3

)
)

)
The maximum power dissipation is:
Pmax = (Tjmax – TA)/θJA
Where Tjmax = +150°C, TA = ambient temperature, and θJA

is the thermal resistance from the junction to the surrounding
environment.

The ISL6412 package features an exposed thermal pad on
its underside. This pad lowers the thermal resistance of the
package by providing a direct heat conduction path from the
die to the PC board. Additionally, the ISL6412’s ground
(GND/GND3) performs the dual function of providing an
electrical connection to system ground and channeling heat
away. Connect the exposed backside pad and GND to the
system ground using a large pad or ground plane, or through
multiple vias to the ground plane layer.

Integrator Circuitry

The ISL6412 uses an external 33nF compensation capacitor
for minimizing load and line regulation errors and for
lowering output noise. When the output voltage shifts due to
varying load current or input voltage, the integrator capacitor
voltage is raised or lowered to compensate for the
systematic offset at the error amplifier. Compensation is
limited to ±5% to minimize transient overshoot when the
device goes out of dropout, current limit, or thermal
shutdown.

FAULT Functionality

TABLE 1.

EVENT FAULT1

Below UVLO threshold L

= 1.8V ±8% typ

V

OUT1

V

OUT2/VOUT3

V

OUT1

V

OUT2

Thermal Shutdown L
Normal Shutdown with SHDN pin L
Overcurrent only on LDO1 L
Overcurrent only on LDO2/LDO3 H

not in regulation

not in regulation
and V

are in regulation

OUT3

H

L

Applications Information

Capacitor Selection and Regulator Stability

Capacitors are required at the ISL6412’s input and output for
stable operation over the entire load range and the full
temperature range. Use >1µF capacitor at the input of
ISL6412. The input capacitor lowers the source impedance
of the input supply. Larger capacitor values and lower ESR
provides better PSRR and line transient response. The input
capacitor must be located at a distance of not more then 0.5
inches from the VIN pins of the IC and returned to a clean
analog ground. Any good quality ceramic or tantalum can be
used as an input capacitor.

The output capacitor must meet the requirements of
minimum amount of capacitance and ESR for all three
LDO’s. The ISL6412 is specifically designed to work with
small ceramic output capacitors. The output capacitor’s ESR
affects stability and output noise. Use an output capacitor
with an ESR of 50mΩ or less to insure stability and optimum
transient response. For stable operation, a ceramic
capacitor, with a minimum value of 3.3μF, is recommended
for V
recommended for V
current. There is no upper limit to the output capacitor value.
Larger capacitor can reduce noise and improve load
transient response, stability and PSRR. Higher value of
output capacitor (10µF) is recommended for LDO3 when
used to power VCO circuitry in wireless chipsets. The output
capacitor should be located very close to VOUT pins to
minimize impact of PC board i n du ctances and the other end
of the capacitor should be returned to a clean analog
ground.

Input-Output (Dropout) Voltage

A regulator’s minimum input-output voltage differential (or
dropout voltage) determines the lowest usable supply
voltage. Because the ISL6412 uses a P-channel MOSFET
pass transistor, its dropout voltage is a function of r
(typically 0.5) multiplied by the load current.

for 300mA output current, and 2.2μF is

OUT1

OUT2

and V

each at 200mA load

OUT3

DS(ON)

9

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March 20, 2007

ISL6412

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Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 ­A1 - - 0.05 ­A2 - - 1.00 9
A3 0.20 REF 9

b 0.23 0.28 0.35 5, 8

D 4.00 BSC -

D1 3.75 BSC 9
D2 1.95 2.10 2.25 7, 8

E 4.00 BSC ­E1 3.75 BSC 9
E2 1.95 2.10 2.25 7, 8

e 0.65 BSC -

k0.25 - - -

L 0.50 0.60 0.75 8
L1 - - 0.15 10

N162

Nd 4 3
Ne 4 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

NOTESMIN NOMINAL MAX

Rev. 5 5/04

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

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10

FN9067.1

March 20, 2007