Intersil ISL6322CRZ, ISL6322IRZ Schematics

®

ISL6322

Data Sheet

Four-Phase Buck PWM Controller with
Integrated MOSFET Drivers and I2C
Interface for Intel VR10, VR11, and AMD
Applications

The ISL6322 four-phase PWM control IC provides a
precision voltage regulation system for advanced
microprocessors. The integration of power MOSFET drivers
into the controller IC marks a departure from the separate
PWM controller and driver configuration of previous
multiphase product families. By reducing the number of
external parts, this integration is optimized for a cost and
space saving power management solution.

One outstanding feature of this controller IC is its
multi-processor compatibility, allowing it to work with both Intel
and AMD microprocessors. Included are programmable VID
codes for Intel VR10, VR11, as well as AMD DAC t ables. A
unity gain, differential amplifier is provided for remote voltage
sensing, compensating for any potential difference between
remote and local grounds. The output voltage can also be
positively or negatively offset through the use of a single
external resistor.

The ISL6322 includes an I
controller to communicate with other devices over an I
bus. Signals sent over this bus can command the ISL6322 to
adjust voltage margining offset, converter switching
frequency, and overvoltage protection levels, and can select
the integrated driver adaptive dead time scheme.

The ISL6322 also includes advanced control loop features
for optimal transient response to load apply and removal.
One of these features is highly accurate, fully differential,
continuous DCR current sensing for load line programming
and channel current balance. Active Pulse Positioning (APP)
modulation is another unique feature, allowing for quicker
initial response to high di/dt load transients.

This controller also allows the user the flexibility to choose
between PHASE detect or LGATE detect adaptive dead time
schemes. This ability allows the ISL6322 to be used in a
multitude of applications where either scheme is required.

Protection features of this controller IC include a set of
sophisticated overvoltage, undervoltage, and overcurrent
protection. Furthermore, the ISL6322 includes protection
against an open circuit on the remote sensing inputs.
Combined, these features provide advanced protection for the
microprocessor and power system.

2

C interface, allowing the

2

C

August 2, 2007

FN6328.2

Features

• Integrated Multiphase Power Conversion

- 2-Phase or 3-Phase Operation with Internal Drivers

- 4-Phase Operation with External PWM Driver Signal

• Precision Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over-Temperature

- Adjustable Reference-Voltage Offset

• Optimal Transient Response

- Active Pulse Positioning (APP) Modulation

- Adaptive Phase Alignment (APA)

• Fully Differential, Continuous DCR Current Sensing

- Accurate Load Line Programming

- Precision Channel Current Balancing

2

C Interface

•I

- Voltage Margining Offset

- Switching Frequency Adjustment

- Overvoltage Protection Level Adjustment

- Selects Adaptive Dead Time Scheme

2

• User Selectable I
1000_110x or 1000_111x

• User Selectable Adaptive Dead Time Scheme

- PHASE Detect or LGATE Detect for Application

Flexibility

• Variable Gate Drive Bias: 5V to 12V

• Multi-Processor Compatible

- Intel VR10 and VR11 Modes of Operation

- AMD Mode of Operation

• Microprocessor Voltage Identification Inputs

-8-bit DAC

- Selectable between Intel’s Extended VR10, VR11, AMD

5-bit, and AMD 6-bit DAC Tables

- Dynamic VID Technology

• Overcurrent Protection

• Multi-Tiered Overvoltage Protection

• Digital Soft-Start

• Selectable Operation Frequency up to 1.5MHz Per Phase

• Pb-Free Plus Anneal Available (RoHS Compliant)

C “Slave Only” Device Address:

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

ISL6322ISL6322

Ordering Information

PART NUMBER (Note) PART MARKING TEMP. (°C) PACKAGE (Pb-Free) PKG. DWG. #

ISL6322CRZ* ISL6322 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
ISL6322IRZ* ISL6322 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material se ts; mold ing compounds/ die attach m aterials and 100% mat te tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free product s are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-f ree re quirements of IPC/JEDEC J STD-020.

Pinout

ISL6322

(48 LD QFN)

TOP VIEW

PHASE3

VID6

VID7

VID5

48

47 46 45 44 43 42 41 40 39

FS

ISEN3-

ISEN3+

PVCC3

LGATE3

BOOT3

UGATE3

PGOOD

38 37

VID4
VID3
VID2
VID1
VID0

VRSEL

SCL

SDA

SS/RST/A0

VCC

REF
OFS

1
2
3
4
5

RGND

49

GND

VSEN

6
7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22

FB

COMP

VDIFF

IDROOP

ISEN2+

ISEN2-

EN

36

ISEN1+

35

ISEN1-

34

PHASE1

33

UGATE1

32

BOOT1

31

LGATE1

30

PVCC1_2

29

LGATE2

28

BOOT2

27

UGATE2

26

PHASE2

25

23 24

ISEN4-

ISEN4+

PWM4

EN_PH4

2

FN6328.2

August 2, 2007

Block Diagram

VSEN

RGND

VDIFF

OPEN SENSE

LINE PREVENTION

x1

UNDERVOLTAGE

DETECTION

LOGIC

ISL6322ISL6322

PGOOD

SOFT-START

AND

FAULT LOGIC

0.85V

EN

POWER-ON

RESET

VCC

PVCC1_2

BOOT1

SS/RST/A0

SCL

SDA

VRSEL

VID7
VID6

VID5
VID4
VID3
VID2
VID1
VID0

REF

FB

COMP

OFS

IDROOP

OVERVOLTAGE

DETECTION

I2C

LOGIC

MODE/DAC

SELECT

DYNAMIC

VID
D/A

OFFSET

LOGIC

E/A

OC

I_TRIP

I_AVG

LOAD APPL Y

TRANSIENT

ENHANCEMENT

CLOCK AND

MODULATOR

WAVEFORM

GENERAT OR

∑

∑

∑

∑

CHANNEL
CURRENT
BALANCE

0.2V

I_AVG

MOSFET

DRIVER

CHANNEL

DETECT

MOSFET

DRIVER

PH4 POR/

MOSFET

DRIVER

DETECT

PWM1

PWM2

PWM3

PWM4

1
N

UGATE1

PHASE1

LGATE1

FS

BOOT2

UGATE2

PHASE2

LGATE2

EN_PH4

PVCC3

BOOT3
UGATE3

PHASE3

LGATE3

ISEN1-

3

CH1

CURRENT

SENSE

ISEN1+

CURRENT

SENSE

ISEN2-

CH2

ISEN2+

CURRENT

SENSE

ISEN3-

CH3

ISEN3+

∑

CURRENT

SENSE

ISEN4-

CH4

ISEN4+

GND

PWM4

SIGNAL

LOGIC

PWM4

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August 2, 2007

ISL6322 Integrated Driver Block Diagram

DRSEL

ISL6322ISL6322

PVCC

BOOT

UGATE

PWM

GATE

CONTROL

SOFT-START

AND

FAULT LOGIC

LOGIC

Simplified I2C Bus Architecture

SHOOT-

THROUGH

PROTECTION

2

C BUS

I

MASTER

SDA

SCL

+5V

20kΩ

PHASE

10kΩ

LGATE

+5V

SCL SDA

SLAVE

IC #1

SCL SDA

SLAVE

IC #2

4

SCL SDA

ISL6322

SLAVE ADDRESS:

1000_110x

NOTE: PIN A0 SELECTS THE SLAVE ADDRESS FOR THE ISL6322

A0

R

SS

SCL SDA

ISL6322

SLAVE ADDRESS:

1000_111x

+5V

A0

FN6328.2

August 2, 2007

R

SS

Typical Application - ISL6322 (4-Phase)

ISL6322ISL6322

+5V

IDROOP

FB
COMP

VSEN
RGND

VCC

OFS

FS
REF

SCL
SDA
SS / RST / A0

VDIFF

ISL6322

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1­ISEN1+

PVCC1_2

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2-

ISEN2+

+12V

+12V

LOAD

+12V

VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0

VRSEL
PGOOD

EN

GND

PVCC3

BOOT3

UGATE3

PHASE3

LGATE3

ISEN3­ISEN3+

EN_PH4

PWM4

ISEN4­ISEN4+

+12V

VCC
PVCC

ISL6612

PWM

+12V

+12V

BOOT

UGATE
PHASE

LGATE

GND

5

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August 2, 2007

ISL6322ISL6322

Typical Application - ISL6322 with NTC Thermal Compensation (4-Phase)

+5V

IDROOP

FB

COMP

VSEN
RGND

VCC

OFS

FS
REF

SCL
SDA
SS / RST / A0

ISL6322

VDIFF

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1-

ISEN1+

PVCC1_2

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2­ISEN2+

+12V

+12V

NTC

PLACE IN
CLOSE
PROXIMITY

LOAD

+12V

VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0

VRSEL
PGOOD

EN

GND

PVCC3

BOOT3

UGATE3

PHASE3

LGATE3

ISEN3-

ISEN3+

EN_PH4

PWM4

ISEN4­ISEN4+

+12V

BOOT

VCC
PVCC

ISL6612

PWM

+12V

+12V

UGATE
PHASE

LGATE

GND

6

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August 2, 2007

ISL6322ISL6322

Absolute Maximum Ratings

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V

BOOT Voltage, V
BOOT to PHASE Voltage, V

PHASE Voltage, V

GND - 8V (<400ns, 20µJ) to 24V (<200ns, V

UGATE Voltage, V

V

PHASE

LGATE Voltage, V

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC + 0.3V

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

. . . . . . . . . . . . . .GND - 0.3V to GND + 36V

BOOT

BOOT - PHASE

. . . . . . . GND - 0.3V to 15V (PVCC = 12)

PHASE

. . . . . . . .V

UGATE

- 3.5V (<100ns Pulse Width, 2µJ) to V

. . . . . . . . . . . GND - 0.3V to PVCC + 0.3V

LGATE

. . . . . -0.3V to 15V (DC)

-0.3V to 16V (<10ns, 10µJ)

BOOT - PHASE

- 0.3V to V

PHASE

BOOT
BOOT

= 12V)
+ 0.3V
+ 0.3V

Thermal Information

Thermal Resistance θJA (°C/W) θJC (°C/W)

QFN Package (Notes 1, 2). . . . . . . . . . 27 2.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V ±5%

Ambient Temperature (ISL6322CRZ) . . . . . . . . . . . . . 0°C to +70°C

Ambient Temperature (ISL6322IRZ) . . . . . . . . . . . . .-40°C to +85°C

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

JA

Tech Brief TB379.

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

3. Limits established by characterization and are not production tested.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

BIAS SUPPLIES

Input Bias Supply Current I
Gate Drive Bias Current - PVCC1_2 Pin I
Gate Drive Bias Current - PVCC3 Pin I
VCC POR (Power-On Reset) Threshold VCC rising 4.25 4.38 4.50 V

PVCC POR (Power-On Reset) Threshold PVCC rising 4.25 4.38 4.50 V

PWM MODULATOR

Oscillator Frequency Accuracy, f

SW

Adjustment Range of Switching Frequency (Note 3) 0.08 1.0 MHz
Oscillator Ramp Amplitude, V

PP

CONTROL THRESHOLDS

EN Rising Threshold 0.85 V
EN Hysteresis 110 mV
EN_PH4 Rising Threshold 1.160 1.210 1.250 V
EN_PH4 Falling Threshold 1.00 1.06 1.10 V
COMP Shutdown Threshold COMP falling 0.1 0.2 0.3 V

REFERENCE AND DAC

System Accuracy (1.000V to 1.600V) -0.5 0.5 %
System Accuracy (0.600V to 1.000V) -1.0 1.0 %
System Accuracy (0.375V - 0.600V) -2.0 2.0 %
DAC Input Low Voltage (VR10, VR11) 0.4 V
DAC Input High Voltage (VR10, VR11) 0.8 V

; EN = high 15 20 25 mA

VCC
PVCC1_2
PVCC3

; EN = high 2 4.3 6 mA

; EN = high 1 2.1 3 mA

VCC falling 3.75 3.88 4.00 V

PVCC falling 3.60 3.88 4.00 V

RT = 100kΩ (±0.1%) 225 250 275 kHz

(Note 3) 1.50 V

7

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ISL6322ISL6322

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DAC Input Low Voltage (AMD) 0.6 V
DAC Input High Voltage (AMD) 1.0 V

PIN-ADJUSTABLE OFFSET

OFS Sink Current Accuracy (Negative Offset) R
OFS Source Current Accuracy (Positive Offset) R

ERROR AMPLIFIER

DC Gain R
Gain-Bandwidth Product C
Slew Rate CL = 100pF, Load = ±400μA, (Note 3) 8 V/μs
Maximum Output Voltage Load = 1mA 3.90 4.20 V
Minimum Output Voltage Load = -1mA 1.30 1.5 V

SOFT-START RAMP

Soft-Start Ramp Rate VR10/VR11, R

Adjustment Range of Soft-Start Ramp Rate (Note 3) 0.625 6.25 mV/µs

PWM OUTPUT

PWM Output Voltage LOW Threshold Iload = ±500μA0.5V
PWM Output Voltage HIGH Threshold Iload = ±500μA4.5V

CURRENT SENSING

Current Sense Resistance, R

ISEN

Sensed Current Tolerance ISEN1+ = ISEN2+ = ISEN3+ = ISEN4+ = 80μA 768084μA

OVERCURRENT PROTECTION

Overcurrent Trip Level - Average Channel Normal operation 110 125 140 μA

Overcurrent Trip Level - Individual Channel Normal operation 150 177 204 μA

PROTECTION

Undervoltage Threshold VSEN falling 55 60 65 %VID
Undervoltage Hysteresis VSEN rising 10 %VID
Overvoltage Threshold During Soft-Start VR10/VR11 1.24 1.28 1.32 V

Overvoltage Threshold (Default) VSEN rising VDAC +

Overvoltage Threshold (Alternate) VSEN rising VDAC +

Overvoltage Hysteresis VSEN falling 100 mV

SWITCHING TIME (Note 3)

UGATE Rise Time t
LGATE Rise Time t
UGATE Fall Time t
LGATE Fall Time t

= 10kΩ from OFS to GND 37.0 40.0 43.0 μA

OFS

= 30kΩ from OFS to VCC 50.5 53.5 56.5 μA

OFS

= 10k to ground, (Note 3) 96 dB

L

= 100pF, RL = 10k to ground, (Note 3) 20 MHz

L

= 100kΩ 1.563 mV/µs

S

AMD 2.063 mV/µs

T = +25°C 297 300 303 Ω

Dynamic VID change 143 163 183 μA

Dynamic VID change (Note 3) 209.4 238 266.6 μA

AMD 2.13 2.20 2.27 V

RUGATE; VPVCC
RLGATE; VPVCC
FUGATE; VPVCC
FLGATE; VPVCC

VDAC +

225mV

250mV

VDAC +

150mV

175mV

= 12V, 3nF load, 10% to 90% 26 ns
= 12V, 3nF load, 10% to 90% 18 ns
= 12V, 3nF load, 90% to 10% 18 ns

= 12V, 3nF load, 90% to 10% 12 ns

VDAC +

275mV

VDAC +

200mV

V

V

8

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ISL6322ISL6322

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

UGATE Turn-On Non-Overlap t
LGATE Turn-On Non-Overlap t

PDHUGATE
PDHLGATE

GATE DRIVE RESISTANCE (Note 3)

Upper Drive Source Resistance V
Upper Drive Sink Resistance V
Lower Drive Source Resistance V
Lower Drive Sink Resistance V

PVCC
PVCC
PVCC
PVCC

OVER TEMPERATURE SHUTDOWN (Note 3)

Thermal Shutdown Setpoint - 160 - °C
Thermal Recovery Setpoint - 100 - °C

; V

; V

= 12V, 3nF load, adaptive 10 ns

PVCC

= 12V, 3nF load, adaptive 10 ns

PVCC

= 12V, 15mA source current 1.25 2.0 3.0 Ω
= 12V, 15mA sink current 0.9 1.65 3.0 Ω
= 12V, 15mA source current 0.85 1.25 2.2 Ω
= 12V, 15mA sink current 0.60 0.80 1.35 Ω

Timing Diagram

t

PDHUGATE

UGATE

LGATE

t

RUGATE

t

FUGATE

t

FLGATE

t

PDHLGATE

t

RLGATE

9

FN6328.2

August 2, 2007

ISL6322ISL6322

Functional Pin Description

VCC

VCC is the bias supply for the ICs small-signal circuitry.
Connect this pin to a +5V supply and decouple using a
quality 0.1μF ceramic capacitor.

PVCC1_2 and PVCC3

These pins are the power supply pins for the corresponding
channel MOSFET drive, and can be connected to any
voltage from +5V to +12V depending on the desired
MOSFET gate-drive level. Decouple these pins with a quality

1.0μF ceramic capacitor .
Leaving PVCC3 unconnected or grounded programs the

controller for 2-phase operation.

GND

GND is the bias and reference ground for the IC.

EN

This pin is a threshold-sensitive (approxima tely 0.85V) enable
input for the controller. Held low, this pin disables controller
operation. Pulled high, the pin enables the controller for
operation.

FS

A resistor, placed from FS to ground, sets the switching
frequency of the controller.

VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7

These are the inputs for the internal DAC that provides the
reference voltage for output regulation. These pins respond to
TTL logic thresholds. These pins are internally pulled high, to
approximately 1.2V, by 40μA internal current sources for Intel
modes of operation, and pulled low by 20μA internal current
sources for AMD modes of operation. The internal pull-up
current decreases to 0 as the VID voltage approaches the
internal pull-up voltage. All VID pins are compat ible with
external pull-up voltages not exceeding the IC’s bias voltage
(VCC).

VRSEL

The state of this pin selects which of the available DAC tables
will be used to decode the VID inputs and puts the controller
into the corresponding mode of operation. For VR10 mode of
operation VRSEL should be less then 0.6V. The VR11 mode of
operation can be selected by setting VRSEL between 0.6V and

3.0V , and AMD compliance is selected if this pin is between

3.0V and VCC.

VSEN and RGND

VSEN and RGND are inputs to the precision differe ntial
remote-sense amplifier and should be connected to the sense
pins of the remote load.

VDIFF

VDIFF is the output of the differential remote-sense amplifier .
The voltage on this pin is equal to the difference between
VSEN and RGND.

FB and COMP

These pins are the internal error amplifier inverting input and
output respectively. FB, VDIFF, and COMP are tied together
through external R-C networks to compensate the regulator.

IDROOP

The IDROOP pin is the average channel-current sense
output. Connecting this pin through a tuned parallel R-C
network to FB allows the converter to incorporate output
voltage droop proportional to the output current. If voltage
droop is not desired leave this pin unconnected.

REF

The REF input pin is the positive input of the error amplifier. It
is internally connected to the DAC output through a 1kΩ
resistor. A cap acitor is used between the REF pin and gro und
to smooth the voltage transition during Dynamic VID
operations.

OFS

The OFS pin provides a means to program a DC current for
generating an offset voltage across the re sistor betwe en FB
and VDIFF. The offset current is generated via an external
resistor and precision internal voltage references. The polarity
of the offset is selected by connecting the resistor to GND or
VCC. For no offset, the OFS pin should be left unconnected.

ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, ISEN3+,
ISEN4-, and ISEN4+

These pins are used for differentially sensing the
corresponding channel output currents. The sensed currents
are used for channel balancing, protection, and load line
regulation.

Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node
between the RC sense elements surrounding the inductor of
their respective channel. Tie the ISEN+ pins to the VCORE
side of their corresponding channel’s sense capacitor.

UGATE1, UGATE2, and UGATE3

Connect these pins to the corresponding upper MOSFET
gates. These pins are used to control the upper MOSFETs
and are monitored for shoot-through prevention purposes.

BOOT1, BOOT2, and BOOT3

These pins provide the bias voltage for the corresponding
upper MOSFET drives. Connect these pins to
appropriately-chosen external bootstrap capacitors. Internal
bootstrap diodes connected to the PVCC pins provide the
necessary bootstrap charge.

PHASE1, PHASE2, and PHASE3

Connect these pins to the sources of the corresponding

10

upper MOSFETs. These pins are the return path for the
upper MOSFET drives.

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August 2, 2007

ISL6322ISL6322

LGATE1, LGATE2, and LGATE3

These pins are used to control the lower MOSFET s. Connect
these pins to the corresponding lower MOSFETs’ gates.

PWM4

Pulse-width modulation output. Connect this pin to the PWM
input pin of an Intersil driver IC if 4-phase operation is
desired.

EN_PH4

This pin has two functions. First, a resistor divider connected
to this pin will provide a POR power-up synch between the
on-chip and external driver. The resistor divider should be
designed so that when the POR-trip point of the external
driver is reached the voltage on this pin should be 1.21V.

The second function of this pin is disabling PWM4 for
3-phase operation. This can be accomplished by connecting
this pin to a +5V supply.

SS/RST/A0

This pin has three different functions associated with it. The
first is that a resistor (R

), placed from this pin to ground, or

SS

VCC, will set the soft-start ramp slope for the Intel DAC
modes of operation. Refer to Equations 18 and 19 for proper
resistor calculation.

The second function of this pin is that it selects which of the
two 8-bit Slave I

2

C addresses the controller will use.
Connecting the RSS resistor on this pin to ground will
choose slave address one(1000_110x), while connecting
this resistor to VCC will select slave address
two(1000_111x).

2

The third function of this pin is a reset to the I

C registers.
During normal operation of the part, if this pin is ever
grounded, all of the I2C registers are reset to 0000_0000. An
open drain device is recommended as the means of
grounding this pin for resetting the I

2

C registers.

SCL

Connect this pin to the clock signal for the I2C bus, which is
a logic level input signal. The clock signal tells the controller
when data is available on the I

2

C bus.

SDA

Connect this pin to the bidirectional data line of the I2C bus,
which is a logic level input/output signal. All I
over this line, including the address of the device the bus is
trying to communicate with, and what functions the device
should perform.

2

C data is sent

PGOOD

During normal operation PGOOD indicates whether the
output voltage is within specified overvolt age an d
undervoltage limits. If the output voltage exceed s these limit s
or a reset event occurs (such as an overcurrent event),
PGOOD is pulled low. PGOOD is always low prior to the end
of soft-start.

Operation

Multiphase Power Conversion

Microprocessor load current profiles have changed to the
point that using single-phase regulators is no longer a viable
solution. Designing a regulator that is cost-effective,
thermally sound, and efficient has become a challenge that
only multiphase converters can accomplish. The ISL6322
controller helps simplify implementation by integrating vital
functions and requiring minimal external components. The
“Block Diagram” on page 3 provides a top level view of
multiphase power conversion using the ISL6322 controller.

IL1 + IL2 + IL3, 7A/DIV

IL3, 7A/DIV

PWM3, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

IL1, 7A/DIV

PWM1, 5V/DIV

1μs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

Interleaving

The switching of each channel in a multiphase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the
peak-to-peak amplitude of the combined inductor currents is
reduced in proportion to the number of phases (Equations 1
and 2). Increased ripple frequency and lower ripple
amplitude mean that the designer can use less per-channel
inductance and lower total output capacitance for any
performance specification.

Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the DC components of the inductor currents
combine to feed the load.

11

FN6328.2

August 2, 2007

ISL6322ISL6322

T o understand the reduction of ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel peak-to-peak inductor current.

VINV

----------------------------------------------------------=

–()V

Lf

I

PP

In Equation 1, V

OUT

S

V⋅IN⋅

and V

IN

⋅

OUT

are the input and output

OUT

(EQ. 1)

voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.

The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.

VINNV

I

CP P–()

FIGURE 2. CHANNEL INPUT CURRENTS AND

------------------------------------------------------------------- -=

INPUT-CAPACITOR CURRENT, 10A/DIV

⋅–()V

Lf

CHANNEL 1
INPUT CURRENT
10A/DIV

INPUT-CAPACITOR RMS CURRENT FOR
3-PHASE CONVERTER

⋅

OUT

S

CHANNEL 2
INPUT CURRENT
10A/DIV

OUT

V⋅IN⋅

CHANNEL 3
INPUT CURRENT
10A/DIV

1μs/DIV

(EQ. 2)

Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.

must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter .

Active Pulse Positioning (APP) Modulated PWM
Operation

The ISL6322 uses a proprietary Active Pulse Positioning
(APP) modulation scheme to control the internal PWM
signals that command each channel’s driver to turn their
upper and lower MOSFETs on and off. The time interval in
which a PWM signal can occur is generated by an internal
clock, whose cycle time is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. The advantage of Intersil’s proprietary Active Pulse
Positioning (APP) modulator is that the PWM signal has the
ability to turn on at any point during this PWM time interval,
and turn off immediately after the PWM signal has
transitioned high. This is important because is allows the
controller to quickly respond to output voltage drops
associated with current load spikes, while avoiding the ring
back affects associated with other modulation schemes.

The PWM output state is driven by the position of the error
amplifier output signal, V
signal relative to the proprietary modulator ramp waveform
as illustrated in Figure 3. At the beginning of each PWM time
interval, this modified V
internal modulator waveform. As long as the modified
V

voltage is lower then the modulator waveform

COMP

voltage, the PWM signal is commanded low. The internal
MOSFET driver detects the low state of the PWM signal and
turns off the upper MOSFET and turns on the lower
synchronous MOSFET. When the modified V
crosses the modulator ramp, the PWM output transitions
high, turning off the synchronous MOSFET and turning on
the upper MOSFET. The PWM signal will remain high until
the modified V

voltage crosses the modulator ramp

COMP

again. When this occurs the PWM signal will transition low
again.

During each PWM time interval the PWM signal can only
transition high once. Once PWM transitions high it can not
transition high again until the beginning of the next PWM
time interval. This prevents the occurrence of double PWM
pulses occurring during a single period.

To further improve the transient response, ISL6322 also
implements Intersil’s proprietary Adaptive Phase Alignment
(APA) technique, which turns on all phases together under
transient events with large step current. With both APP and
APA control, ISL6322 can achieve excellent transient
performance and reduce the deman d on the output
capacitors.

, minus the current correction

COMP

signal is compared to the

COMP

COMP

voltage

The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS input capacitor current. The single-phase converter

12

Channel-Current Balance

One important benefit of multiphase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the

FN6328.2

August 2, 2007

expense of using expensive heat sinks and exotic magnetic
materials.

In order to realize the thermal advantage, it is important that
each channel in a multiphase converter be controlled to
carry equal amounts of current at any load level. To achieve
this, the currents through each channel must be sampled
every switching cycle. The sampled currents, I

, from each

n

active channel are summed together and divided by the
number of active channels. The resulting cycle average
current, I

, provides a measure of the total load-current

AVG

demand on the converter during each switching cycle.
Channel-current balance is achieved by comparing the
sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current­balance method is illustrated in Figure 3, with error
correction for Channel 1 represented. In the figure, the cycle
average current, I
sample, I

, to create an error signal IER.

1

, is compared with the Channel 1

AVG

The filtered error signal modifies the pulse width
commanded by V
I

toward zero. The same method for error signal

ER

to correct any unbalance and force

COMP

correction is applied to each active channel.

V

COMP

FILTER

+

I

AVG

-

MODULATOR

RAMP

WAVEFORM

÷ N

-

f(s)

I

ER

+

PWM1

+

-

Σ

I

4

I

3

I

2

TO GATE

CONTROL

LOGIC

ISL6322

PWM

SWITCHING PERIOD

I

L

I

SEN

TIME

FIGURE 4. CONTINUOUS CURRENT SAMPLING

The ISL6322 supports inductor DCR current sensing to
continuously sense each channel’s current for
channel-current balance. The internal circuitry, shown in
Figure 5 represents Channel N of an N-Channel converter.
This circuitry is repeated for each channel in the converter,
but may not be active depending on how many channels are
operating.

Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 5. The channel current
I

, flowing through the inductor, passes through the DCR.

L

Equation 3 shows the s-domain equivalent voltage, V

,

L

across the inductor.

I

1

Note: Channel 3 and 4 are optional

FIGURE 3. CHANNEL-1 PWM FUNCTION AND

CURRENT-BALANCE ADJUSTMENT

Continuous Current Sampling

In order to realize proper current-balance, the currents in
each channel are sensed continuously every switching
cycle. During this time the current-sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
inductor current, I
scaled version of the inductor current.

. This sensed current, I

L

13

, is simply a

SEN

and C)

1

(EQ. 3)

VLs() ILsL DCR+⋅()⋅=

A simple R-C network across the inductor (R
extracts the DCR voltage, as shown in Figure 5. The voltage
across the sense capacitor, V
proportional to the channel current I

sL⋅

⎛⎞

-------------

⎝⎠

s()

C

--------------------------------------

sR

V

1+

DCR

C⋅⋅ 1+()

1

, can be shown to be

C

L

⋅⋅=

DCR I

L

, shown in Equation 4.

(EQ. 4)

In some cases it may be necessary to use a resistor divider
R-C network to sense the current through the inductor. This
can be accomplished by placing a second resistor, R

,

2

across the sense capacitor. In these cases the voltage
across the sense capacitor , V
channel current I

, and the resistor divider ratio, K.

L

, becomes proportional to the

C

FN6328.2

August 2, 2007