intersil ISL6308 DATA SHEET

®

ISL6308

Data Sheet October 19, 2005

Three-Phase Buck PWM Controller with
High Current Integrated MOSFET Drivers

The ISL6308 is a three-phase PWM control IC with
integrated MOSFET drivers. It provides a precision voltage
regulation system for multiple applications including, but not
limited to, high current low voltage point-of-load converters,
embedded applications and other general purpose low
voltage medium to high current applications.The integration
of power MOSFET drivers into the controller IC marks a
departure from the separate PWM controller and driver
configuration of previous multi-phase product families. By
reducing the number of external parts, this integration allows
for a cost and space saving power management solution.

Output voltage can be programmed using the on-chip DAC
or an external precision reference. A two bit code programs
the DAC reference to one of 4 possible values (0.6V,

0.9V,1.2V and 1.5V). A unity gain, differential amplifier is
provided for remote voltage sensing, compensating for any
potential difference between remote and local grounds. The
output voltage can also be offset through the use of single
external resistor. An optional droop function is also
implemented and can be disabled for applications having
less stringent output voltage variation requirements or
experiencing less severe step loads.

A unique feature of the ISL6308 is the combined use of both
DCR and r
positioning and overcurrent protection are accomplished
through continuous inductor DCR current sensing, while
r

current sensing is used for accurate channel-current

DS(ON)

balance. Using both methods of current sampling utilizes the
best advantages of each technique.

Protection features of this controller IC include a set of
sophisticated overvoltage and overcurrent protection.
Overvoltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the load. An OVP output is also provided to drive an optional
crowbar device. The overcurrent protection level is set
through a single external resistor. Other protection features
include protection against an open circuit on the remote
sensing inputs. Combined, these features provide advanced
protection for the output load.

current sensing. Load line voltage

DS(ON)

FN9208.2

Features

• Integrated Multi-Phase Power Conversion

- 1, 2, or 3 Phase Operation

• Precision Output Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.8% System Accuracy Over Temperature
(for REF=0.6V and 0.9V)

- ±0.5% System Accuracy Over Temperature
(for REF=1.2V and 1.5V)

- Usable for output voltages not exceeding 2.3V

- Adjustable Reference-Voltage Offset

• Precision Channel Current Sharing

- Uses Loss-Less r

DS(ON)

Current Sampling

• Optional Load Line (Droop) Programming

- Uses Loss-Less Inductor DCR Current Sampling

• Variable Gate-Drive Bias - 5V to 12V

• Internal or External Reference Voltage Setting

- On-Chip Adjustable Fixed DAC Reference voltage with
2-bit Logic Input Selects from Four Fixed Reference
Voltages (0.6V, 0.9V, 1.2V, 1.5V)

- Reference can be Changed Dynamically

- Can use an External Voltage Reference

• Overcurrent Protection

• Multi-tiered Overvoltage Protection

- OVP Pin to Drive Optional Crowbar Device

• Selectable Operation Frequency up to 1.5MHz per phase

• Digital Soft-Start

• Capable of Start-up in a Pre-Biased Load

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• High Current DDR/Chipset core voltage regulators

• High Current, Low voltage DC/DC converters

• High Current, Low voltage FPGA/ASIC DC/DC converters

Ordering Information

PART NUMBER* PART MARKING TEMERATURE (°C) PACKAGE PKG. DWG. #

ISL6308CRZ (Note) ISL6308CRZ 0 to 70 40 Ld 6x6 QFN (Pb-free) L40.6x6

ISL6308IRZ (Note) ISL6308IRZ -40 to 85 40 Ld 6x6 QFN (Pb-free) L40.6x6

ISL6308EVAL1 Evaluation Platform

* Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005. All Rights Reserved

Pinout

ISL6308

ISL6308 (6x6 QFN)

TOP VIEW

REF1

OVP

REF0

40

39 38 37 36 35 34 33 32 31

ENLL

FS

PGOOD

LGATE1

PVCC1

ISEN1

UGATE1

3PH

2PH

DAC

REF

OFST

VCC

COMP

FB

VDIFF

RGND

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

VSEN

ICOMP

OCSET

GND

ISUM

DROOP

41

IREF

LGATE3

PVCC3

ISEN3

BOOT1

30

PHASE1

29

PHASE2

28

27

UGATE2

26

BOOT2

ISEN2

25

PVCC2

24

LGATE2

23

PHASE3

22

21

BOOT3

UGATE3

2

FN9208.2

October 19, 2005

Block Diagram

ISL6308

ISUM

IREF

RGND

VSEN

VDIFF

ICOMP

ISEN AMP

x1

DROOP OVP

x1

UVP

OVP

OVP

OCSET

100µA

OC

+1V

SOFT-START

AND

FAULT LOGIC

0.2V

CLOCK AND

SAWTOOTH

GENERATOR

PGOOD

0.66V

GATE

CONTROL

LOGIC

ENLL

POWER-ON

PROTECTION

RESET

SHOOT-

THROUGH

VCC

PVCC1

BOOT1

UGATE1

PHASE1

LGATE1

FS

PVCC2

BOOT2

REF1

REF0

DAC

REF

FB

COMP

OFST

+150mV

DAC

OFFSET

x 0.82

E/A

∑

∑

∑

CHANNEL
CURRENT
BALANCE

CHANNEL
CURRENT

SENSE

PWM1

PWM2

PWM3

UGATE2

GATE

CONTROL

LOGIC

CHANNEL

DETECT

1
N

GATE

CONTROL

∑

LOGIC

SHOOT-

THROUGH

PROTECTION

SHOOT-

THROUGH

PROTECTION

PHASE2

LGATE2

2PH

3PH

PVCC3

BOOT3

UGATE3

PHASE3

LGATE3

ISEN1 ISEN2 ISEN3

3

GND

FN9208.2

October 19, 2005

Typical Application - ISL6308

VDIFF

VSEN

RGND

FB

COMP

ISL6308

+12V

PVCC1

BOOT1

UGATE1

+5V

3PH
2PH

VCC

OFST

FS

DAC

REF

REF1

REF0

OVP
PGOOD

ISL6308

PHASE1

ISEN1

LGATE1

PVCC2

BOOT2

UGATE2

PHASE2

ISEN2

LGATE2

PVCC3

+12V

LOAD

+12V

+12V

GND

ENLL

IREF

DROOP
OCSET

BOOT3

UGATE3

PHASE3

ISEN3

ISUMICOMP

4

LGATE3

FN9208.2

October 19, 2005

ISL6308

Absolute Maximum Ratings

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V

Absolute Boot Voltage, V
Phase Voltage, V

GND - 8V (<400ns, 20µJ) to 24V (<200ns, V

Upper Gate Voltage, V

V

Lower Gate Voltage, V

PHASE

UGATE

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

LGATE

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V

. . . . . . . . GND - 0.3V to GND + 36V

BOOT

. . . . . . . . GND - 0.3V to 15V (PVCC = 12)

BOOT
BOOT

= 12V)
+ 0.3V
+ 0.3V

. . . . V

PHASE

BOOT-PHASE

- 0.3V to V

. . . . . . . . GND - 0.3V to PVCC + 0.3V

Thermal Information

Thermal Resistance θJA (°C/W) θJC (°C/W)

QFN Package (Notes 1, 2). . . . . . . . . . 32 3.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD

Recommended Operating Conditions

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%

Ambient Temperature (ISL6308CRZ) . . . . . . . . . . . . . . 0°C to 70°C

Ambient Temperature (ISL6308IRZ) . . . . . . . . . . . . . . -40°C to 85°C

CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

JA

Tech Brief TB379.

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

BIAS SUPPLY AND INTERNAL OSCILLATOR

Input Bias Supply Current I

Gate Drive Bias Current I

VCC POR (Power-On Reset) Threshold VCC Rising 4.25 4.38 4.50 V

PVCC POR (Power-On Reset) Threshold PVCC Rising 4.25 4.38 4.50 V

Oscillator Ramp Amplitude (Note 3) V

Maximum Duty Cycle (Note 3) - 66.6 - %

CONTROL THRESHOLDS

ENLL Rising Threshold -0.66-V

ENLL Hysteresis - 100 - mV

COMP Shutdown Threshold COMP Falling 0.1 0.25 0.4 V

REFERENCE AND DAC

System Accuracy (DAC = 0.6V, 0.9V) DROOP connected to IREF -0.8 - 0.8 %

System Accuracy (DAC = 1.2V, 1.50V) DROOP connected to IREF -0.5 - 0.5 %

DAC Input Low Voltage (REF0, REF1) - - 0.4 V

DAC Input High Voltage (REF0, REF1) 0.8 - - V

External Reference (Note 3) 0.6 1.75 V

OFS Sink Current Accuracy (Negative Offset) R

OFS Source Current Accuracy (Positive Offset) R

; ENLL = high - 15 20 mA

VCC

; ENLL = high; all gate outputs open,

PVCC

F

= 250kHz

sw

- 0.8 2.00 mA

VCC Falling 3.75 3.88 4.00 V

PVCC Falling 3.75 3.88 4.00 V

PP

= 30kΩ from OFS to VCC 47.5 50.0 52.5 µA

OFS

= 10kΩ from OFS to GND 47.5 50.0 52.5 µA

OFS

-1.50-V

5

FN9208.2

October 19, 2005

ISL6308

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ERROR AMPLIFIER

DC Gain (Note 3) R

Gain-Bandwidth Product (Note 3) C

Slew Rate (Note 3) C

Maximum Output Voltage Load = 1mA 3.90 4.20 - V

Minimum Output Voltage Load = -1mA - 0.85 1.0 V

REMOTE SENSE DIFFERENTIAL AMPLIFIER

Input Bias Current (VSEN) (VSEN = 1.5V) 49 55 60 µA

Bandwidth (Note 3) -20-MHz

Slew Rate (Note 3) -8-V/µs

OVERCURRENT PROTECTION

OCSET trip current 93 100 107 µA

OCSET Accuracy OC comparator offset (OCSET and ISUM Difference) -5 0 5 mV

ICOMP Offset ISEN amplifier offset -5 0 5 mV

PROTECTION

Undervoltage Threshold VSEN falling 80 82 84 %VID

Undervoltage Hysteresis VSEN Rising - 3 - %VID

Overvoltage Threshold while IC Disabled 1.62 1.67 1.72 V

Overvoltage Threshold VSEN Rising DAC +

Overvoltage Hysteresis VSEN Falling - 50 - mV

Open Sense-Line Protection Threshold IREF Rising and Falling VDIFF

OVP Output High Drive Voltage I

SWITCHING TIME

UGATE Rise Time (Note 3) t

LGATE Rise Time (Note 3) t

UGATE Fall Time (Note 3) t

LGATE Fall Time (Note 3) t

UGATE Turn-On Non-overlap (Note 3) t

LGATE Turn-On Non-overlap (Note 3) t

GATE DRIVE RESISTANCE (Note 3)

Upper Drive Source Resistance V

Upper Drive Sink Resistance V

Lower Drive Source Resistance V

Lower Drive Sink Resistance V

OVER TEMPERATURE SHUTDOWN

Thermal Shutdown Setpoint (Note 3) - 160 - °C

Thermal Recovery Setpoint (Note 3) - 100 - °C

NOTE:

3. Parameter magnitude guaranteed by design. Not 100% tested.

= 10K to ground - 96 - dB

L

= 100pF, RL = 10K to ground - 20 - MHz

L

= 100pF, Load = ±400µA-8-V/µs

L

125mV

DAC +

150mV

DAC +

175mV

VDIFF + 1VVDIFF

+ 0.9V

= 50mA, VCC = 5V 2.2 3.9 V

OVP

RUGATE; VPVCC

RLGATE; VPVCC

FUGATE; VPVCC

FLGATE; VPVCC

PDHUGATE

PDHLGATE

= 12V, 150mA Source Current 1.25 2.0 3.0 Ω

PVCC

= 12V, 150mA Sink Current 0.9 1.6 3.0 Ω

PVCC

= 12V, 150mA Source Current 0.85 1.4 2.2 Ω

PVCC

= 12V, 150mA Sink Current 0.60 0.94 1.35 Ω

PVCC

= 12V, 3nF Load, 10% to 90% - 26 - ns

= 12V, 3nF Load, 10% to 90% - 18 - ns

= 12V, 3nF Load, 90% to 10% - 18 - ns

= 12V, 3nF Load, 90% to 10% - 12 - ns

; V

= 12V, 3nF Load, Adaptive - 10 - ns

PVCC

; V

= 12V, 3nF Load, Adaptive - 10 - ns

PVCC

+ 1.1V

V

V

6

FN9208.2

October 19, 2005

Timing Diagram

UGATE

LGATE

t

PDHUGATE

t

RUGATE

ISL6308

t

FUGATE

t

FLGATE

Simplified Power System Diagram

+12V

IN

+5V

IN

REF0,REF1

ENLL

OVP

PGOOD

2

DAC

ISL6308

CHANNEL1

CHANNEL2

t

PDHLGATE

Q1

Q2

Q3

Q4

Q5

t

RLGATE

V

OUT

Functional Pin Description

VCC (Pin 6)

Bias supply for the IC’s small-signal circuitry. Connect this
pin to a +5V supply and locally decouple using a quality

1.0µF ceramic capacitor.

PVCC1, PVCC2, PVCC3 (Pins 33, 24, 18)

Power supply pins for the corresponding channel MOSFET
drive. These pins can be connected to any voltage from +5V
to +12V, depending on the desired MOSFET gate drive level.
Note that tying PVCC2 OR PVCC3 to GND has the same
effect as tying 2PH or 3PH to GND for disabling the
corresponding phase

GND (Pin 41)

Bias and reference ground for the IC.

7

CHANNEL3

Q6

ENLL (Pin 37)

This pin is a threshold sensitive (approximately 0.66V) enable
input for the controller. Held low, this pin disables controller
operation. Pulled high, the pin enables the controller for
operation.

FS (Pin 36)

A resistor, placed from FS to ground, will set the switching
frequency. Refer to Equation (33) and Figure 23 for proper
resistor calculation

3PH and 2PH (Pins 1, 2)

These pins decide how many phases the controller will
operate. Tying both pins to VCC allows for 3-phase operation .
Tying the 3PH pin to GND causes the controller to operate in
2-phase mode, while connecting both 3PH and 2PH GND will
allow for single phase operation.

FN9208.2

October 19, 2005

ISL6308

REF0 and REF1 (Pins 40, 39)

These pins make up the 2-bit input that selects the fixed
DAC reference voltage. These pins respond to TTL logic
thresholds. The ISL6308 decodes these inputs to establish
one of four fixed reference voltages; see “Table 1” for
correspondence between REF0 and REF1 inputs and
reference voltage settings.

These pins are internally pulled high, to approximately 1.2V,
by 40µA (typically) internal current sources; the internal pull­up current decreases to 0 as the REF0 and REF1 voltages
approach the internal pull-up voltage. Both REF0 and REF1
pins are compatible with external pull-up voltages not
exceeding the IC’s bias voltage (VCC).

RGND and VSEN (Pins 10, 11)

RGND and VSEN are inputs to the precision differential
remote-sense amplifier and should be connected to the
sense pins of the remote load.

ICOMP, ISUM, and IREF (Pins 13, 15, 16)

ISUM, IREF, and ICOMP are the DCR current sense
amplifier’s negative input, positive input, and output
respectively. For accurate DCR current sensing, connect a
resistor from each channel’s phase node to ISUM and
connect IREF to the summing point of the output inductors.
A parallel R-C feedback circuit connected between ISUM
and ICOMP will then create a voltage from IREF to ICOMP
proportional to the voltage drop across the inductor DCR.
This voltage is referred to as the droop voltage and is added
to the differential remote-sense amplifier’s output.

An optional 0.001-0.01µF ceramic capacitor can be placed
from the IREF pin to the ISUM pin to help reduce common
mode noise that might be introduced by the layout.

DROOP (Pin 14)

This pin enables or disables droop. Tie this pin to the ICOMP
pin to enable droop. To disable droop, tie this pin to the IREF
pin.

VDIFF (Pin 9)

VDIFF is the output of the differential remote-sense
amplifier. The voltage on this pin is equal to the difference
between VSEN and RGND added to the difference between
IREF and ICOMP. VDIFF therefore represents the VOUT
voltage plus the droop voltage.

FB and COMP (Pin 7, 8)

The internal error amplifier’s inverting input and output
respectively. FB is connected to VDIFF through an external
R or R-C network depending on the desired type of
compensation (Type II or III). COMP is tied back to FB
through an external R-C network to compensate the
regulator.

DAC (Pin 3)

The DAC pin is the direct output of the internal DAC. This pin
is connected to the REF pin using a 1-5kΩ resistor. This pin
can be left open if an external reference is used.

REF (Pin 4)

The REF input pin is the positive input of the error amplifier.
This pin can be connected to the DAC pin using a resistor
(1-5kΩ) when the internal DAC voltage is used as the
reference voltage. When an external voltage reference is
used, it must be connected directly to the REF pin, while the
DAC pin is left unconnected. The output voltage will be
regulated to the voltage at the REF pin unless this voltage
is greater than the voltage at the DAC pin. If an external
reference is used at this pin, its magnitude cannot exceed

1.75V.

A capacitor is used between the REF pin and ground to
smooth the DAC voltage during soft-start.

OFST (Pin 5)

The OFST pin provides a means to program a DC current for
generating an offset voltage across the resistor between FB
and VDIFF. The offset current is generated via an external
resistor and precision internal voltage references. The
polarity of the offset is selected by connecting the resistor to
GND or VCC. For no offset, the OFST pin should be left
unconnected.

OCSET (Pin 12)

This is the overcurrent set pin. Placing a resistor from OCSET
to ICOMP, allows a 100µA current to flow out of this pin,
producing a voltage reference. Internal circuitry compares the
voltage at OCSET to the voltage at ISUM, and if ISUM ever
exceeds OCSET, the overcurrent protection activates.

ISEN1, ISEN2 and ISEN3 (Pins 32, 25, 19)

These pins are used for balancing the channel currents by
sensing the current through each channel’s lower MOSFET
when it is conducting. Connect a resistor between the
ISEN1, ISEN2, and ISEN3 pins and their respective phase
node. This resistor sets a current proportional to the current
in the lower MOSFET during its conduction interval.

UGATE1, UGATE2, and U G AT E 3 ( P i n s 31, 27, 20)

Connect these pins to the upper MOSFETs’ gates. These
pins are used to control the upper MOSFETs and are
monitored for shoot-through prevention purposes. Maximum
individual channel duty cycle is limited to 66%.

BOOT1, BOOT2, and BOOT3 (Pins 30, 26, 21)

These pins provide the bias voltage for the upper MOSFETs’
drives. Connect these pins to appropriately-chosen external
bootstrap capacitors. Internal bootstrap diodes connected to
the PVCC pins provide the necessary bootstrap charge.

PHASE1, PHASE2, and PHASE3 (Pins 29, 28, 22)

Connect these pins to the sources of the upper MOSFETs.

8

These pins are the return path for the upper MOSFETs’
drives.

FN9208.2

October 19, 2005

ISL6308

LGATE1, LGATE2, and LGATE3 (Pins 34, 23, 17)

These pins are used to control the lower MOSFETs and are
monitored for shoot-through prevention purposes. Connect
these pins to the lower MOSFETs’ gates. Do not use
external series gate resistors as this might lead to shoot­through.

PGOOD (Pin 35)

PGOOD is used as an indication of the end of soft-start. It is
an open-drain logic output that is low impedance until the
soft-start is completed and VOUT is equal to the VID setting.
Once in normal operation PGOOD indicates whether the
output voltage is within specified overvoltage and
undervoltage limits. If the output voltage exceeds these limits
or a reset event occurs (such as an overcurrent event),
PGOOD becomes high impedance again. The potential at
this pin should not exceed that of the potential at VCC pin by
more than a typical forward diode drop at any time.

OVP (Pin 38)

Overvoltage protection pin. This pin pulls to VCC when an
overvoltage condition is detected. Connect this pin to the
gate of an SCR or MOSFET tied across V
prevent damage to a load device.

and ground to

IN

combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the dc components of the inductor currents
combine to feed the load.

IL1 + IL2 + IL3, 7A/DIV

I

, 7A/DIV

L3

PWM3, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

IL1, 7A/DIV

PWM1, 5V/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

Operation

Multi-Phase Power Conversion

Modern low voltage DC/DC converter load current profiles
have changed to the point that the advantages of multi­phase power conversion are impossible to ignore. The
technical challenges associated with producing a single­phase converter that is both cost-effective and thermally
viable have forced a change to the cost-saving approach of
multi-phase. The ISL6308 controller helps simplify
implementation by integrating vital functions and requiring
minimal output components. The block diagram on page 3
provides a top level view of multi-phase power conversion
using the ISL6308 controller.

Interleaving

The switching of each channel in a multi-phase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-to­peak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.

Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (I

, IL2, and IL3)

L1

To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine the equation representing an
individual channel peak-to-peak inductor current.

VINV

----------------------------------------------------------=
LF

–()V

I

PP

In Equation 1, V

⋅

OUT

⋅⋅

SWVIN

and V

IN

OUT

are the input and output

OUT

(EQ. 1)

voltages respectively, L is the single-channel inductor value,
and F

is the switching frequency.

SW

The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.

VINNV

I

------------------------------------------------------------- -------=

CPP,

⋅–()V

LF

⋅

SW

OUT

⋅

OUT

V⋅

IN

(EQ. 2)

Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input

9

FN9208.2

October 19, 2005