Intersil ISL62883CHRTZ, ISL62883CIRTZ Schematic [ru]

Multiphase PWM Regulator for IMVP-6.5™ Mobile
CPUs and GPUs

ISL62883C

ISL62883C

The ISL62883C is a multiphase PWM buck regulator for
miroprocessor or graphics processor core power supply.
The multiphase buck converter uses interleaved phase to
reduce the total output voltage ripple with each phase
carrying a portion of the total load current, providing
better system performance, superior thermal
management, lower component cost, reduced power
dissipation, and smaller implementation area. The
ISL62883C uses two integrated gate drivers and an
external gate driver to provide a complete solution. The
PWM modulator is based on Intersil's Robust Ripple
Regulator (R
modulators, the R3™ modulator commands variable
switching frequency during load transients, achieving
faster transient response. With the same modulator, the
switching frequency is reduced at light load, increasing
the regulator efficiency.

The ISL62883C can be configured as CPU or graphics
Vcore controller and is fully compliant with IMVP-6.5™
specifications. It responds to PSI# and DPRSLPVR signals
by adding or dropping PWM3 and Phase 2 respectively,
adjusting overcurrent protection threshold accordingly,
and entering/exiting diode emulation mode. It reports
the regulator output current through the IMON pin. It
senses the current by using either discrete resistor or
inductor DCR whose variation over temperature can be
thermally compensated by a single NTC thermistor. It
uses differential remote voltage sensing to accurately
regulate the processor die voltage. The adaptive body
diode conduction time reduction function minimizes
the body diode conduction loss in diode emulation
mode. User-selectable overshoot reduction function
offers an option to aggressively reduce the output
capacitors as well as the option to disable it for users
concerned about increased system thermal stress. In
2-Phase configuration, the ISL62883C offers the FB2
function to optimize 1-Phase performance.

3

) technology™. Compared with traditional

Features

• Programmable 1, 2- or 3-Phase CPU or GPU Mode of
Operation

• Precision Multiphase Core Voltage Regulation

- 0.5% System Accuracy Over-Temperature

- Enhanced Load Line Accuracy

• Microprocessor Voltage Identification Input

- 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps

- Supports VID Changes On-The-Fly

• Supports Multiple Current Sensing Methods

- Lossless Inductor DCR Current Sensing

- Precision Resistor Current Sensing

• Supports PSI# and DPRSLPVR modes

• Superior Noise Immunity and Transient Response

• Current Monitor and Thermal Monitor

• Differential Remote Voltage Sensing

• High Efficiency Across Entire Load Range

• Two Integrated Gate Drivers

• Excellent Dynamic Current Balance

• FB2 Function Optimizes 1-Phase Mode Performance

• Adaptive Body Diode Conduction Time Reduction

• User-selectable Overshoot Reduction Function

• Small Footprint 40 Ld 5x5 TQFN Packages

• Pb-Free (RoHS Compliant)

Applications*(see page 42)

• Notebook Core Voltage Regulator

• Notebook GPU Voltage Regulator

Related Literature*(see page 42)

•See AN1460 for ISL62883/ISL62883C Evaluation
Board Application Note “ISL62883EVAL2Z User
Guide”

Load Line Regulation

(V)

OUT

V

March 18, 2010
FN7557.1

1

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92
0 5 10 15 20 25 30 35 40 45 50 55 60 65

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

VIN = 8V

VIN = 12V

VIN = 19V

I

(A)

OUT

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2009, 2010. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

ISL62883C

Ordering Information

PART NUMBER

(Note 3) PART MARKING

ISL62883CIRTZ (Note 2) 62883C IRTZ -40 to +100 40 Ld 5x5 TQFN L40.5x5

ISL62883CIRTZ-T (Notes 1, 2) 62883C IRTZ -40 to +100 40 Ld 5x5 TQFN L40.5x5

ISL62883CHRTZ (Note 2) 62883C HRTZ -10 to +100 40 Ld 5x5 TQFN L40.5x5

ISL62883CHRTZ-T (Notes 1, 2) 62883C HRTZ -10 to +100 40 Ld 5x5 TQFN L40.5x5

NOTES:

1. Please refer to TB347

for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62883C
see techbrief TB363

.

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

. For more information on MSL please

Pin Configuration

ISL62883C

(40 LD TQFN)

TOP VIEW

R
V
P

N

L
S

O

R

_

P

R

D

V

39 38 37 36 35 34 33 32 31

6

4

5

D

D

D

I

I

I

V

V

V

GND PAD

(BOTTOM)

1

2

3

D

D

D

I

I

I

V

V

V

0
D

I
V

30

29

28

27

26

25

24

23

22

21

BOOT2

UGATE2

PHASE2

VSSP2

LGATE2

VCCP

PWM3

LGATE1

VSSP1

PHASE1

PGOOD

PSI#

RBIAS

VR_TT#

NTC

VW

COMP

FB

ISEN3/FB2

ISEN2

#
N

E
_
K
L
C

40

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

RTN

VSEN

ISEN1

ISUM-

2

VIN

VDD

IMON

ISUM+

BOOT1

UGATE1

FN7557.1

March 18, 2010

ISL62883C

Functional Pin Descriptions

ISL62883C SYMBOL DESCRIPTION

- GND Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.

1 PGOOD Power-Good open-drain output indicating when the regulator is able to supply regulated

2 PSI# Low load current indicator input. When asserted low, indicates a reduced load-current condition.

3 RBIAS A resistor to GND sets internal current reference. Use 147kΩ or 47kΩ. The choice of Rbias value,

4 VR_TT# Thermal overload output indicator.

5NTCThermistor input to VR_TT# circuit.

6 VW A resistor from this pin to COMP programs the switching frequency (8kΩ gives approximately

7 COMP This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the

8 FB This pin is the inverting input of the error amplifier.

9 INSE3/FB2 When the ISL62883C is configured in 3-phase mode, this pin is ISEN3. ISEN3 is the individual

10 ISEN2 Individual current sensing for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will

11 ISEN1 Individual current sensing for phase 1.

12 VSEN Remote core voltage sense input. Connect to microprocessor die.

13 RTN Remote voltage sensing return. Connect to ground at microprocessor die.

14, 15 ISUM- and

ISUM+

16 VDD 5V bias power.

17 VIN Battery supply voltage, used for feed-forward.

18 IMON An analog output. IMON outputs a current proportional to the regulator output current.

19 BOOT1 Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is

20 UGATE1 Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the

21 PHASE1 Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to

22 VSSP1 Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to the

23 LGATE1 Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the

24 PWM3 PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase-3

voltage. Pull up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.

together with the ISEN2 pin configuration and the external resistance from the COMP pin to
GND, programs the controller to enable/disable the overshoot reduction function and to select
the CPU/GPU mode.

300kHz).

overcurrent threshold.

current sensing for phase 3. When the ISL62883C is configured in 2-phase mode, this pin is
FB2. There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode
and is off in 1-phase mode. The components connecting to FB2 are used to adjust the
compensation in 1-phase mode to achieve optimum performance.

disable Phase 2.

Droop current sense input.

charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each
time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot
diode.

Phase-1 high-side MOSFET.

the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-1.

source of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallel
with the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1 low­side MOSFETs.

Phase-1 low-side MOSFET.

and allow other phases to operate.

3

FN7557.1

March 18, 2010

ISL62883C

Functional Pin Descriptions (Continued)

ISL62883C SYMBOL DESCRIPTION

25 VCCP Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at

least 1µF of an MLCC capacitor to VSSP1 and VSSP2 pins respectively.

26 LGATE2 Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of the

Phase-2 low-side MOSFET.

27 VSSP2 Current return path for the Phase-2 converter low-side MOSFET gate driver. Connect the VSSP2

28 PHASE2 Current return path for the Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to

29 UGATE2 Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of the

30 BOOT2 Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is

31 thru 37 VID0 thru

VID6

38 VR_ON Voltage regulator enable input. A high level logic signal on this pin enables the regulator.

39 DPRSLPVR Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor

40 CLK_EN# Open drain output to enable system PLL clock. It goes low 13 switching cycles after Vcore is

pad BOTTOM The bottom pad of ISL62883C is electrically connected to the GND pin inside the IC.It should

pin to the source of the Phase-2 low-side MOSFET through a low impedance path, preferably in
parallel with the trace connecting the LGATE2 pin to the gate of the Phase-2 low-side MOSFET.

the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-2.

Phase-2 high-side MOSFET.

charged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each
time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot
diode.

VID input with VID0 = LSB and VID6 = MSB.

is in deeper sleep mode.

within 10% of Vboot.

also be used as the thermal pad for heat removal.

4

FN7557.1

March 18, 2010

Block Diagram

Σ

VR_ON

PSI#

DPRSLPVR

RBIAS

VID0

VID1

VID2

VID3

VID4

MODE

CONTROL

DAC
AND

SOFT-

START

VIN

VSEN

ISEN1 ISEN3 ISEN2

IBAL2
IBAL3
IBAL1

VIN

CLOCK

VDAC

COMP VW

ISL62883C

PGOOD CLK_EN#

CURRENT
BALANCE

IBAL

PROTECTION

WOC OC

FLT

IBAL2 VIN VDAC

MODULATOR

COMP

PGOOD &

CLK_EN#

LOGIC

6µA

54µA

SHOOT-THROUGH

PROTECTION

PWM CONTROL LOGIC

1.20V

1.24V

DRIVER

DRIVER

VDD

VR_TT#

NTC

BOOT2

UGATE2

PHASE2

LGATE2

VID5

VID6

RTN

FB

COMP

VW

IMON

ISUM+

ISUM-

IBAL3 VIN VDAC

+

+

IDROOP

IMON

+

_

CURRENT

SENSE

Σ

+

E/A

_

+

WOC

_

2.5X

CURRENT
COMPARATORS

+

OC

_

MODULATOR

COMP

IBAL1 VIN VDAC

MODULATOR

COMP

NUMBER OF

PHASES

GAIN

SELECT

60µA

+

PWM CONTROL LOGIC

+

DRIVER

SHOOT-THROU GH

PROTECTION

DRIVER

ADJ. OCP

THRESHOLD

COMP

VSSP2

PWM3

BOOT1

UGATE1

PHASE1

VCCP

LGATE1

VSSP1

GND

5

FN7557.1

March 18, 2010

ISL62883C

Table of Contents

Ordering Information ......................................................................................................................... 2

Pin Configuration ................................................................................................................................ 2

Functional Pin Descriptions ................................................................................................................ 3

Block Diagram .................................................................................................................................... 5

Table of Contents ............................................................................................................................... 6

Absolute Maximum Ratings ................................................................................................................ 7

Thermal Information .......................................................................................................................... 7

Recommended Operating Conditions .................................................................................................. 7

Electrical Specifications ...................................................................................................................... 7

Gate Driver Timing Diagram ............................................................................................................. 10

Simplified Application Circuits .......................................................................................................... 10

Theory of Operation .......................................................................................................................... 13

Diode Emulation and Period Stretching ............................................................................................... 14

Start-up Timing .............................................................................................................................. 15

Voltage Regulation and Load Line Implementation ............................................................................... 15

Differential Sensing ......................................................................................................................... 17

Phase Current Balancing .................................................................................................................. 18

Modes of Operation ......................................................................................................................... 20

Dynamic Operation .......................................................................................................................... 20

Protections ..................................................................................................................................... 21

FB2 Function .................................................................................................................................. 22

Adaptive Body Diode Conduction Time Reduction ................................................................................. 22

Overshoot Reduction Function ........................................................................................................... 22

Key Component Selection ................................................................................................................. 23

R

Inductor DCR Current-Sensing Network ............................................................................................. 23

Resistor Current-Sensing Network .................................................................................................... 25

Overcurrent Protection..................................................................................................................... 25

Current Monitor .............................................................................................................................. 26

Compensator .................................................................................................................................. 27

Optional Slew Rate Compensation Circuit For 1-Tick VID Transition ........................................................ 29

Voltage Regulator Thermal Throttling ................................................................................................. 30

Current Balancing ........................................................................................................................... 30

Layout Guidelines ............................................................................................................................. 30

1-PHASE GPU Application Reference Design Bill of Materials ............................................................ 34

2-PHASE CPU Application Reference Design Bill of Materials ............................................................ 35

Typical Performance ......................................................................................................................... 37

Products ........................................................................................................................................... 42

Package Outline Drawing ................................................................................................................. 43

............................................................................................................................................ 23

BIAS

6

FN7557.1

March 18, 2010

ISL62883C

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . .-0.3V to +7V

Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . +28V

Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . -0.3V to +33V

Boot to Phase Voltage (BOOT-PHASE) . . . . -0.3V to +7V(DC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)

Phase Voltage (PHASE) . . . . . -7V (<20ns Pulse Width, 10µJ)

UGATE Voltage (UGATE) . . . . . . . PHASE-0.3V (DC) to BOOT

. . . . . . . . . PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT

LGATE Voltage

. . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V

All Other Pins. . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)

Open Drain Outputs, PGOOD, VR_TT#,

CLK_EN# . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.

NOTE:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”

4. θ

JA

features. See Tech Brief TB379.

5. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance (Typical) θ

(°C/W) θJC (°C/W)

JA

40 Ld TQFN Package (Notes 4, 5). . 31 2

Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range . . . -65°C to +150°C
Maximum Junction Temperature (Plastic Package). . . +150°C

Storage Temperature Range . . . . . . . . . . . -65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . +4.5V to 25V

Ambient Temperature

ISL62883CHRTZ. . . . . . . . . . . . . . . . . . -10°C to +100°C

ISL62883CIRTZ . . . . . . . . . . . . . . . . . . -40°C to +100°C

Junction Temperature

ISL62883CHRTZ. . . . . . . . . . . . . . . . . . -10°C to +125°C

ISL62883CIRTZ . . . . . . . . . . . . . . . . . . -40°C to +125°C

Electrical Specifications Operating Conditions: VDD = 5V, T

unless otherwise noted. Boldface limits apply over the operating temperature range,

-40°C to +100°C.

PARAMETER SYMBOL TEST CONDITIONS

INPUT POWER SUPPLY

+5V Supply Current I

Battery Supply Current I

Input Resistance R

V

IN

VDD

VIN

VIN

Power-On-Reset Threshold POR

POR

SYSTEM AND REFERENCES

System Accuracy HRTZ

%Error

(V

CC_CORE

IRTZ

%Error

(V

CC_CORE

V

BOOT

Maximum Output Voltage V

Minimum Output Voltage V

Voltag e R

R

BIAS

CC_CORE(max)

CC_CORE(min)

r

f

VR_ON = 1V 4 4.6 mA

VR_ON = 0V 1 µA

VR_ON = 0V 1 µA
VR_ON = 1V 900 kΩ

VDD rising 4.35 4.5 V

VDD falling 4.00 4.15 V

No load; closed loop, active mode
range
VID = 0.75V to 1.50V, -0.5 +0.5 %

)

VID = 0.5V to 0.7375V -8 +8 mV

VID = 0.3V to 0.4875V -15 +15 mV

No load; closed loop, active mode
range
VID = 0.75V to 1.50V -0.8 +0.8 %

)

VID = 0.5V to 0.7375V -10 +10 mV

VID = 0.3V to 0.4875V -18 +18 mV

ISL62883CHRTZ 1.0945 1.100 1.1055 V

ISL62883CIRTZ 1.0912 1.100 1.1088 V

VID = [0000000] 1.500 V

VID = [1100000] 0.300 V

= 147kΩ 1.45 1.47 1.49 V

BIAS

= -40°C to +100°C, f

A

= 300kHz,

SW

MIN

(Note 6) TYP

MAX

(Note 6) UNITS

7

FN7557.1

March 18, 2010

ISL62883C

Electrical Specifications Operating Conditions: VDD = 5V, T

unless otherwise noted. Boldface limits apply over the operating temperature range,

= -40°C to +100°C, f

A

= 300kHz,

SW

-40°C to +100°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6) UNITS

CHANNEL FREQUENCY

R

Nominal Channel Frequency f

SW(nom)

= 7kΩ, 3-channel operation,

fset

V

= 1V

COMP

285 300 315 kHz

Adjustment Range 200 500 kHz

AMPLIFIERS

Current-Sense Amplifier Input

= 0A -0.15 +0.15 mV

I

FB

Offset

Error Amp DC Gain (Note 7) A

Error Amp Gain-Bandwidth

GBW C

Product (Note 7)

v0

= 20pF 18 MHz

L

90 dB

ISEN

Imbalance Voltage Maximum of ISENs - Minimum of

1 mV

ISENs

Input Bias Current 20 nA

POWER-GOOD AND PROTECTION MONITORS

PGOOD Low Voltage V

PGOOD Leakage Current I

OL

OH

I

PGOOD = 3.3V -1 1 µA

= 4mA 0.26 0.4 V

PGOOD

PGOOD Delay tpgd CLK_ENABLE# LOW to PGOOD HIGH 6.3 7.6 8.9 ms

GATE DRIVER

UGATE Pull-Up Resistance
(Note 7)

UGATE Source Current (Note 7) I

UGATE Sink Resistance (Note 7) R

UGATE Sink Current (Note 7) I

LGATE Pull-Up Resistance
(Note 7)

LGATE Source Current (Note 7) I

LGATE Sink Resistance (Note 7) R

LGATE Sink Current (Note 7) I

UG ATE to LGAT E De adtim e t

LGATE to UGAT E De adtim e t

R

UGPU

UGSRC

UGPD

UGSNK

R

LGPU

LGSRC

LGPD

LGSNK

UGFLGR

LGFUGR

200mA Source Current 1.0 1.5 Ω

UGATE - PHASE = 2.5V 2.0 A
250mA Sink Current 1.0 1.5 Ω

UGATE - PHASE = 2.5V 2.0 A

250mA Source Current 1.0 1.5 Ω

LGATE - VSSP = 2.5V 2.0 A
250mA Sink Current 0.5 0.9 Ω

LGATE - VSSP = 2.5V 4.0 A

UGATE falling to LGATE rising, no load 23 ns

LGATE falling to UGATE rising, no load 28 ns

BOOTSTRAP DIODE

Forward Voltage V

Reverse Leakage I

F

R

PVCC = 5V, IF = 2mA 0.58 V

VR = 25V 0.2 µA

PROTECTION

Overvoltage Threshold OV

Severe Overvoltage Threshold OV

OC Threshold Offset at
Rcomp = Open Circuit

H

HS

VSEN rising above setpoint for >1ms 150 195 240 mV

VSEN rising for >2µs 1.525 1.55 1.575 V

3-phase configuration, ISUM- pin

28.4 30.3 32.2 µA

current

2-phase configuration, ISUM- pin

18.3 20.2 22.1 µA

current

1-phase configuration, ISUM- pin

8.2 10.1 12.0 µA

current

Current Imbalance Threshold One ISEN above another ISEN for

9mV

>1.2ms

Undervoltage Threshold UV

f

VSEN falling below setpoint for
>1.2ms

-355 -295 -235 mV

8

FN7557.1

March 18, 2010

ISL62883C

Electrical Specifications Operating Conditions: VDD = 5V, T

unless otherwise noted. Boldface limits apply over the operating temperature range,

= -40°C to +100°C, f

A

= 300kHz,

SW

-40°C to +100°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6) UNITS

LOGIC THRESHOLDS

VR_ON Input Low V

VR_ON Input High V

V

VID0-VID6, PSI#, and
DPRSLPVR Input Low

VID0-VID6, PSI#, and DPRSLPVR
Input High

IL

IH

IH

V

IL

V

IH

ISL62883CHRTZ 0.7 V

ISL62883CIRTZ 0.75 V

0.7 V

0.3 V

0.3 V

PWM

PWM3 Output Low V

PWM3 Output High V

0L

0H

Sinking 5mA 1.0 V

Sourcing 5mA 3.5 V

PWM Tri-State Leakage PWM = 2.5V 2 µA

THERMAL MONITOR

NTC Source Current NTC = 1.3V 53 60 67 µA

Over-Temperature Threshold V (NTC) falling 1.18 1.2 1.22 V

VR_TT# Low Output Resistance R

TT

I = 20mA 6.5 9 Ω

CLK_EN# OUTPUT LEVELS

CLK_EN# Low Output Voltage V

CLK_EN# Leakage Current I

OL

OH

I = 4mA 0.26 0.4 V

CLK_EN# = 3.3V -1 1 µA

CURRENT MONITOR

IMON Output Current I

IMON

ISUM- pin current = 20µA 114 120 126 µA

ISUM- pin current = 10µA 54 60 66 µA

ISUM- pin current = 5µA 25.5 30 34.5 µA

IMON Clamp Voltage V

IMONCLAMP

1.1 1.15 V

Current Sinking Capability 275 µA

INPUTS

VR_ON Leakage Current I

VR_ON

VR_ON = 0V -1 0µA

VR_ON = 1V 0 1 µA

VIDx Leakage Current I

VIDx

VIDx = 0V -1 0µA

VIDx = 1V 0.45 1 µA

PSI# Leakage Current I

PSI#

PSI# = 0V -1 0µA

PSI# = 1V 0.45 1 µA

DPRSLPVR Leakage Current I

DPRSLPVR

DPRSLPVR = 0V -1 0µA

DPRSLPVR = 1V 0.45 1 µA

SLEW RATE

Slew Rate (For VID Change) SR 56.5mV/µs

NOTES:

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.

7. Limits established by characterization and are not production tested.

9

FN7557.1

March 18, 2010

Gate Driver Timing Diagram

PWM

t

LGFUGR

UGATE

t

RU

ISL62883C

t

FU

1V

LGATE

t

FL

1V

Simplified Application Circuits

V+5 Vin

V+5

VINVDD

VCCP

ISL62883C

(Bottom Pad)

VSS

PWM3

ISEN3

BOOT2

UGATE2

PHASE2

LGATE2

VSSP2

ISEN2

BOOT1

UGATE1

PHASE1

LGATE1

VSSP1

ISEN1

ISUM+

ISUM-

PGOOD

CLK_EN#

VID<0:6>

PSI#

DPRSLPVR

VR_ON

Rdroop

VCCSENSE
VSSSENSE

IMON

Rbias

Rntc

o

C

Rimon

Rfset

RBIAS

NTC

PGOOD
VR_TT#VR_TT#
CLK_EN#

VIDs
PSI#
DPRSLPVR
VR_ON
VW

COMP

FB

VSEN

RTN

IMON

t

UGFLGR

V+5

VCC

FCCM

ISL6208

PWM

GND

Cs3

Cs2

Cs1

Cn

Ri

UGATE

PHASE

BOOT

LGATE

o

Rs3

Rs2

Rs1

C

Rn

t

RL

Vin

L3

L2

L1

Rsum3

Rsum2

Rsum1

V

o

FIGURE 1. TYPICAL 3-PHASE APPLICATION CIRCUIT USING DCR SENSING

10

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March 18, 2010

ISL62883C

Simplified Application Circuits (Continued)

PGOOD

CLK_EN#

VID<0:6>

PSI#

DPRSLPVR

VR_ON

Rdroop

VCCSENSE
VSSSENSE

IMON

Rbias

Rntc

o

C

Rimon

Rfset

V+5 Vin

RBIAS

NTC

PGOOD
VR_TT#VR_TT#
CLK_EN#

VIDs
PSI#
DPRSLPVR
VR_ON
VW

ISL62883C

COMP

FB

VSEN

RTN

IMON

(Bottom Pad)

V+5

VCCP

VSS

VINVDD

PWM3

ISEN3

BOOT2

UGATE2

PHASE2

LGATE2

VSSP2

ISEN2

BOOT1

UGATE1

PHASE1

LGATE1

VSSP1

ISEN1

ISUM+

ISUM-

FCCM

ISL6208

PWM

Cs3

Cs2

Cs2

Cn

Ri

V+5

VCC

LGATE

GND

UGATE

PHASE

BOOT

Rs3

Rs2

Rs1

Rsum3

Rsum2

Rsum1

Vin

L3

L2

L1

Rsen3

Rsen2

Rsen1

V

o

FIGURE 2. TYPICAL 3-PHASE APPLICATION CIRCUIT USING RESISTOR SENSING

V+5 Vin

V+5

VCCP

VSS

VINVDD

PWM3

BOOT2

UGATE2

PHASE2

LGATE2

VSSP2

ISEN2

BOOT1

UGATE1
PHASE1

LGATE1a

VSSP1

ISEN1

ISUM+

ISUM-

Cn

Ri

Cs2

Cs1

Vin

L2

V

o

Rs2

L1

Rs1

Rsum2

Rn

o

C

Rsum1

PGOOD

CLK_EN#

VID<0:6>

PSI#

DPRSLPVR

VR_ON

Rdroop

VCCSENSE

VSSSENSE

IMON

Rbias

Rntc

o

C

Rimon

Rfset

RBIAS

NTC

PGOOD
VR_TT#VR_TT#
CLK_EN#

VIDs
PSI#
DPRSLPVR
VR_ON
VW

ISL62883C

COMP

FB2
FB

VSEN

RTN

IMON

(Bottom Pad)

FIGURE 3. TYPICAL 2-PGHASE APPLICATION CIRCUIT USING DCR SENSING

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FN7557.1

March 18, 2010

ISL62883C

Simplified Application Circuits (Continued)

V+5 Vin

V+5

VCCP

VSS

VINVDD

PWM3

BOOT2

UGATE2

PHASE2

LGATE2

VSSP2

ISEN2

BOOT1

UGATE1
PHASE1

LGATE1a

VSSP1

ISEN1

ISUM+

ISUM-

Cn

Ri

PGOOD

CLK_EN#

VID<0:6>

PSI#

DPRSLPVR

VR_ON

Rdroop

VCCSENSE

VSSSENSE

IMON

Rbias

Rntc

o

C

Rimon

Rfset

RBIAS

NTC

PGOOD
VR_TT#VR_TT#
CLK_EN#

VIDs
PSI#
DPRSLPVR
VR_ON
VW

ISL62883C

COMP

FB2
FB

VSEN

RTN

IMON

(Bottom Pad)

Vin

L

Rsum

Rn

o

C

V

o

FIGURE 4. TYPICAL 1-PHASE APPLICATION CIRCUIT USING DCR SENSING

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FN7557.1

March 18, 2010

ISL62883C

Theory of Operation

Multiphase R3™ Modulator

MASTER CLOCK CIRCUIT

VW

MASTER

CLOCK

gmVo

VW

Vcrs1

Crs1

VW

Vcrs2

Crs2

VW

Vcrs3

Crs3

FIGURE 5. R

VW

Vcrm

COMP

Master

Clock

Clock1

PWM1

Clock2

PWM2

Clock3

PWM3

FIGURE 6. R

COMP

Vcrm

Crm

Vcrs2 Vcrs1

3

™ MODULATOR OPERATION

PRINCIPLES IN STEADY STATE

MASTER

CLOCK

Phase

Sequencer

SLAVE CIRCUIT 1

Clock1

S

R

gm

SLAVE CIRCUIT 2

Clock2

Clock3

S

R

gm

SLAVE CIRCUIT 3

S

R

gm

3

™ MODULATOR CIRCUIT

Q

Q

Q

PWM1

PWM2

PWM3

Phase1

Phase2

Phase3

VW

Vcrs3

Clock1
Clock2
Clock3

L1

I

L1

L2

I

L2

L3

I

L3

Hysteretic

Window

Vo

Co

VW

COMP

Vcrm

Master

Clock

Clock1

PWM1

Clock2

PWM2

Clock3

PWM3

VW

Vcrs1

Vcrs3

Vcrs2

FIGURE 7. R

3

™ MODULATOROPERATION

PRINCIPLES IN LOAD INSERTION
RESPONSE

The ISL62883C is a multiphase regulators implementing
Intel™ IMVP-6.5™ protocol. It can be programmed for
1-, 2- or 3-phase operation. It uses Intersil patented

3

R

™ (Robust Ripple Regulator™) modulator. The R3™
modulator combines the best features of fixed
frequency PWM and hysteretic PWM while eliminating
many of their shortcomings. Figure 5 conceptually
shows the ISL62883C multiphase R

3

™ modulator

circuit, and Figure 6 shows the operation principles.

A current source flows from the VW pin to the COMP
pin, creating a voltage window set by the resistor
between the two pins. This voltage window is called
VW window in the following discussion.

Inside the IC, the modulator uses the master clock
circuit to generate the clocks for the slave circuits. The
modulator discharges the ripple capacitor C
current source equal to g
factor. C

voltage V

rm

crm

, where gm is a gain

mVo

is a sawtooth waveform

with a

rm

traversing between the VW and COMP voltages. It
resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer
distributes the master clock signal to the slave circuits.
If the ISL62883C is in 3-phase mode, the master clock
signal will be distributed to the three phases, and the
Clock1~3 signals will be 120° out-of-phase. If the
ISL62883C is in 2-phase mode, the master clock signal
will be distributed to Phases 1 and 2, and the Clock1
and Clock2 signals will be 180° out-of-phase. If the

13

FN7557.1

March 18, 2010

ISL62883C

ISL62883C is in 1-phase mode, the master clock signal
will be distributed to Phases 1 only and be the Clock1
signal.

Each slave circuit has its own ripple capacitor C
whose voltage mimics the inductor ripple current. A g

,

rs

m

amplifier converts the inductor voltage into a current
source to charge and discharge C

. The slave circuit

rs

turns on its PWM pulse upon receiving the clock signal,
and the current source charges C
V

hits VW, the slave circuit turns off the PWM pulse,

Crs

and the current source discharges C

Since the ISL62883C works with V

. When Crs voltage

rs

.

rs

, which are

crs

large-amplitude and noise-free synthesized signals,
the ISL62883C achieves lower phase jitter than
conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode
converters, the ISL62883C has an error amplifier that
allows the controller to maintain a 0.5% output voltage
accuracy.

Figure 7 shows the operation principles during load
insertion response. The COMP voltage rises during load
insertion, generating the master clock signal more
quickly, so the PWM pulses turn on earlier, increasing
the effective switching frequency, which allows for
higher control loop bandwidth than conventional fixed
frequency PWM controllers. The VW voltage rises as
the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls.
It takes the master clock circuit longer to generate the
next master clock signal so the PWM pulse is held off
until needed. The VW voltage falls as the VW voltage
falls, reducing the current PWM pulse width. This kind
of behavior gives the ISL62883C excellent response
speed.

The fact that all the phases share the same VW
window voltage also ensures excellent dynamic current
balance among phases.

ISL62883C can operate in diode emulation (DE) mode
to improve light load efficiency. In DE mode, the low­side MOSFET conducts when the current is flowing from
source to drain and doesn’t not allow reverse current,
emulating a diode. As Figure 8 shows, when LGATE is
on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage
drop across the ON-resistance. The ISL62883C
monitors the current through monitoring the phase
node voltage. It turns off LGATE when the phase node
voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary
power loss.

If the load current is light enough, as Figure 8 shows,
the inductor current will reach and stay at zero before
the next phase node pulse, and the regulator is in
discontinuous conduction mode (DCM). If the load
current is heavy enough, the inductor current will
never reach 0A, and the regulator is in CCM although
the controller is in DE mode.

Figure 9 shows the operation principle in diode
emulation mode at light load. The load gets
incrementally lighter in the three cases from top to
bottom. The PWM on-time is determined by the VW
window size, therefore is the same, making the inductor
current triangle the same in the three cases. The
ISL62883C clamps the ripple capacitor voltage V
DE mode to make it mimic the inductor current. It takes
the COMP voltage longer to hit V

, naturally stretching

crs

the switching period. The inductor current triangles
move further apart from each other such that the
inductor current average value is equal to the load
current. The reduced switching frequency helps increase
light load efficiency.

CCM/DCM BOUNDARY
VW

Vcrs

crs

in

Diode Emulation and Period Stretching

Phase

UGATE

LGATE

IL

FIGURE 8. DIODE EMULATION

14

iL

LIGHT DCM

Vcrs

iL

Vcrs

iL

FIGURE 9. PERIOD STRETCHING

VW

VW

DEEP DCM

FN7557.1

March 18, 2010