intersil ISL6210 DATA SHEET

®

www.BDTIC.com/Intersil

ISL6210

PRELIMINARY

Data Sheet November 28, 2006

Dual Synchronous Rectified MOSFET
Drivers

The ISL6210 integrates two ISL6208A drivers and is
optimized to drive two independent power channels in a
synchronous-rectified buck converter topology. These
drivers combined with an Intersil ISL62xx multiphase PWM
controller forms a complete single-stage core-voltage
regulator solution with high efficiency performance at high
switching frequency for advanced microprocessors.

The IC is biased by a single low voltage supply (5V),
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications.
Each driver is capable of driving a 3nF load with less than
10ns rise/fall time. Bootstrapping of the upper gate driver is
implemented via an internal low forward drop diode,
reducing implementation cost, complexity, and allowing the
use of higher performance, cost effective N-Channel
MOSFETs. Adaptive shoot-through protection is integrated
to prevent both MOSFETs from conducting simultaneously.

The ISL6210 features 4A typical sink current for the lower
gate driver, enhancing the lower MOSFET gate hold-down
capability during PHASE node rising edge, preventing power
loss caused by the self turn-on of the lower MOSFET due to
the high dV/dt of the switching node.

The ISL6210 also features an input that recognizes a high­impedance state, working together with Intersil multiphase
PWM controllers to prevent negative transients on the
controlled output voltage when operation is suspended. This
feature eliminates the need for the schottky diode that may
be utilized in a power system to protect the load from
negative output voltage damage.

Ordering Information

PART

NUMBER

(Note)

ISL6210CRZ 62 10CRZ -10 to +100 16 Ld 4x4 QFN L16.4x4
ISL6210CRZ-T 62 10CRZ -10 to +100 16 Ld 4x4 QFN L16.4x4

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

PART

MARKING

TEMP.

RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

FN6392.0

Features

• 5V Quad N-Channel MOSFET Drives for Two
Synchronous Rectified Bridges

• Adaptive Shoot-Through Protection

- Active Gate Threshold Monitoring

- Programmable Dead-Time

•0.4Ω On-Resistance and 4A Sink Current Capability

• Supports High Switching Frequency

- Fast Output Rise and Fall

- Ultra Low Three-State Hold-Off Time (20ns)

•Low V

• Low Bias Supply Current

• Power-On Reset

• QFN Package

• Pb-Free Plus Anneal Available (RoHS Compliant)

Internal Bootstrap Diode

F

- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat

No Leads-Product Outline

- Near Chip-Scale Package Footprint; Improves PCB

Efficiency and Thinner in Profile

Applications

• Core Voltage Supplies for Intel® and AMD®
Microprocessors

• High Frequency Low Profile High Efficiency DC/DC
Converters

• High Current Low Voltage DC/DC Converters

• Synchronous Rectification for Isolated Power Supplies

Related Literature

• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

• Technical Brief 400 and Technical Brief 417 for Power
Train Design, Layout Guidelines, and Feedback
Compensation Design

• Technical Brief 447 “Guidelines for Preventing Boot-to­Phase Stress on Half-Bridge MOSFET Driver ICs”

1

AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Copyright Intersil Americas Inc. 2006. All Rights Reserved. Intel® is a registered trademark of Intel Corporation.

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Pinout

www.BDTIC.com/Intersil

ISL6210

ISL6210

(16 LD 4X4 QFN)

TOP VIEW

PWM2

PWM1

VCC

15

16 14 13

PHASE1

Block Diagram

FCCM

VCC

PWM1

4.25K

EN

LGATE1

PVCC

GND

PVCC

FCCM

1

2

3

4

PGND

ISL6210

SHOOT-

THROUGH

PROTECTION

12

GND

6578

LGATE2

PVCC

11

10

9

EN

PHASE2

UGATE1

BOOT1

BOOT2

UGATE2

BOOT1

UGATE1

PHASE1

CHANNEL 1

PWM2

GND

VCC

4K

4.25K

4K

CONTROL

LOGIC

PAD

LGATE1

PGND

PVCC

SHOOT-

THROUGH

PROTECTION

PGND

PGND

BOOT2

UGATE2

PHASE2

PVCC

LGATE2

CHANNEL 2

THE PAD ON THE BOTTOM SIDE OF THE QFN PACKAGE
MUST BE SOLDERED TO THE CIRCUIT’S GROUND.

2

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November 28, 2006

ISL6210

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Typical Application - Multiphase Converter Using ISL6210 Gate Drivers

PGOOD

EN

VID

FB

VSEN

FCCM

COMP

MAIN

CONTROL

ISL62xx

GND

V

CC

ISEN1

PWM1

PWM2

ISEN2

ISEN3

PWM3

PWM4

ISEN4

EN

+5V

+5V

VCC

FCCM

PWM1

PWM2

+5V

DUAL
DRIVER
ISL6210

PAD

GND

BOOT1

UGATE1

PHASE1

LGATE1

PVCC

UGATE2

PHASE2

LGATE2

PGND

BOOT1

UGATE1

+5V

BOOT2

+12V

+12V

+12V

+V

CORE

EN

VCC

FCCM

DUAL
DRIVER
ISL6210

PWM1

PWM2

PAD

GND

3

PHASE1

LGATE1

PVCC

BOOT2

UGATE2

PHASE2

LGATE2

PGND

+5V

+12V

FN6392.0

November 28, 2006

ISL6210

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

Input Voltage (V
BOOT Voltage (V
BOOT To PHASE Voltage (V

PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V (DC)

UGATE Voltage . . . . . . . . . . . . . . . . V

LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V

Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C

HBM ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV

, V

EN

BOOT-GND

V

GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V

) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V

PWM

). . . -0.3V to 33V (DC) or 36V (<200ns)

BOOT-PHASE

GND -8V (<20ns Pulse Width, 10μJ)

- 5V (<20ns Pulse Width, 10μJ) to V

PHASE

). . . . . . -0.3V to 7V (DC)

-0.3V to 9V (<10ns)

- 0.3V (DC) to V

PHASE

BOOT
BOOT

Recommended Operating Conditions

Ambient Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +100°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.

1. θ

JA

, “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.

2. θ

JC

Thermal Resistance (Notes 1 and 2) θ

QFN Package. . . . . . . . . . . . . . . . . . 46 8.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

(°C/W) θJC(°C/W)

JA

Electrical Specifications These specifications apply for T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SUPPLY CURRENT

Bias Supply Current I

POWER-ON RESET

POR Rising -3.44.2V
POR Falling 2.6 3.0 - V
Hysteresis - 400 - mV

BOOTSTRAP DIODE

Forward Voltage Drop V

PWM INPUT

Sinking Impedance R
Source Impedance R
Three-State Rising Threshold V
Three-State Falling Threshold V
Three-State Shutdown Holdoff Time t
Three-state to UG/LG Rising Propagation

Delay
SWITCHING TIME (See Figure 1)
UGATE Rise Time (Note 3) t
LGATE Rise Time (Note 3) t
UGATE Fall Time (Note 3) t
LGATE Fall Time (Note 3) t
UGATE Turn-Off Propagation Delay t
LGATE Turn-Off Propagation Delay t
UGATE Turn-On Propagation Delay t
LGATE Turn-On Propagation Delay t

VCC

F

PWM_SNK
PWM_SRC

TSSHDtPDLU

t

PTS

RU
RL
FU

FL
PDLU
PDLL

PDHU

PDHL

= -10°C to +100°C, Unless Otherwise Noted

A

PWM pin floating, V

V

= 5V, forward bias current = 2mA 0.3 0.60 0.7 V

VCC

= 5V 1.08 1.3 1.5 V

VCC

= 5V 3.4 3.65 3.98 V

VCC

or t

+ Gate Falling Time - 80 - ns

PDLL

V

= 5V, 3nF Load - 8.0 - ns

VCC

V

= 5V, 3nF Load - 8.0 - ns

VCC

V

= 5V, 3nF Load - 8.0 - ns

VCC

V

= 5V, 3nF Load - 4.0 - ns

VCC

V

= 5V, Outputs Unloaded - 20 - ns

VCC

V

= 5V, Outputs Unloaded - 27 - ns

VCC

V

= 5V, Outputs Unloaded; R

VCC

V

= 5V, Outputs Unloaded; R

VCC

= 5V - 170 - μA

VCC

8.0 10.4 15 kΩ

8.3 10.6 25 kΩ

-20-ns

= 0Ω -26-ns

SET

= 0Ω -26-ns

SET

4

FN6392.0

November 28, 2006

ISL6210

www.BDTIC.com/Intersil

Electrical Specifications These specifications apply for T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

UGATE Turn-On Propagation Delay t
LGATE Turn-On Propagation Delay t
Minimum LGATE On Time in DCM (Note 3) t

OUTPUT

Upper Drive Source Resistance (Note 3) R
Upper Drive Source Current (Note 3) I
Upper Drive Sink Resistance (Note 3) R
Upper Drive Sink Current (Note 3) I
Lower Drive Source Resistance (Note 3) R
Lower Drive Source Current (Note 3) I
Lower Drive Sink Resistance (Note 3) R
Lower Drive Sink Current (Note 3) I

NOTE:

3. Guaranteed by Characterization. Not 100% tested in production.

PDHU

PDHL

LGMIN

UG_SRC

UG_SCRVUGATE-PHASE

UG_SNK

UG_SNKVUGATE-PHASE

LG_SRC

LG_SCR

LG_SNK

LG_SNKVLGATE

= -10°C to +100°C, Unless Otherwise Noted (Continued)

A

V

= 5V , Outputs Unloaded; R

VCC

V

= 5V , Outputs Unloaded; R

VCC

250mA Source Current - 1.0 2.5 Ω

= 2.5V - 2.00 - A

250mA Sink Current - 1.0 2.5 Ω

= 2.5V 2.00 - A
250mA Source Current - 1.0 2.5 Ω
V

= 2.5V - 2.00 - A

LGATE

250mA Sink Current - 0.4 1.0 Ω

= 2.5V - 4.00 - A

= 80kΩ -41-ns

SET

= 80kΩ -33-ns

SET

- 400 - ns

Functional Pin Description

NUMBER NAME FUNCTION

1 GND Bias and reference ground. All signals are referenced to this node.
2 LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
3 PVCC This pin supplies power to both the lower and higher gate drives in ISL6614. Its operating range is +5V to 12V. Place a high

quality low ESR ceramic capacitor from this pin to GND.

4 FCCM Logic control input that will force continuous conduction mode (HIGH state) or allow discontinuous conduction mode

(LOW state). Placing a series resistor in this input will allow the switching dead-time to be programmed.
5 PGND It is the power ground return of both low gate drivers.
6 LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
7 EN Logic control input that will enable (HIGH st ate) or disable (L OW state) the IC. Shut down current is <1μA.
8 PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This pin

9 UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.

10 BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this pin and

11 BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this pin and

12 UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
13 PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This pin

14 VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic

15 PWM1 The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during operation, see

16 PWM2 The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during operation, see

N/A PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.

provides a return path for the upper gate drive.

the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap

Device section under DESCRIPTION for guidance in choosing the capacitor value.

the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap

Device section under DESCRIPTION for guidance in choosing the capacitor value.

provides a return path for the upper gate drive.

capacitor from this pin to GND.

the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller.

the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller.

5

FN6392.0

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Timing Diagram

www.BDTIC.com/Intersil

PWM

t

PDHU

t

PDLU

2.5V

ISL6210

t

TSSHD

t

RU

UGATE

LGATE

t

PDLL

1V

1V

t

RL

t

PDHL

FIGURE 1. TIMING DIAGRAM

Description

Theory of Operation

Designed for speed, the ISL6210 dual MOSFET driver
controls both high-side and low-side N-Channel FETs for two
separate channels of a Multiphase PWM system from two
independent PWM signals.

A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
[t

] are provided in the Electrical Specifications section.

FL

Adaptive shoot-through circuitry monitors the LGATE
voltage. When LGATE has fallen below 1V, UGATE is
allowed to turn ON. This prevents both the lower and upper
MOSFETs from conducting simultaneously, or shoot­through.

A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
gate begins to fall [t
voltage is monitored, and the lower gate is allowed to rise
after the upper MOSFET gate-to-source voltage drops below
1V. The lower gate then rises [t
MOSFET.

This driver is optimized for converters with large step down
compared to the upper MOSFET because the lower
MOSFET conducts for a much longer time in a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement.

The 0.5Ω on-resistance and 4A sink current capability
enable the lower gate driver to absorb the current injected to

], the lower gate begins to fall. Typical fall times

PDLL

] is encountered before the upper

PDLU

]. The upper MOSFET gate-to-source

FU

], turning on the lower

RL

t

RU

t

PTS

t

TSSHD

t

FL

t

FU

t

PTS

the lower gate through the drain-to-gate capacitor of the
lower MOSFET and prevent a shoot through caused by the
high dv/dt of the phase node.

Diode Emulation

Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6210 will detect the zero current crossing of the output
inductor and turn off LGATE. This ensures that
discontinuous conduction mode (DCM) is achieved. Diode
emulation is asynchronous to the PWM signal. Therefore,
the ISL6210 will respond to the FCCM input immediately
after it changes state.

NOTE: Intersil does not recommend Diode Emulation use with
r
MOSFET can cause gross current measurement inaccuracies.

current sensing topologies. The turn-OFF of the low side

DS(ON)

Three-State PWM Input

A unique feature of the ISL6210 and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.

Adaptive Shoot-Through Protection

Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to turn on.

6

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During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate-to-source voltage during
UGATE turn-off. Once the upper MOSFET gate-to-source
voltage has dropped below a threshold of 1V, the LGATE is
allowed to rise.

In addition to gate threshold monitoring, a programmable
delay between MOSFET switching can be accomplished by
placing a resistor in series with the FCCM input. This delay
allows for maximum design flexibility over MOSFET
selection. The delay can be programmed from 5ns to 50ns
and is obtained from the absolute value of the current
flowing into the FCCM pin. If no resistor is used, the
minimum 5ns delay is selected. Gate threshold monitoring is
not affected by the addition or removal of the additional
dead-time. Refer to Figure 2 and Figure 3 for more detail.

FCCM = VCC or GND

GATE A

GATE B

50

45

40

35

30

25

DEAD-TIME (ns)

20

15

10

5

0

0 167 667333 500 833 1000

FIGURE 3. ISL6210 PROGRAMMABLE DEAD-TIME vs

DELAY RESISTOR

R

DELAY

t

DELAY

(kΩ)

The equation governing the dead-time seen in Figure 3 is
expressed as:

T

DELAY ns()

0.045 R

×[]5ns+=

DELAY kΩ()

(EQ. 1)

1V

1V

ADAPTIVE SHOOT-THROUGH

PROTECTION

FCCM = RESISTOR to VCC or GND

GATE A

ADAPTIVE PROTECTION

WITH DELAY

= 5n - 50ns

T

DELAY

FIGURE 2. PROGRAMMABLE DEAD-TIME

GATE B

The equation can be rewritten to solve for R

DELAY

as

follows:

R

DELAY

T

DELAY ns()

------------------------------------------------------

=

kΩ()

5ns–()

0.045

(EQ. 2)

Internal Bootstrap Diode

This driver features an internal bootstrap diode. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.

The following equation helps select a proper bootstrap
capacitor size:

Q

GATE

C

BOOT_CAP

Q

GATE

where Q
at V

GS1

control MOSFETs. The ΔV
allowable droop in the rail of the upper gate drive.

As an example, suppose two IRLR7821 FET s are chosen as
the upper MOSFETs. The gate charge, Q
sheet is 10nC at 4.5V (V
Q

GATE

assume a 200mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least

0.110μF is required. The next larger standard value

--------------------------------------

≥

ΔV

BOOT_CAP

QG1PVCC•

----------------------------------- -

V

GS1

is the amount of gate charge per upper MOSFET

G1

•=

N

Q1

gate-source voltage and NQ1 is the number of

BOOT_CAP

) gate-source voltage. Then the

GS

term is defined as the

, from the data

G

is calculated to be 22nC at PVCC level. We will

(EQ. 3)

7

FN6392.0

November 28, 2006

ISL6210

www.BDTIC.com/Intersil

capacitance is 0.22µF. A good quality ceramic capacitor is
recommended.

2.0

1.8

1.6

1.4

(µF)

1.2

1.0

0.8

BOOT_CAP

C

0.6

0.4

0.2

20nC

0.0

Q

= 100nC

GATE

50

n

C

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
ΔV

BOOT_CAP

(V)

FIGURE 4. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

Power Dissipation

Package power dissipation is mainly a function of the
switching frequency (F
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
125°C. The maximum allowable IC powe r dissipation for the
SO14 package is approximately 1W at room temperature,
while the power dissipation capacity in the QFN packages,
with an exposed heat escape pad, is around 2W. See Layout
Considerations paragraph for thermal transfer improvement
suggestions. When designing the driver into an application, it
is recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFET s. The total gate drive power losses due to
the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 4 and 5, respectively,

P

Qg_TOTPQg_Q1PQg_Q2IQ

QG1PVCC

P

Qg_Q1

P

Qg_Q2

⎛⎞

I

⎜⎟

DR

⎝⎠

---------------------------------------

QG2PVCC

---------------------------------------

QG1NQ1•

----------------------------- -

V

GS1

), the output drive impedance, the

SW

VCC•++=

•

V

•

V

+

2

GS1

2

GS2

•

Q

G2NQ2

----------------------------- -

V

GS2

• NQ1•=

F

SW

• NQ2•=

F

SW

F

+•=

SWIQ

(EQ. 4)

(EQ. 5)

where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
and N
respectively. The I

are number of upper and lower MOSFETs,

Q2

Q VCC

and QG2) is defined at a

G1

and V

GS1

GS2

is the driver’s total

Q

) in the

Q1

product is the quiescent power of

the driver without capacitive load and is typically negligible.
The total gate drive power losses are dissipated among the

resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R

and RG2, should be a short to avoid

G1

interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R

GI1

and R

GI2

) of
MOSFET s. Figures 5 and 6 show the typical upper and lower
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as:

P

DRPDR_UPPDR_LOWIQ

R

⎛⎞

HI1

P

DR_UP

P

DR_LOW

R

EXT2RG1

PVCC

--------------------------------------

⎜⎟

R

+

⎝⎠

HI1REXT1

R

⎛⎞

HI2

--------------------------------------

⎜⎟

R

+

⎝⎠

HI2REXT2

R

GI1

-------------

+=

N

Q1

BOOT

R

HI1

R

LO1

UGATE

PHASE

FIGURE 5. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

PVCC

LGATE

R

HI2

R

LO2

GND

FIGURE 6. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

VCC•++=

R

LO1

----------------------------------------

+

R

+

LO1REXT1

R

LO2

----------------------------------------

+

R

+

LO2REXT2

R

EXT2RG2

G

R

G1

C

G

R

R

G2

R

GD

GI2

(EQ. 6)

P

Qg_Q1

---------------------

•=

2

P

Qg_Q2

---------------------

•=

2

R

GI2

-------------

+=

N

Q2

D

C

GD

C

DS

GI1

C

GS

C

GS

S

Q1

S

D

C

DS

Q2

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FN6392.0

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www.BDTIC.com/Intersil

Layout Considerations

Reducing Phase Ring

The parasitic inductances of the PCB and the power devices
(both upper and lower FET s) could cause serious ringing,
exceeding absolute maximum rating of the devices. The
negative ringing at the edges of the PHASE node could add
charges to the bootstrap capacitor through the internal
bootstrap diode, in some cases, it could cause over stress
across BOOT and PHASE pins. Therefore, user should do a
careful layout and select proper MOSFETs and drivers. The

2

D

PAK and DPAK package MOSFETs have high parasitic
lead inductance, which can exacerbate this issue. FET
selection plays an important role in reducing PHASE ring. If
higher inductance FETs must be used, a Schottky diode is
recommended across the lower MOSFET to clamp negative
PHASE ring.

A good layout would help reduce the ringing on the phase
and gate nodes significantly:

• Avoid uses via for decoupling components across BOOT
and PHASE pins and in between VCC and GND pins. The
decoupling loop should be short.

• All power traces (UGATE, PHASE, LGATE, GND, VCC)
should be short and wide, and avoid using via; otherwise,
use two vias for interconnection when possible.

• Keep SOURCE of upper FET and DRAIN of lower FET as
close as thermally possible.

• Keep connection in between SOURCE of lower FET and
power ground wide and short.

• Input capacitors should be placed as close to the DRAIN
of upper FET and SOURCE of lower FETs as thermally
possible.

NOTE: Refer to Intersil Tech Brief TB447 for more information.

Thermal Management

For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
pad of the QFN part to the power ground with multiple vias is
recommended. This heat spreading allows the part to
achieve its full thermal potential.

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FN6392.0

November 28, 2006

ISL6210

www.BDTIC.com/Intersil

Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A2 - - 1.00 9

A3 0.20 REF 9

b 0.23 0.28 0.35 5, 8

D 4.00 BSC -

D1 3.75 BSC 9

D2 1.95 2.10 2.25 7, 8

E 4.00 BSC -

E1 3.75 BSC 9

E2 1.95 2.10 2.25 7, 8

e 0.65 BSC -

k0.25 - - -

L 0.50 0.60 0.75 8

L1 - - 0.15 10

N162

Nd 4 3

Ne 4 3

P- -0.609
θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

NOTESMIN NOMINAL MAX

Rev. 5 5/04

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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