intersil ISL6208 DATA SHEET

®

www.BDTIC.com/Intersil

ISL6208

Data Sheet March 30, 2007 FN9115.2

High Voltage Synchronous Rectified Buck
MOSFET Driver

The ISL6208 is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology. It is
especially suited for mobile computing applications that
require high efficiency and excellent thermal performance.
This driver, combined with an Intersil multiphase Buck PWM
controller, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.

The ISL6208 features 4A typical sinking current for the lower
gate driver. This current is capable of holding the lower
MOSFET gate off during the rising edge of the Phase node.
This prevents shoot-through power loss caused by the high
dv/dt of phase voltages. The operating voltage matches the
30V breakdown voltage of the MOSFETs commonly used in
mobile computer power supplies.

The ISL6208 also features a three-state PWM input that,
working together with Intersil’s multiphase PWM controllers,
will prevent negative voltage output during CPU shutdown.
This feature eliminates a pr ot ective Schottky diode usually
seen in a microprocessor power systems.

MOSFET gates can be efficiently switched up to 2MHz using
the ISL6208. Each driver is capable of driving a 3000pF load
with propagation delays of 8ns and transition times under
10ns. Bootstrapping is implemented with an internal
Schottky diode. This reduces system cost and complexity,
while allowing the use of higher performance MOSFETs.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously.

A diode emulation feature is integrated in the ISL6208 to
enhance converter efficiency at light load conditions. This
feature also allows for monotonic start-up into pre-biased
outputs. When diode emulation is enabled, the driver will
allow discontinuous conduction mode by detecting when the
inductor current reaches zero and subsequently turning off
the low side MOSFET gate.

Features

• Dual MOSFET Drives for Synchronous Rectified Bridge

• Adaptive Shoot-Through Protection

•0.5Ω On-Resistance and 4A Sink Current Capability

• Supports High Switching Frequency up to 2MHz

- Fast output rise and fall time

- Low propagation delay

• Three-State PWM Input for Power Stage Shutdown

• Internal Bootstrap Schottky Diode

• Low Bias Supply Current (5V, 80µA)

• Diode Emulation for Enhanced Light Load Efficiency and
Pre-Biased Start-Up Applications

• VCC POR (Power-On-Reset) Feature Integrated

• Low Three-State Shutdown Holdoff Time (Typical 160ns)

• Pin-to-pin Compatible with ISL6207

• QFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Core Voltage Supplies for Intel® and AMD® Mobile
Microprocessors

• High Frequency Low Profile DC/DC Converters

• High Current Low Output Voltage DC/DC Converters

• High Input Voltage DC/DC Converters

Related Literature

• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for MLFP Packages”

• Technical Brief TB447 “Guidelines for Preventing Boot-to­Phase Stress on Half-Bridge MOSFET Driver ICs”

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2004-2006. All Rights Reserved

ISL6208

www.BDTIC.com/Intersil

Ordering Information

PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #

ISL6208CB* ISL6208CB -10 to +100 8 Ld SOIC M8.15
ISL6208CBZ* (Note) ISL6208CBZ -10 to +100 8 Ld SOIC (Pb-free) M8.15
ISL6208CR* 208C -10 to +100 8 Ld 3x3 QFN L8.3x3
ISL6208CRZ* (Note) 208Z -10 to +100 8 Ld 3x3 QFN (Pb-free) L8.3x3
ISL6208IB* ISL6208IB -40 to +100 8 Ld SOIC M8.15
ISL6208IBZ* (Note) ISL6208IBZ -40 to +100 8 Ld SOIC (Pb-free) M8.15
ISL6208IR* 208I -40 to +100 8 Ld 3x3 QFN L8.3x3
ISL6208IRZ* (Note) 81RZ -40 to +100 8 Ld 3x3 QFN (Pb-free) L8.3x3
* Add “-T” suffix for T ape and Reel.

NOTE: Intersil Pb-free plus anneal products em ploy specia l Pb-free m aterial set s; molding comp ounds/die atta ch materi als and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Pinouts

ISL6208CB

(8 LD SOIC)

TOP VIEW

ISL6208CR

(8 LD 3x3 QFN)

TOP VIEW

UGATE

BOOT

PWM

GND

Block Diagram

1
2
3
4

VCC

FCCM

PWM

8
7
6
5

10K

PHASE
FCCM
VCC
LGATE

CONTROL

LOGIC

SHOOT-

THROUGH

PROTECTION

VCC

BOOT

PWM

UGATE

PHASE

7

8

1

2

GND

BOOT

UGATE

PHASE

LGATE

6

6

FCCM

5

VCC

43

LGATE

THERMAL PAD (FOR QFN PACKAGE ONLY)

FIGURE 1. BLOCK DIAGRAM

ti

2

GND

FN9115.2

March 30, 2007

ISL6208

www.BDTIC.com/Intersil

ti

Absolute Maximum Ratings Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

Input Voltage (V
BOOT Voltage (V
BOOT To PHASE Voltage (V

PHASE Voltage (Note 1) . . . . . . . . . . . . . . . . . . .GND - 0.3V to 30V

UGATE Voltage . . . . . . . . . . . . . . . . V

LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V

Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C

, V

FCCM

BOOT-GND

V

PHASE

GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V

). . . . . . . . . . . . . -0.3V to VCC + 0.3V

PWM

). . . . . . . . . . . . . . . . . . . . . -0.3V to 33V

BOOT-PHASE

GND - 8V (<20ns Pulse Width, 10μJ)

- 5V (<20ns Pulse Width, 10μJ) to V

). . . . . . -0.3V to 7V (DC)

-0.3V to 9V (<10ns)

- 0.3V (DC) to V

PHASE

BOOT
BOOT

Thermal Resistance (Typical) θ

SOIC Package (Note 2) . . . . . . . . . . . . 110 n/a

QFN Package (Notes 3, 4). . . . . . . . . . 80 15

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)

Recommended Operating Conditions

Ambient Temperature Range. . . . . . . . . . . . . . . . . . -10°C to +100°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θ

JA

3. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

4. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

(°C/W) θJC (°C/W)

JA

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SUPPLY CURRENT

V

CC

Bias Supply Current I
POR --­V

Rising - 3.40 3.90 V

CC

Falling 2.40 2.90 - V

V

CC

Hysteresis - 500 - mV

BOOTSTRAP DIODE

Forward Voltage V

PWM INPUT

Input Current I

PWM Three-State Rising Threshold V
PWM Three-State Falling Threshold V
Three-State Shutdown Hold-off Time t

FCCM INPUT

FCCM LOW Threshold 0.50 - - V
FCCM HIGH Threshold --2.0V

VCC

PWM

TSSHD

PWM pin floating, V

V

F

V
V

V

= 5V, forward bias current = 2mA 0.50 0.55 0.65 V

VCC

= 5V - 250 - μA

PWM

= 0V - -250 - μA

PWM

= 5V 0.70 1.00 1.30 V

VCC

= 5V 3.5 3.8 4.1 V

VCC

= 5V, temperature = +25°C 100 175 250 ns

VCC

= 5V - 80 - μA

FCCM

SWITCHING TIME

UGATE Rise Time (Note 5) t
LGATE Rise Time (Note 5) t

RU
RL

V

= 5V, 3nF load - 8.0 - ns

VCC

V

= 5V, 3nF load - 8.0 - ns

VCC

3

FN9115.2

March 30, 2007