intersil ISL6140, ISL6150 DATA SHEET

®

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ISL6140, ISL6150

PRELIMINARY

Data Sheet February 2004

Negative Voltage Hot Plug Controller

The ISL6140 is an 8-pin, negative voltage hot plug controller
that allows a board to be safely inserted and removed from a
live backplane. Inrush current is limited to a programmable
value by controlling the gate voltage of an external
N-channel pass transistor. The pass transistor is turned off if
the input voltage is less than the undervoltage threshold, or
greater than the overvoltage threshold. A programmable
electronic circuit breaker protects the system against shorts.
The active low PWRGD

signal can be used to directly enable

a power module (with a low enable input)

The ISL6150 is the same part, but with an active high
PWRGD signal.

Ordering Information

TEMP.

PART NUMBER

ISL6140CB 0 to 70 8 Ld SOIC M8.15

ISL6140CBZ
(Note 1)

ISL6140IB -40 to 85 8 Lead SOIC M8.15

ISL6140IBZ
(Note 1)

ISL6150CB 0 to 70 8 Ld SOIC M8.15

ISL6150CBZ
(Note 1)

ISL6150IB -40 to 85 8 Lead SOIC M8.15

ISL6150IBZ
(Note 1)

NOTES:

1. Intersil Lead-Free products employ special lead-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which is compatible with both SnPb and lead­free soldering operations. Intersil Lead-Free products are MSL
classified at lead-free peak reflow temperatures that meet or
exceed the lead-free requirements of IPC/JEDEC J Std-020B.

2. Add suffix “-T” to Part Number for Tape and Reel.

RANGE (°C) PACKAGE

0 to 70 8 Ld SOIC

(Lead-Free)

-40 to 85 8 Lead SOIC
(Lead-Free)

0 to 70 8 Ld SOIC

(Lead-Free)

-40 to 85 8 Lead SOIC
(Lead-Free)

PKG.

DWG. #

M8.15

M8.15

M8.15

M8.15

Pinout

ISL6140 OR ISL6150 (8 LEAD SOIC)

TOP VIEW

PWRGD

1

OV

2

3

UV

V

4

EE

ISL6140 has active Low (L version) PWRGD output pin

ISL6150 has active High (H version) PWRGD output pin

8

7

6

5

V

DD

DRAIN

GATE

SENSE

FN9039.2

Features

• Low Side External NFET Switch

• Operates from -10V to -80V (-100V absolute max rating)
or +10V to +80V (+100V absolute max rating)

• Programmable Inrush Current

• Programmable Electronic Circuit Breaker (Over-Current
shutdown)

• Programmable Overvoltage Protection

• Programmable Undervoltage Lockout

• Power Good Control Output

- PWRGD Active High: (H Version) ISL6150

-PWRGD

active Low: (L Version) ISL6140

• Lead-Free Available as an Option

Applications

• VoIP (Voice over Internet Protocol) Servers

• Telecom systems at -48V

• Negative Power Supply Control

• +24V Wireless Base Station Power

Related Literature

• ISL6140/50EVAL1 Board Set, Document # AN9967

• ISL6116 Hot Plug Controller, Document # FN4778

NOTE: See www.intersil.com/hotplug for more information.

Typical Application (RL and CL are the Load)

GND GND

R4

UV

R5

OV

R6

-48V IN

R1 = 0.02Ω (1%)
R2 = 10Ω (5%)
R3 = 18kΩ (5%)
R4 = 562kΩ (1%)
R5 = 9.09kΩ (1%)
R6 = 10kΩ (1%)

V

EE

R1

V

DD

R3

PWRGD

C2

ISL6140

SENSE GATE DRAIN

C1

R2

Q1

C1 = 150nF (25V)

C2 = 3.3nF (100V)
Q1 = IRF530 (100V, 17A, 0.11Ω)
CL = 100µF (100V)

(LOAD)

CL

RL

-48V OUT

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2003. All Rights Reserved

ISL6140, ISL6150

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Pin Description

PWRGD (ISL6140; L Version) Pin 1 - This digital output is
an open-drain pull-down device. The Power Good
comparator looks at the DRAIN pin voltage compared to the
internal VPG reference (VPG is nominal 1.7V); this
essentially measures the voltage drop across the external
FET and sense resistor. If the voltage drop is small (<1.7V is
normal), the PWRGD
used as an active low enable for an external module. If the
voltage drop is too large (>1.7V indicates some kind of short
or overload condition), the pull-down device shuts off, and
the pin becomes high impedance. Typically, an external pull­up of some kind is used to pull the pin high (many brick
regulators have a pull-up function built in).

PWRGD (ISL6150; H Version) Pin 1 - This digital output is
a variation of an open-drain pull-down device. The Power
Good comparator is the same as described above, but the
polarity of the output is reversed, as follows:

If the voltage drop across the FET is too large (>1.7V), the
open drain pull-down device will turn on, and sink current to
the DRAIN pin. If the voltage drop is small (<1.7V), a 2nd
pull-down device in series with a 6.2K resistor (nominal)
sinks current to VEE; if the external pull-up current is low
enough (<1mA, for example), the voltage drop across the
resistor will be big enough to look like a logic high signal (in
this example, 1mA * 6.2kΩ = 6.2V). This pin can thus be
used as an active High enable signal for an external module.

Note that for both versions, although this is a digital pin
functionally, the logic high level is determined by the external
pull-up device, and the power supply to which it is
connected; the IC will not clamp it below the VDD voltage.
Therefore, if the external device does not have its own
clamp, or if it would be damaged by a high voltage, then an
external clamp might be necessary.

OV (Over-Voltage) Pin 2 - This analog input compares the
voltage on the pin to an internal voltage reference (nominal

1.223V). When the input goes above the reference (low to
high transition), that signifies an OV (Over-Voltage)
condition, and the GATE pin is immediately pulled low to
shut off the external FET. Since there is 20mV of nominal
hysteresis built in, the GATE will remain off until the OV pin
drops below a 1.203V (nominal) high to low threshold. A
typical application will use an external resistor divider from
VDD to VEE, to set the OV level as desired; a three-resistor
divider can set both OV and UV.

UV (Under-Voltage) Pin 3 - This analog input compares the
voltage on the pin to an internal voltage reference (nominal

1.223V). When the input goes below the reference (high to
low transition), that signifies an UV (Under-Voltage)
condition, and the GATE pin is immediately pulled low to
shut off the external FET. Since there is 20mV of nominal
hysteresis built in, the GATE will remain off until the UV pin

pin pulls low (to VEE); this can be

rises above a 1.243V (nominal) low to high threshold. A
typical application will use an external resistor divider from
VDD to VEE, to set the UV level as desired; a three-resistor
divider can set both OV and UV.

If there is an Over-Current condition, the GATE pin is latched
off, and the UV pin is then used to reset the Over-Current
latch; the pin must be externally pulled below its trip point,
and brought back up (toggled) in order to turn the GATE
back on (assuming the fault condition has disappeared).

VEE Pin 4 - This is the most Negative Supply Voltage, such
as in a -48V system. Most of the other signals are
referenced relative to this pin, even though it may be far
away from what is considered a GND reference.

SENSE Pin 5 - This analog input measures the voltage drop
across an external sense resistor (between SENSE and
VEE), to determine if the current exceeds an Over-Current
trip point, equal to nominal (50mV / Rsense). Noise spikes of
less than 2µs are filtered out; if longer spikes need to be
filtered, an additional RC time constant can be added to
stretch the time (See Figure 29; note that the FET must be
able to handle the high currents for the additional time). To
disable the Over-Current function, connect the SENSE pin
to VEE.

GATE Pin 6 - This analog output drives the gate of the
external FET used as a pass transistor. The GATE pin is
high (FET is on) when UV pin is high (above its trip point);
the OV pin is low (below its trip point), and there is no Over­Current condition (VSENSE - VEE <50mV). If any of the 3
conditions are violated, the GATE pin will be pulled low, to
shut off the FET.

The Gate is driven high by a weak (-45µA nominal) pull-up
current source, in order to slowly turn on the FET. It is driven
low by a strong (32mA nominal) pull-down device, in order to
shut off the FET very quickly in the event of an Over-Current
or shorted condition.

DRAIN Pin 7 - This analog input compares the voltage of
the external FET DRAIN to the internal VPG reference
(nominal 1.7V), for the Power Good function.

Note that the Power Good comparator does NOT turn off the
GATE pin. However, whenever the GATE is turned off (by
OV, UV or SENSE), the Power Good Comparator will usually
then switch to the power-NOT-good state, since an off FET
will have the supply voltage across it.

VDD Pin 8 - This is the most positive Power Supply pin. It
can range from +10 to +80V (Relative to VEE). If operation
down near 10V is expected, the user should carefully
choose a FET to match up with the reduced GATE voltage
shown in the spec table.

2

ISL6140, ISL6150

www.BDTIC.com/Intersil

.

Absolute Maximum Ratings Thermal Information

Supply Voltage (VDD to VEE) . . . . . . . . . . . . . . . . . . . -0.3V to 100V

DRAIN, PWRGD, PWRGD Voltage . . . . . . . . . . . . . . . -0.3V to 100V

UV, OV Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V

SENSE, GATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 20V

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V

Thermal Resistance (Typical, Note 3) θ

8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

Operating Conditions

Temperature Range (Industrial) . . . . . . . . . . . . . . . . . .-40°C to 85°C

Temperature Range (Commercial). . . . . . . . . . . . . . . . . 0°C to 70°C

Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . 36V to 72V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

4. Typical value depends on VDD voltage; see Figure 13, “VGATE vs VDD” (<20V).

5. PWRGD is referenced to DRAIN; V

PWRGD-VDRAIN

= 0V.

Electrical Specifications VDD = +48V, VEE = +0V Unless Otherwise Specified. All tests are over the full temperature range; either

Commercial (0°C to 70°C) or Industrial (-40°C to 85°C). Typical specs are at 25°C.

(°C/W)

JA

PARAMETER SYMBOL

DC PARAMETRIC

Supply Operating Range V

Supply Current I

GATE PIN

Gate Pin Pull-Up Current I

Gate Pin Pull-Down Current I

External Gate Drive delta-

SENSE PIN

Circuit Breaker Trip Voltage V

SENSE Pin Current I

UV PIN

UV Pin High Threshold Voltage V

UV Pin Low Threshold Voltage V

UV Pin Hysteresis V

UV Pin Input Current I

OV PIN

OV Pin High Threshold Voltage V

OV Pin Low Threshold Voltage V

OV Pin Hysteresis V

OV Pin Input Current I

DD

DD

PU

PD

V

GATE

CB

SENSEVSENSE

UVH

UVL

UVHY

INUV

OVH

OVL

OVHY

INOV

TEST

LEVEL

TEST

CONDITIONS

UV = 3V; OV = VEE; SENSE = VEE;

= 80V

V

DD

Gate Drive on, V

Gate Drive off; any fault condition 24 32 70 mA

(V

GATE - VEE)

(V

GATE - VEE)

VCB = (V

UV Low to High Transition 1.213 1.243 1.272 V

UV High to Low Transition 1.198 1.223 1.247 V

VUV = V

OV Low to High Transition 1.198 1.223 1.247 V

OV High to Low Transition 1.165 1.203 1.232 V

VOV = V

GATE = VEE

, 17V ≤ VDD ≤ 80V 10 14 15 V

, 10V ≤ VDD ≤ 17V 4 5.4 6.2 15 V

- VEE) 405060mV

SENSE

= 50mV - 0 -0.5 µA

EE

EE

OR

NOTES

PART NUMBER

OR GRADE

UNITSMIN TYP MAX

10 - 80 V

0.6 0.9 1.3 mA

-30 -45 -60 µA

72050mV

- -0.05 -0.5 µA

72050mV

- -0.05 -0.5 µA

3

ISL6140, ISL6150

www.BDTIC.com/Intersil

Electrical Specifications VDD = +48V, VEE = +0V Unless Otherwise Specified. All tests are over the full temperature range; either

Commercial (0°C to 70°C) or Industrial (-40°C to 85°C). Typical specs are at 25°C. (Continued)

PARAMETER SYMBOL

DRAIN PIN

Power Good Threshold (L to H) V

Power Good Threshold (H to L) V

Power Good Threshold Hysteresis V

Drain Input Bias Current I

ISL6140 (PWRGD

PWRGD

Output Leakage I

ISL6150 (PWRGD PIN: H VERSION)

PWRGD Output Low Voltage (PWRGD-DRAIN) V

PWRGD Output Impedance R

AC TIMING

OV High to GATE Low

OV Low to GATE High

UV Low to GATE Low

UV High to GATE High

SENSE High to GATE Low

ISL6140 (L VERSION)

DRAIN Low to PWRGD

DRAIN High to PWRGD

ISL6150 (H VERSION)

DRAIN Low to (PWRGD-DRAIN) High

DRAIN High to (PWRGD-DRAIN) Low

Output Low Voltage V

PIN: L VERSION)

Low

High

tPHLOV

tPLHOV

tPHLUV

tPLHUV

tPHLSENSE

tPHLPG

tPLHPG

tPHLPG

tPLHPG

PGLHVDRAIN

PGHLVDRAIN

PGHY

DRAINVDRAIN

OH

OUT

Transition

Transition

(V

OL

OL

DRAIN

I

= 1mA

OUT

= 3mA - 0.88 1.20

I

OUT

= 5mA - 1.45 1.95 V

I

OUT

V

DRAIN

V

DRAIN

(V

DRAIN

(Figures 1, 3A) 0.6 1.6 3.0 µs

(Figures 1, 3A) 1.0 7.8 12.0 µs

(Figures 1, 3B) 0.6 1.3 3.0 µs

(Figures 1, 3B) 1.0 8.4 12.0 µs

(Figures 1, 2) 2 3 4 µs

(Figures 1, 4A) 0.1 0.9 2.0 µs

(Figures 1, 4A) 0.1 0.7 2.0 µs

(Figures 1, 4B) 5 0.1 0.9 2.0 µs

(Figures 1, 4B) 5 0.1 0.8 2.0 µs

TEST

TEST

CONDITIONS

- VEE, Low to High

- VEE, High to Low

= 48V 103560µA

- V

< V

EE)

PG

= 48V, V

= 5V, I

- V

EE)

OUT

< V

= 80V - 0.05 10 µA

PWRGD

= 1mA - 0.80 1.0 V

PG

LEVEL

OR

NOTES

PART NUMBER

OR GRADE

UNITSMIN TYP MAX

1.55 1.70 1.87 V

1.10 1.25 1.42 V

0.30 0.45 0.60 V

- 0.28 0.50 V

3.5 6.2 9.0 kΩ

4

Test Circuit and Timing Diagrams

www.BDTIC.com/Intersil

R = 5K

5V

OV

V

UV

PWRGD

V

1

OV

2

ISL6140

UV

V

EE

ISL6150

3

4

FIGURE 1. TYPICAL TEST CIRCUIT FIGURE 2. SENSE TO GATE TIMING

8

7

6

5

V

DD

DRAIN

GATE

SENSE

ISL6140, ISL6150

+

48V

-

V

DRAIN

V

SENSE

SENSE

GATE

50mV

t

PHLSENSE

1V

2V

0V

13V

GATE

0V

OV

1.223V 1.203V

t

PHLOV

1V

FIGURE 3A. OV TO GATE TIMING FIGURE 3B. UV TO GATE TIMING

DRAIN

PWRGD

1.8V

t

1.0V

PLHPG

FIGURE 4A. DRAIN TO PWRGD

2V

1.223V 1.243V

t

PHLUV

1V

t

PLHUV

1V

t

PLHOV

1V

UV
0V

13V

GATE

0V

FIGURE 3. OV AND UV TO GATE TIMING

1.8V

1.0V

t

PLHPG

t

PHLPG

1.4V

1.0V

t

PHLPG

1.4V

DRAIN

PWRGD

1.0V

TIMING (ISL6140) FIGURE 4B. DRAIN TO PWRGD TIMING (ISL6150)

FIGURE 4. DRAIN TO PWRGD

/PWRGD TIMING

5

ISL6140/ISL6150 Block Diagram

www.BDTIC.com/Intersil

ISL6140, ISL6150

GND

R4

R5

R6

3 UV

2 OV

, V

V

UVL

(1.223V)

+

­V

EE

EE

OVH

GND

8 V

DD

V

(INTERNAL

CC

-

+

VOLTAGE) AND

REFERENCE
GENERATOR

V

EE

C1

-

+

-

+

(50mV)

V

CB

+

­V

EE

V

CC

VPG (1.7V)
V

UVL

VCB (50mV)

LOGIC AND
GATE DRIVE

R2

, V

OVH

C2R3

PWRGD/PWRGD

OUTPUT DRIVE

-

+

VPG (1.7V)

+

­V

EE

7 DRAIN6 GATE5 SENSE4 V

1 PWRGD (6150)

1 PWRGD (6140)

CL

LOAD

RL

-48V IN

R1

Typical Values for a representative system; which
assumes:

36V to 72V supply range; 48 nominal; UV = 37V; OV = 71V

1A of typical current draw; 2.5 Amp Over-Current

100µF of load capacitance (CL); equivalent RL of 48Ω
(R = V/I = 48V/1A)

R1: 0.02Ω (1%)

R2: 10Ω (5%)

R3: 18kΩ (5%)

R4: 562kΩ (1%)

R5: 9.09kΩ (1%)

R6: 10kΩ (1%)

C1: 150nF (25V)

C2: 3.3nF (100V)

Q1: IRF530 (100V, 17A, 0.11Ω)

Q1

-48V OUT

Applications: Quick Guide to Choosing
Component Values

(See Block Diagram for reference)

This section will describe the minimum components needed
for a typical application, and will show how to select
component values. (Note that “typical” values may only be
good for this application; the user may have to select some
component values to match the system). Each block will
then have more detailed explanation of how it works, and
alternatives.

R4, R5, R6 - together set the Under-Voltage (UV) and Over­Voltage (OV) trip points. When the power supply ramps up
and down, these trip points (and their 20mV nominal
hysteresis) will determine when the gate is allowed to turn on
and off (the UV and OV do not affect the PWRGD output).
The input power supply is divided down such that when each
pin is equal to the trip point (nominal is 1.223V), the
comparator will switch.

V

= 1.223 (R4 + R5 + R6)/(R5 + R6)

UV

V

= 1.223 (R4 + R5 + R6)/(R6)

OV

The values of R4 = 562K, R5 = 9.09K, and R6 = 10K will
give trip points of UV = 37V and OV = 71V.

6