intersil ISL6113 DATA SHEET

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ISL6113, ISL6114

Data Sheet September 25, 2007

Dual Slot PCI-E Hot Plug Controllers

The ISL6113, ISL6114 both target the PCI-Express Add-in card hot swap application. Together with a pair of N-Channel and P-Channel MOSFETs, and two sense resistors per slot, either provides compliant hot plug power control to any combination of two PCI-Express X1, X4, X8 or X16 slots.

The ISL6113, ISL6114 feature a programmable current regulated (CR) maximum level for a programmable period to each voltage load so that both fault isolation protection and imperviousness to electrical transients are provided.

For each +12V supply, the CR level is set by a resistor value depending on the needs of the PCI-Express connector (X1, X4, X8 or X16) to be powered. This resistor is a sub-ohm standard value current sense resistor one for each slot and the voltage across this resistor is compared to a 50mV reference providing a nominal CR protection level adequately above the specific slot maximum limits. The 3.3V supply uses a 15mΩ sense resistor compared to a 50mV reference to provide 3.3A of maximum regulated current to all connector sizes. The

3.3VAUX is internally monitored and controlled to provide a nominal maximum of 1A of AUX output current.

FN6457.0

Features

• Dual PCI-E Slot Hot Swap Power Control and Distribution

• Highest Accuracy External R

Current Monitoring

SENSE

On Main Supplies

• Programmable Current Regu lation Prot ection F unctio n for X1, X4, X8, X16 Connectors

• Programmable Current Regu lation Durati on

• Programmable In-rush Protecti on Duri ng Turn-On

• Latch-off or Retry Modes After Failure

• Pb-free (RoHS Compliant)

Applications

• PCI-Express Servers

• Power Supply Distribution and Control

• Hot Swap/Electronic Breaker Circuits

• Network Hubs, Routers, Switches

• Hot Swap Bays, Cards and Modules

The CR period for each slot is set by a separate external capacitor on the associated CFILTER pin. Once the CR period has expired, the IC then quickly turns off its associated FETs thus unloading the faulted card from the supply voltage rails. A nominal 3.3V must always be present on the AUXI pin for proper IC bias; this should be the 3.3VAUX supply if used, if not the AUXI pin is tied directly to the 3VMAIN supply. Both ICs employ a card presence detection input that disables the MAIN and AUX enabling inputs if it is not pulled low. Output voltage monitoring with both PCI-E Reset Not and Power Good Not reporting along with OC Fault reporting are provided. Whereas the ISL6113 has the same GATE drive and response characteristics as the ISL6112, the ISL6114 has a lower turn-on GA TE drive curr ent allo wing for the use of smaller compensation capacitors and thus much faster response to Way Overcurrent (WOC) conditions. Additionally, the ISL6114 does not turn-on with the CR feature invoked as do the ISL6112, ISL6113 all owing for sho rter CR progra mmed periods.The ISL6113, ISL6114 are footprint compatible for all common pins, but not entirely function compatible with the ISL61 12’ s QFN package as there ar e I/O dif ferences.

IF 3.3VAUX NOT

IMPLEMENTED

12VSENSEA

12VINA

VSTBYA PRSNTB PRSNTA FORONA FORONB

AUXENA ONA AUXENB ONB GPI_A0 GPI_BO CFILTERA CFILTERB

GND VSTBYB

12VINB 3SENSEB

12VSENSEB

IF 3.3VAUX NOT IMPLEMENTED

FIGURE 1. TYPICAL ISL6113, ISL6114 BLOCK DIAGRAM

APPLICATION IMPLEMENTATION

12VOUTA

12VGATEA

12VGATEB

12VOUTB

ISL6113, ISL6114

3VINA

3VINB

3VSENSEA

3VGATEA

3VGATEB

3VOUTA

3VOUTB

VAUXA

FAULTA

PWRGDA

PERSTA GPO_A0 GPO_B0

PERSTB

PWRGDB

FAULTB

VAUXB

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6113, ISL6114

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Ordering Information

PART

NUMBER

ISL6113IRZA ISL6113 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL6113IRZA-T* ISL6113 IRZ -40 to +85 48 Ld 7x7 QFN Tape and Reel L48.7x7 ISL6114IRZA ISL6114 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL6114IRZA-T* ISL6114 IRZ -40 to +85 48 Ld 7x7 QFN Tape and Reel L48.7x7 ISL6113EVAL1Z ISL6113 Evaluation Platform ISL6114EVAL1Z ISL6114 Evaluation Platform *Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-free) PKG. DWG. #

Pinout

ISL6113, ISL6114

(48 LD QFN)

TOP VIEW

FAULT

CFILTERA

12VGATEA

GPI_A0

12VINA

PWRGDA

12VSENSEA

FORCE_ON

12VOUTA

VSTBYA

3VINA

GPO_A0

GPO_B0

48 47 46 45 44 43 42 41 40 39 38 37

2 3 4 5 6 7 8 9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

3VGATEA

3VSENSEA

AUXENA

GND

VAUXA

ONA

ONB

AUXENB

GND

(EXPOSED BOTTOM PAD)

GND (Exposed bottom pad)

GND

3VOUTA

PERST

L/R

PRSNT

VAUXB

3VOUTB

GPI_B0

3VGATEB

PERSTA

36 35 34 33 32 31 30 29 28 27 26 25

3VSENSEB

FAULTB CFILTERB

12VGATEB GND 12VINB

PWRGD NC

12VSENSEB FORCE_ON 12VOUTB VSTBYB 3VINB

FN6457.0

September 25, 2007

Functional Block Diagram (1 Channel)

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ISL6113, ISL6114

12VSENSE

12VIN

3VSENSE

3VIN

CFILTER

50mV

100mV*

VSTBY

REF

1.25V

ON/OFF

/OFF

ON AUXEN

12V

UVLO

ON/OFF

POWER-ON

RESET 250µs

UVLO

ON/ OFF

VSTBY

UVLO

VSTBY

LOGIC

VSTBY

VAUX CHARGE

PUMP AND

MOSFET

VAUX

OVERCURRENT

THERMAL

SHUTDOWN

VAUX

PWRGD

12VIN

3VIN

12V BIAS

ON/OFF

12VPWRGD

3VPWRGD

10.5V

2.8V

12VGATE

VAUX

3VGATE

FAULT

PERST

PWRGD

12VOUT

3VOUT

INT

FORCE_ON

GPI

BOTH A AND B SLOTS SHARE THE L/R PIN.

GPO

40kΩ x 2

L/R

PRSNT

GND

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ISL6113, ISL6114

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Pin Descriptions

PIN NAME FUNCTION

Asserting a FORCE_ON

9, 28 FORCE_ON

FORCE_ON

44, 43 ONA, ONB Enable input for MAIN outputs use to enable or disable MAIN voltage supply (12V and 3.3V) outputs. Taking ONX

45, 42 AUXENA, AUXENB 3.3VAUX Enable Input, enables the respective VAUX output. Pulling AUXENX low after a fault resets the

5, 32 12VINA,12VINB Connect to 12VMAIN supply and high side of sense resistor. This is one of two pins for Kelvin connection to

8, 29 12VSENSEA,

12VSENSEB

10, 27 12VOUTA,

12VOUTB

12, 25 3VINA, 3VINB Connect to 3VMAIN supply and high side of sense resistor. This provides one of two pins for Kelvin connection to

13, 24 3VSENSEA,

3VSENSEB

16, 21 3VOUTA,

3VOUTB

1, 36 FAULT

15, 22 VAUXA, VA UXB 3.3VAUX output to the PCI-E slot: This output connects to the V AUX pin of the PCI-E connector through an internal

11, 26 VSTBYA

VSTBYB

41 L/R

40, 39 PRSNT

6, 31 PWRGD

PWRGD

4, 38 GPI_A0, GPI_B0 ~5ms debounced user attention input, driven by either a mechanical switch or digital signal form higher level

48, 47 GPO_A0, GPO_B0 User attention output, that can be used to drive LEDs, alarms or other attention getting devices. Open drain with

A, B

over riding the ON input and the UV, OC and short circuit protections on those outputs. UVLO protection for the VSTBY input is not affected by the FORCE_ON outputs to enter their open-drain state. This input is internally pulled high to the VAUX rail. Functionality is disabled when PRSNT

low after a fault resets the respective slots Main Output Fault Latch. Functionality is disabled when PRSNT

associated slot’s VAUX fault latch. Functionality is disabled when PRSNT

measure the 50mV CR Vth. An undervoltage lockout prevents the IC main supply function until 12VIN >10V . The current regulation threshold is set by connecting a sense resistor between this pin and 12VSENSE. When the current-limit threshold of IR = 50mV is reached, the 12VGATE pin is modulated to maintain a constant 50mV voltage across the sense resistor and thereby a constant current is passed into the load. If the 50mV threshold is maintained for CR duration, the circuit breaker is tripped and both GATE pins for the affected slot turn off the switch FETs and thus turn off the supplies to the slot.

12V current sense low side input. This is the second of two pins for Kelvin connection to the R the 50mV CR Vth. The CR limits are set by connecting a sense resistor between each of these pins and associated 12VIN pin.

12V output voltage monitor for UV condition. This is the voltage input downstream of the MOSFET that is delivered to the add-in card load.

measure the 50mV CR Vth. Undervoltage lockout (UVLO) prevents turn-on until 3VIN >2.75V. The current regulation threshold is set by connecting a sense resistor between this pin and 3VSENSE. When the current-limit threshold of IR = 50mV is reached, the 3VGATE pin is modulated to maintain a constant 50mV voltage across the sense resistor and thereby a constant current is passed into the load. If the 50mV threshold is maintained for the CR duration, the circuit breaker is tripped and both FETs for the affected slot are turned-off.

3.3V current sense low side input. This provides the second of two pins for Kelvin connection for measuring the 50mV CR Vth. The CR limits are set by connecting a sense resistor between each of these pins and associated 3VINX pin.

3.3V output voltage monitor for UV condition. This is the voltage downstream of the MOSFET that is delivered to the add-in card load.

A, FAULTB An open drain output which is pulled low whenever the CR duration has expired due to an OC fault condition on

A, PRSNTB The card presence detection input disables the operation of the FORCE_ON, ON and AUXEN inputs if not pulled

any of the MAIN or the AUX supplies or in the event of an IC over-temperature condition. If fault latch is invoked by a MAIN (+12V , +3.3V) supply fault, then it is reset by pulling the faulted slot’s ON pin low . if fault was asserted because of an OC fault condition on the slot’s AUX output then pulling the AUXEN input low will reset the latch. Both enabling inputs must be pulled low to clear a fault condition on both the MAIN and VAUX outputs of the same slot. Internal over-temperature limit is ~+140°C with a +20°C hysteresis.

0.3Ω FET. This output is current regulated to ~1A.

3.3V bias input for the IC, and internal VAUX switches. V from a dedicated 3.3V or 3VMAIN if AUX supply not implemented.

Latch-off or Retry bar input. Tying this input low invokes a periodic retry to turn-on after current regulation timer has expired on both slots. Leaving this pin open provides a latch-off operational mode after CR period has expired. In this mode turn-on is initiated by cycling the appropriate EN input(s). This pin is internally pulled up to VSTBY.

to GND. If after turn-on, the PRSNT immediately.

A POWER GOOD NOT signal that is asserted low while all output voltages are compliant.

controller.

90mA pull-down capability.

is high.

input low will turn on the MAIN and AUX supplies to the respective slot in a forced mode

pins. Asserting FORCE_ON will cause the PWRGD and FAULT

is high.

to measure

SENSE

must always be present for proper IC bias, either

VSTBY

input goes high then all associated outputs (MAIN and AUX) are turned off

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ISL6113, ISL6114

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Pin Descriptions (Continued)

PIN NAME FUNCTION

3, 34 12VGATEA,

14,

37, 18 PERST

2, 35 CFILTERA,

17, 33,

7,19, 20,

12VGATEB

3VGATEA,

3VGATEB

PERST

CFILTERB

GND IC ground reference

NC No Connect

12VMAIN gate drive output, connects to gate of an external P-Channel MOSFET. During power-up, this pin is pulled down with a 25µA (5µA for ISL6114) current to control the dv/dt ramp of the output voltage to the slot. During CR, the voltage on this pin is modulated to maintain a constant current into the load. During power-down or latch-off for an overcurrent fault, this pin is pulled high to 12VIN by internal sources.

3VMAIN gate drive outputs connects to gate of an external N-Channel MOSFET . During power-up this pin charges up with a 25µA (5µA for ISL6114) current to control the dv/dt ramp of the output voltage to the slot load. During CRTIM the voltage on this pin is modulated to maintain a constant current into the load. During power-down or latch-off for an overcurrent fault this pin is pulled low by internal sources.

100ms delayed report of MAIN supplies output voltage compliance.

A capacitor connected between each of these pins and ground sets the current regulated duration (tFIL TER) for each slot. tFILTER is the amount of time for which a slot remains in current limit before its circuit breaker is tripped.

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ISL6113, ISL6114

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Absolute Maximum Ratings (Note 3) Thermal Information

12VIN, 12VSENSE, 12VOUT . . . . . . . . . . . . . . . . . . . . . . . . +14.5V

VSTBY, 3VIN, 3VSENSE, 3VOUT. . . . . . . . . . . . . . . . . . . . . . . +7V

12VGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 12VI

3VGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 12VI

Logic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +5.5V

VAUX Output Current . . . . . . . . . . . . . . . . . .Short Circuit Protected

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V

Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

2. For θ

3. All voltages are relative to GND, unless otherwise specified.

, the “case temp” location is the center of the exposed metal pad on the package underside.

Thermal Resistance (Typical, N otes 1, 2) θ

48 Ld 7x7 QFN Package . . . . . . . . . . . 27 3

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

12VMAIN Supply Voltage Range. . . . . . . . . . . . . . . . . . +12V ± 10%

3VMAIN Supply Voltage Range. . . . . . . . . . . . . . . . . . .+3.3V ± 10%

AUXI Supply Voltage Range . . . . . . . . . . . . . . . . . . . . .+3.3V ± 10%

Temperature Range (T

) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

(°C/W) θJC (°C/W)

Electrical Specifications 12VIN = 12V, 3VIN and VSTBY = +3.3V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

MAIN CURRENT REGULATION

Current Limit Threshold Voltages VTHILIMIT V Fast-Trip Threshold Voltages VTHFAST V

VSENSE Input Current ISENSE 0.1 µA CFILTER Threshold Voltage VFILTER 1.20 1.25 1.30 V CFILTER Charging Current

Nominal Current Limit Duration =

x 550k

FILTER

AUXILIARY CURRENT REGULATION

Regulated Current Level ILIM(AUX) From end of ISC(TRAN) to

Output MOSFET Resistance VAUX MOSFET

Off-State Output Offset Voltage VAUX VOFF(VAUX) VAUX = Off, T

BIAS AND POWER GOOD

Supply Current ICC12 Enabled with no load current 0.9 1.5 mA

12VIN, 3VIN, VSTBY Undervoltage Lockout Thresholds

Undervoltage Lockout Hysteresis 12VIN, 3VIN

IFILTER V

tFILTER CFILTER Open 10 µs

ICC3.3 Enabled with no load current 0.1 0.2 mA ICCSTBY Enabled with no load current 5 6 mA VUVLO (12V) 12VIN increasing 8 9 10 V VUVLO (3V) 3VIN increasing 2.1 2.5 2.75 V VUVLO(STBY) VSTBY increasing 2.8 2.9 2.96 V VHYSUV 180 mV

DS(AUX)

– V

VIN

CFILTER time-out

= 375mA, T

= TJ = -40°C to +85°C, Unless Otherwise Specified.

47.5 50 52.5 mV

SENSE

(ISL6113) 85 100 115 mV

SENSE

(ISL6114) 140 150 160 mV

SENSE

VSENSE

> V

THILIMIT

2 2.5 3 µA

0.8 1 1.2 A

= +125°C 350 mΩ

= +125°C 40 mV

FN6457.0

September 25, 2007

ISL6113, ISL6114

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Electrical Specifications 12VIN = 12V, 3VIN and VSTBY = +3.3V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Undervoltage Lockout Hysteresis VSTBY

Power-Good Undervoltage Thresholds VUVTH(12V) 12V

Power-Good Detect Hysteresis VHYSPG 30 mV

GATE DRIVE

12VGATE Voltage VGATE(12V) Max Gate Voltage when Enabled 0 0.55 V ISL6113 12VGATE Sink Current IGATE (12VSINK) Start Cycle 17 25 35 µA ISL6114 12VGATE Sink Current Start Cycle 3 5 7 µA 12VGATE Source Current (Fault Off)

(Absolute Value) 3VGATE Voltage VGATE(3V) Min Gate voltage when Enabled 12V ISL6113 3VGATE Source Current IGATE(3VCHARGE) Start Cycle 17 25 35 µA ISL6114 3VGATE Source Current Start Cycle 3 5 7 µA 3VGATE Sink Current (Fault Off) IGATE(3VSINK) Any fault condition

ANALOG I/O DC PARAMETERS

GPO Pull-Down Current I LOW-Level Input Voltage ON, AUXEN,

GPI, FORCE_ON Output LOW Voltage FAULT

GPO, PERST HIGH-Level Input Voltage ON, AUXEN,

GPI,FORCE_ON Internal Pull-ups to VSTBY (Note 4) RPULLUP 40 50 kΩ 12VIN, 3VIN Input Leakage Current ILKG,OFF XVIN VSTBY = +3.3V, 12VIN = OFF;

Input/Output Leakage Current, ON, AUXEN, GPO, FORCE_ON

Off-State Leakage Current FAULT PWRGD

Output Discharge Resistance RDIS (12V) 12V

PERST Pull-Down Current when Asserted.

THERMAL PROTECTION

Over-temperature Shutdown and Reset Thresholds with Overcurrent on Slot

Over-temperature Shutdown and Reset Thresholds, all other Conditions (all Outputs will Latch OFF)

, GPI

, PRSNT

, PWRGD,

, PRSNT

, PERST,

VHYSSTBY 50 mV

OUT

VUVTH(3V) 3V VUVTH(VAUX) VAUX decreasing 2.55 2.8 3.0 V

IGATE (12VPULLUP)

GPO_OUT

VIL 0.8 V

VOL IOL = 3mA 0.4 V

VIH 2.1 5 V

IIL -2 2 µA

ILKG(OFF) GPI I

RDIS (3V) 3V RDIS (VAUX) 3VAUX = 1.65V 350 400 Ω I

PERST

tOVER T

OUT

Any fault condition (VDD – VGATE) = 2.5V

VGATE = 2.5V

3VIN = OFF

LKG

measured with VAUX OFF

OUT

ONX is low 30 mA

increasing, each slot 140 °C

decreasing, each slot 130 °C

increasing, both slots 160 °C

decreasing, both slots 150 °C

= TJ = -40°C to +85°C, Unless Otherwise Specified. (Continued)

decreasing 10.15 10.5 10.75 V

decreasing 2.7 2.8 2.9 V

35 72 mA

for these two pins

- 0.55 12V

80 105 mA

80 mA

0.5 1 µA

-2 2 µA

= 6.0V 1400 1850 Ω

= 1.65V 140 180 Ω

FN6457.0

September 25, 2007

ISL6113, ISL6114

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Electrical Specifications 12VIN = 12V, 3VIN and VSTBY = +3.3V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

I/O TIMING PARAMETERS

12V Current Limit Response Time

3.3V Current Limit Response Time t

VAUX Current Limit Response Time t Delay from MAIN Overcurrent to FAUL T

output Delay from VAUX Overcurrent to F AUL T

Output

ON, AUXEN, PRSNT Power-On Reset Time after VSTBY

Becomes Valid Auto-Retry Period t Presence Detect Delay to Auto Enable t Presence Detect Delay to Disable t GPI to GPO Propagation Delay t Delay of Main Power Good to Reporting t Power Supply Disabled to PERST Low t

NOTE:

4. Limits should be considered typical and are not production tested.

Min Pulse Width t

t or 3V FAULT)

CGATE = 25pF

OFF(12V)

CGATE = 25pF

OFF(3V)

SC(TRAN) PROP

PROP

min POR

RETRY PRSNT_ON PRSNT_OFF GPI-GPO PVPERL PERST

VAUX = 0V, VSTBY = +3.3V 2.5 µs

(12V FAULT

(VAUXFAULT) I

100 ns

250 µs

VIN – VSENSE = 140mV

CFILTER = 0 VIN – VSENSE = 140mV

LIM(AUX)

CFILTER = 0 VAUX output grounded

R/L tied to GND, Any OC Event 0.75 1.4 3 s PRSNT = high to low 4 6.5 9 ms PRSNT = low to high 2.5 µs GPI high/low to GPO high/low 4 6 8 ms PWRGD low to PERST high. 105 145 185 ms ON Low to PERST Low 100 ns

to FAULT output

= TJ = -40°C to +85°C, Unless Otherwise Specified. (Continued)

1 2.1 µs

0.3 1 µs

1 µs

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