intersil ISL5861 DATA SHEET

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ISL5861

Data Sheet September 2001

12-bit, +3.3V, 130/210+MSPS, CommLink

High Speed D/A Converter

The ISL5861 is a 12-bit, 130/210+MSPS (Mega Samples

Per Second), CMOS, high speed, low power, D/A (digital to analog) converter, designed specifically for use in high performance communication systems such as base transceiver stations utilizing 2.5G or 3G cellular protocols.

This device complements the CommLink ISL5x61 family of high speed converters, which include 10, 12, and 14-bit devices.

Ordering Information

TEMP.

PART

NUMBER

ISL5861IB -40 to 85 28 Ld SOIC M28.3 130MHz

ISL5861IA -40 to 85 28 Ld TSSOP M28.173 130MHz

ISL5861/2IB -40 to 85 28 Ld SOIC M28.3 210MHz

ISL5861/2IA -40 to 85 28 Ld TSSOP M28.173 210MHz

ISL5861EVAL1 25 SOIC Evaluation Platform 210MHz

RANGE

(

C) PACKAGE

PKG.

NO.

CLOCK SPEED

Pinout

ISL5861

TOP VIEW

File Number 6008.1

Features

• Speed Grades . . . . . . . . . . . . . . . . 130M and 210+MSPS

• Low Power . . . . . 103mW with 20mA Output at 130MSPS

• Adjustable Full Scale Output Current. . . . . 2mA to 20mA

• +3.3V Power Supply

• 3V LVCMOS Compatible Inputs

• Excellent Spurious Free Dynamic Range (73dBc to Nyquist, f

= 130MSPS, f

OUT

= 10MHz)

• UMTS Adjacent Channel Power =70dB at 19.2MHz

• EDGE/GSM SFDR = 90dBc at 11MHz in 20MHz Window

• Pin compatible, 3.3V, Lower Power Replacement For The AD9752 and HI5860

Applications

• Cellular Infrastructure - Single or Multi-Carrier: IS-136, IS95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA

• BWA Infrastructure

• Medical/Test Instrumentation

• Wireless Communication Systems

• High Resolution Imaging Systems

• Arbitrary Waveform Generators

D11 (MSB)

D10

D0 (LSB)

DCOM

CLK

DCOM

COMP

IOUTA

IOUTB

ACOM

FSADJ

REFIO

REFLO

SLEEP

CAUTION: These devices are se nsitive t o electrostati c discharge; f ollow proper IC Handling Proce dures.

1-888-INTERSIL or 321-724-7143

| Intersil and Design is a trademark of Intersil Americas Inc.

60096009CommLink™ is a trademark of Intersil Americas Inc.

Typical Applications Circuit

50Ω

BEAD

10µF

10µH

0.1µF

D11

D10

ISL5861

D11 (MSB) (1)

D10 (2)

D9 (3)

D8 (4)

D7 (5)

D6 (6)

D5 (7)

D4 (8)

D3 (9)

D2 (10)

D1 (11)

D0 (LSB) (12)

CLK (28) DCOM (26, 13, 14)

(27)

(25, 19) NC

(15) SLEEP

(16) REFLO

(17) REFIO

(18) FSADJ

(22) IOUTA

(21) IOUTB

(23) COMP

(20) ACOM

(24) AV

ONE CONNECTION

ACOMDCOM

0.1µF

50Ω

1:1, Z1:Z2

0.1µF

(50Ω)

0.1µF

FERRITE

BEAD

10µH

10µF

SET

1.91kΩ

REPRESENTS

ANY 50Ω LOAD

+3.3V (VDD)

Functional Block Diagram

(LSB) D0

D10

D11

CLK

INPUT

LATCH

UPPER

5-BIT

DECODER

IOUTA IOUTB

SWITCH

MATRIX

INT/EXT

VOLTAGE

REFERENCE

CASCODE

CURRENT

SOURCE

SEGMENTS

GENERATION

7 LSBs

31 MSB

BIAS

COMP

REFLO

REFIO

FSADJ SLEEP

ISL5861

Pin Descriptions

PIN NO. PIN NAME DESCRIPTION

1-12 D11 (MSB) Through

D0 (LSB)

15 SLEEP Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin

16 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AV

17 REFIO Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is

18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current

19, 25 NC No Connect. These should be grounded, but can be left disconnected.

21 IOUTB The complementary current output of the device. Full scale output current is achieved when all input bits are

22 IOUTA Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.

23 COMP Connect 0.1µF capacitor to ACOM.

24 AV

20 ACOM Connect to Analog Ground.

26, 13, 14 DCOM Connect to Digital Ground.

27 DV

28 CLK Clock Input.

Digital Data Bit 11, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).

has internal 20µA active pulldown current.

to disable internal reference.

enabled. Use 0.1µF cap to ground when internal reference is enabled.

= 32 x V

FSADJ/RSET

set to binary 0.

Analog Supply (+3.0V to +3.6V).

Digital Supply (+3.0V to +3.6V).

ISL5861

Absolute Maximum Ratings Thermal Information

Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +3.6V

Analog Supply Voltage AV

to ACOM . . . . . . . . . . . . . . . . . +3.6V

Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DV

Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV

Analog Output Current (I

) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA

OUT

DD DD

+ 0.3V + 0.3V

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

1. θ

Thermal Resistance (Typical, Note 1) θ

(oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . -65

C to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

Electrical Specifications AV

PARAMETER TEST CONDITIONS

= DVDD = +3.3V, V

= Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values

REF

= -40oC TO 85oC

UNITSMIN TYP MAX

SYSTEM PERFORMANCE

Resolution 12 - - Bits

Integral Linearity Error, INL “Best Fit” Straight Line (Note 7) -1.25 ±0.5 +1.25 LSB

Differential Linearity Error, DNL (Note 7) -1 ±0.5 +1 LSB

Offset Error, I

Offset Drift Coefficient (Note 7) - 0.1 - ppm

IOUTA (Note 7) -0.006 +0.006 % FSR

FSR/

Full Scale Gain Error, FSE With External Reference (Notes 2, 7) -3 ±0.5 +3 % FSR

With Internal Reference (Notes 2, 7) -3 ±0.5 +3 % FSR

Full Scale Gain Drift With External Reference (Note 7) - ±50 - ppm

With Internal Reference (Note 7) - ±100 - ppm

Full Scale Output Current, I

2-20mA

FSR/

Output Voltage Compliance Range (Note 3) -1.0 - 1.25 V

DYNAMIC CHARACTERISTICS

Maximum Clock Rate, f

CLK

ISL5861/2IA, ISL5861/2IB 210 250 - MHz

ISL5861IA, ISL5861IB 130 150 - MHz

Output Rise Time Full Scale Step - 1.5 - ns

Output Fall Time Full Scale Step - 1.5 - ns

Output Capacitance -10 - pF

Output Noise IOUTFS = 20mA - 50 - pA/√Hz

IOUTFS = 2mA - 30 - pA/√Hz

AC CHARACTERISTICS (Using Figure 13 with R

Spurious Free Dynamic Range, SFDR Within a Window

= 210MSPS, f

CLK

= 210MSPS, f

CLK

= 130MSPS, f

CLK

= 50Ω and R

DIFF

= 50Ω, Full Scale Output = -2.5dBm)

LOAD

= 80.8MHz, 30MHz Span (Notes 4, 7) - 73 - dBc

OUT

= 40.4MHz, 30MHz Span (Notes 4, 7) - 80 - dBc

OUT

= 20.2MHz, 20MHz Span (Notes 4, 7) - 85 - dBc

OUT

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