The ISL5586 is a very low
power Ringing Subscriber
Interface circuit designed for
use with the Broadcom
BCM3352 Cable Modem Chip,
with on-board voiceband codecs, or other 3.3V voiceband
codec devices.
The ISL5586 provides on board ringing signal generation up
to 95V peak supporting sinusoidal or trapezoidal
waveshapes with DC offset. Loop start and ground start
trunks are supported, and an open circuit DC voltage of less
than 56V is maintained on the subscriber loop in the on-hook
condition, in compliance with MTU operation and the safety
requirements of UL-1950.
Together with the Broadcom BCM3352, the ISL5586
provides resistive and complex two wire impedance
matching and transhybrid balancing. Also supported are onhook transmission of caller id signals, soft and hard polarity
reversal and 12/16kHz subscriber pulse metering systems
used in Europe and Asia, thereby allowing a low cost, low
risk, global product design to be achieved.
Related Literature
• Evaluation Board for the ISL5586 family AN9918
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
FN4924.2
Features
• Interfaces to Broadcom 3352 cable modem device
• Very low on-hook power consumption
- 64mW @ Vbh = 75V
• User Programmable constant current to the subscriber
loop
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
BL
BATTERY
SWITCH
SENSING
LOGIC
BH
CONTROL
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2001, 2004. All Rights Reserved
ILIM
TIP
RING
TL
1
CDCP
POLCDCMV
DC
CONTROL
2-WIRE
PORT
TRANSIENT
CURRENT
LIMIT
INTERNAL
LOOP BACK
RSLIC18™ is a trademark of Intersil Corporation. All other trademarks mentioned are the property of their respective owners.
RINGING
PORT
4-WIRE
PORT
LOGIC
BSEL
V
V
V
V
-IN
V
V
V
V
F2
F1
F0
RSP
RSM
RXP
RXM
ZO
FB
TXP
TXM
ISL5586
www.BDTIC.com/Intersil
Ordering Information
HIGH BATTERY (V
BH
PART NUMBER
ISL5586FCM
ISL5586FCMZ (Note)
ISL5586FCMZ-T (Note)
ISL5586BIM
ISL5586BIMZ (Note)
ISL5586CIM
ISL5586CIMZ (Note)
ISL5586DIM
ISL5586DIMZ (Note)
••
••
••
••
••
••
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
LONGITUDINAL
)
BALANCE
TEMP.
RANGE (°C)PACKAGE
••
••
••
0 to 7528 Ld PLCCN28.45
0 to 7528 Ld PLCC (Pb-free)N28.45
0 to 7528 Ld PLCC Tape and Reel (Pb-free)N28.45
-40 to 8528 Ld PLCCN28.45
-40 to 8528 Ld PLCC (Pb-free)N28.45
-40 to 8528 Ld PLCCN28.45
-40 to 8528 Ld PLCC (Pb-free)N28.45
-40 to 8528 Ld PLCCN28.45
-40 to 8528 Ld PLCC (Pb-free)N28.45
PKG.
DWG. #100V85V75V58dB53dB
Device Operating Modes
MODEF2F1F0DETDESCRIPTION
Low Power Standby (LPS)000SHD MTU compliant on hook operating mode.
Forward Active (FA)001SHD MTU compliant and OHT capable on hook mode, off hook loop feed mode.
Unused010n/aReserved for internal purposes.
Reverse Active (RA)011SHD Signalling mode which reverses direction of loop current, otherwise like Forward Active.
Ringing100RTDSignalling mode used to generate high voltage balanced ringing signal.
Forward Loop Back (FLB)101SHD Internal loop back mode which connects internal load across Tip and Ring terminals.
Tip Open/Ground Start (TO) 110SHD Signalling mode sets Tip to high impedance state, Ring output still active.
Power Denial (PD)111n/aLoop disconnect mode which forces both Tip and Ring to high impedance.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Maximum Storage Temperature Range. . . . . . . . . . -65
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
(PLCC - Lead Tips Only)
(oC/W)
JA
o
C to 150oC
Die Characteristics
o
C to 85oC
= -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V, AGND = BGND = 0V,
loop current limit = 25mA. All AC Parameters are specified at 600
frequency band of 300Hz to 3.4kHz. Protection resistors = 0
product offering.
Electrical SpecificationsUnless Otherwise Specified, T
loop current limit = 25mA. All AC Parameters are specified at 600
frequency band of 300Hz to 3.4kHz. Protection resistors = 0
product offering. (Continued)
PARAMETERTEST CONDITIONSMINTYPMAXUNITS
Amplitude Tracking, Off Hook, 2-Wire to 4-Wire, 4-Wire to
2-Wire, 4-Wire to 4-Wire
Amplitude Tracking, ON-Hook0dBmo to -37dBmo, f = 1004Hz,
Signal to Distortion, 2-Wire to 4-Wire, 4-Wire to 2-Wire,
4-Wire to 4-Wire, ON-Hook and OFF-Hook
Signal Frequency Distortion (0Hz to 12kHz)0dBmo input, 0 Hz ≤ f ≤ 12kHz2845-dB
Single Frequency Distortion (0Hz to 4kHz)0dBmo Input, 1004Hz ≤ f ≤ 1024Hz4050-dB
Intermodulation Distortion, 2-Wire to 4-Wire,
4-Wire to 2-Wire, 4-Wire to 4-Wire
(IEEE Standard 743-1984)
f = 300Hz ≤ f ≤ 3400Hz-45-dB
f = 8kHz ≤ f ≤ 16kHz-28-dB
to 4-Wire, BSEL = 0.8Vf = 50Hz-70-dB
V
CC
f = 300Hz ≤ f ≤ 3400Hz-55-dB
f = 8kHz ≤ f ≤ 16kHz-40-dB
V
to 2-Wire, BSEL = 0.8Vf = 50Hz-25-dB
BL
f = 300Hz ≤ f ≤ 3400Hz-38-dB
f = 8kHz ≤ f ≤ 16kHz-28-dB
to 4-Wire, BSEL = 0.8Vf = 50Hz-27-dB
V
BL
f = 300Hz ≤ f ≤ 3400Hz-36-dB
f = 8kHz ≤ f ≤ 16kHz-23-dB
V
to 2-Wire, BSEL = 2.0Vf = 50Hz-27-dB
BH
f = 300Hz ≤ f ≤ 3400Hz-35-dB
f = 8kHz ≤ f ≤ 16kHz-23-dB
5
FN4924.2
November 3, 2004
ISL5586
www.BDTIC.com/Intersil
Electrical SpecificationsUnless Otherwise Specified, T
loop current limit = 25mA. All AC Parameters are specified at 600
frequency band of 300Hz to 3.4kHz. Protection resistors = 0
product offering. (Continued)
PARAMETERTEST CONDITIONSMINTYPMAXUNITS
VBH to 4-Wire, BSEL = 2.0Vf = 50Hz-76-dB
NOTES:
2. These parameters are controlled via design and Statistical Process Control and are not directly tested. These parameters are characterized upon
initial design release and upon design changes which would affect these characteristics.
3. Input voltage = 0.636V
4. Tested per IEEE455-1985, with 368Ω resistorsconnected to the Tip and Ring terminals.
5. These parameters are tested 100% at room temperature, and are guaranteed but not tested across the full temperature range via statistical
characterization and design.
6. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current limits.
7. Characterized with 2 x 10us and 10 x 1000us first level lightning surge waveform (GR-1089-CORE).
f = 300Hz ≤ f ≤ 3400Hz-55-dB
f = 8kHz ≤ f ≤ 16kHz-42-dB
for VBH = -85V and 0.460V
for -75V devices.
RMS
Design Equations
Refer to Figure 14 for programming resistor connections.
Loop Supervision Thresholds
SWITCH HOOK DETECT
The desired switch hook detect threshold current (I
a single external resistor, R
R
615 ISH⁄=
SH
as follows
SH
) is set by
SH
(EQ. 1)
The loop current threshold programming range is from 5mA
to 15mA.
RING TRIP DETECT
The ring trip detect threshold (I
resistor, R
R
RT
should be set between the peak ringing current and the
I
RT
RT
1800 IRT⁄=
as follows.
) is set by a single external
RT
(EQ. 2)
peak off hook current while still ringing. In addition, the ring
trip current must be set below the transient current limit
including tolerances. The ringing signal filter capacitor C
in parallel with R
sets the ring trip response time.
RT
RT
LOOP CURRENT LIMIT
The DC loop current limit (I
external resistor R
1760
------------ -=
R
IL
I
LIM
as follows.
IL
) is programmed by the
LIM
(EQ. 3)
The loop current limit programming range is from 15mA to
45mA.
Impedance Matching
The AC source impedance of the SLIC is programmed with
the external impedance network Z
synthesize and match Resistive line terminations the
programming network is simply a resistor (R
as described next. To
S
) as shown in
S
,
Figure 14. For complex line terminations such as the one
illustrated in Figure 1, a complex programming network is
required.
RESISTIVE IMPEDANCE SYNTHESIS
The AC source resistance of the SLIC is synthesized with a
single external resistor R
400
R
SZ0
--------- -
×133.3 Z
3
The synthesized resistance (Z
as follows:
S
()==
0
) is determined by the
0
(EQ. 4)
characteristic line resistance and protection resistors as
shown in Equation 5.
Z
ORL
RP1RP2+()–=
(EQ. 5)
COMPLEX IMPEDANCE SYNTHESIS
A complex network is used in place of RS when the termination
impedance of the line is complex as shown in Figure 1.
2-WIRE TERMINATION
IMPEDANCE (ZL)
C
2
R
1
R
2
FIGURE 1. COMPLEX PROGRAMMING NETWORK
The component R
R
used for resistive impedance synthesis. The design
S
has a different design equation than the
S
PROGRAMMING
NETWORK (ZS)
C
P
R
S
R
P
equations for each component are provided below where
RP1 and RP2 are the protection resistors and R
P
is a
component of the programming network.
RS133.3R1 RP1–RP2–()×=
R
P
133.3 R2×=
(EQ. 6)
(EQ. 7)
6
FN4924.2
November 3, 2004
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