The Intersil ISL54200 dual 2:1 multiplexer IC is a single
supply part that can operate from a single 2.7V to 5.5V supply .
It contains two SPDT (Single Pole/Double Throw) switches
configured as a DPDT. The part was designed for switching
between USB High-Speed and USB Full-Speed sources in
portable battery powered products.
The 7
Ω normally-closed (NC) FSx switches can swing rail to
rail and were specifically designed to pass USB full speed
data signals (12Mbps) that range from 0V to 3.6V. The 4.5
normally-open (NO) HSx switches have high bandwidth and
low capacitance and were specifically designed to pass USB
high speed data signals (480Mbps) with minimal di stortion.
The part can be used in Personal Media Players and other
portable battery powered devices that need to switch between
a high-speed transceiver and a full-speed transceiver while
connected to a single USB host (computer).
The digital logic inputs are 1.8V logic compatible when
operated with a 2.7V to 3.6V supply. The part has an enable
pin to open all switches. It can be used to facilitate pro per bus
disconnect and connection when switching between the USB
sources.
The ISL54200 is available in a 10 Ld 3mmx3mm TDFN and a
small 10 Ld 2.1mmx1.6mm µTQFN packages. It operates
over a temperature range of -40 to +85°C.
Ω
FN6408.0
Features
• High Speed (480Mbps) and Full Speed (12Mbps)
Signaling Capability per USB 2.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
Pinouts
ISL54200
(10 LD TDFN
TOP VIEW
VDD
COMD1
COMD2
GND
1
IN
2
3
4
5
LOGIC
CONTROL
4M
EN
10
9
HSD1
8
HSD2
7
FSD1
6
FSD2
NOTE:
1. ISL54200 Switches Shown for IN = Logic “0” and EN = Logic “1”.
Ordering Information
ISL54200
VDD
COMD1
COMD2
ISL54200
(10 LD µTQFN)
TOP VIEW
EN
10
4M
HSD1
1
IN
2
3
4
LOGIC
CONTROL
5
GND
9
HSD2
8
FSD1
7
FSD2
6
PART NUMBER
(Note)
PART
MARKINGTEMP. RANGE (°C)PACKAGE (Pb-Free)PKG. DWG. #
ISL54200IRZ200Z-40 to +8510 Ld 3x3 TDFN L10.3x3A
ISL54200IRZ-T200Z-40 to +8510 Ld 3x3 TDFN Tape and ReelL10.3x3A
ISL54200IRUZ-TFM-40 to +8510 Ld 2.1x1.6mm μTQFN Tape and ReelL10.2.1x1.6A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Truth Table
ISL54200
ENINFSD1, FSD2HSD1, HSD2
10ONOFF
11OFFON
0XOFFOFF
Logic “0” when ≤0.5V, Logic “1” when ≥1.4V with a 2.7V to 3.6V
Supply. X = Don’t Care
Pin Descriptions
ISL54200
PIN NO.NAMEFUNCTION
1VDDPower Supply
2INSelect Logic Control Input
3COMD1USB Common Port
4COMD2USB Common Port
5GNDGround Connection
6FSD1Full Speed USB Differential Port
7FSD2Full Speed USB Differential Port
8HSD1High Speed USB Differential Port
9HSD2High Speed USB Differential Port
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on FSD1, FSD2, HSD1, HSD2, COMD1, COMD2, EN, IN exceeding V
maximum current ratings.
3. θ
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
OFF IsolationV
FSx Switch -3dB BandwidthSignal = -10dBm, 1.0VDC offset, R
HSx Switch -3dB BandwidthSignal = -10dBm, 0.2VDC offset, R
HSx OFF Capacitance, C
Input Voltage Low, V
Input Voltage High, V
Input Current, I
Input Current, I
Input Current, I
INL, IENL
INH
ENH
INL
INH
, V
, V
ENL
ENH
V
= 2.7V to 3.6VFull--0.5V
DD
V
= 2.7V to 3.6VFull1.4--V
DD
V
= 3.6V, IN = 0V, EN = 0VFull-10-nA
DD
V
= 3.6V, IN = 3.6Full-10-nA
DD
V
= 3.6V, EN = 3.6Full-1-μA
DD
NOTES:
4. V
= Input voltage to perform proper function.
LOGIC
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parameters with limits are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range
matching between channels is calculated by subtracting the channel with the highest max r
8. r
(ON)
r
value, between HSD2 and HSD1 or between FSD2 and FSD1.
(ON)
value from the channel with lowest max
(ON)
Test Circuits and Waveforms
V
tr < 20ns
< 20ns
t
f
90%
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
VIN
VIN
V
INPUT
0V
H
50%
L
t
OFF
V
OUT
90%
t
ON
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
V
SWITCH
INPUT
INPUT
VIN
Repeat test for all switches. C
capacitance.
V
OUT
FIGURE 1B. TEST CIRCUIT
DD
EN
HSx or FSx
IN
V
=
(INPUT)
COMx
GND
includes fixture and stray
L
R
----------------------------
RLr
+
RL
45W
L
ON()
V
OUT
= 1.4V,
C
L
10pF
5
FN6408.0
January 24, 2007
Test Circuits and Waveforms (Continued)
ISL54200
V
DD
C
LOGIC
INPUT
SWITCH
OUTPUT
V
OUT
V
HSX
VIN
H
VIN
L
0V
t
D
FIGURE 2A. MEASUREMENT POINTS
V
r
= V1/I
(ON)
COMx
HSx
V
90%
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 2. BREAK-BEFORE-MAKE TIME
DD
C
INPUT
VIN
V
FSX
r
(ON)
EN
FSD1 or FSD2
HSD1 or HSD2
IN
GND
FIGURE 2B. TEST CIRCUIT
= V1/40mA
FSx
COMx
V
OUT
R
L
45Ω
V
DD
C
C
L
10pF
V
1
I
COMx
Repeat test for all switches.
FIGURE 3. HSx Switch r
COMx
GND
1.4V
TEST CIRCUIT
(ON)
EN
IN
1.4V
V
40mA
Repeat test for all switches.
FIGURE 4. FSx Switch r
1
COMx
GND
TEST CIRCUIT
(ON)
EN
1.4V
IN
0.5V
6
FN6408.0
January 24, 2007
Test Circuits and Waveforms (Continued)
V
DD
C
ISL54200
V
DD
C
IMPEDANCE
ANALYZER
Repeat test for all switches.
FIGURE 5. CAPACITANCE TEST CIRCUIT
DIN+
DIN-
OUT+
OUT-
10%
90%
10%
90%
FIGURE 7A. MEASUREMENT POINTS
HSx or FSx
COMx
t
ri
50%
50%
t
fi
t
ro
50%
50%
t
f0
90%
10%
t
skew_i
90%
t
skew_o
10%
EN
GND
IN
VINL OR
VIN
H
FIGURE 7. SKEW TEST
SIGNAL
GENERATOR
ANALYZER
IN
VIN
R
L
HSx
COMx
EN
GND
FSx
COMx
45Ω
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
V
DD
C
EN
DIN+
DIN-
VIN
15.8Ω
143Ω
15.8Ω
143Ω
VIN
COMD2
COMD1
GND
D2
D1
CL
CL
OUT+
45Ω
OUT-
45Ω
|tro-tri| Delay Due to Switch for Rising Input and Rising Output
Signals.
|tfo-tfi| Delay Due to Switch for Falling Input and Falling Output
Signals.
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 7B. TEST CIRCUIT
N.C.
7
FN6408.0
January 24, 2007
Application Block Diagram
VBUS
D-
3.3V
V
IN
ISL54200
LOGIC CIRCUITRY
COMD1
DD
ISL54200
EN
4MΩ
HSD1
HSD2
µCONTROLLER
USB
HIGH-SPEED
TRANSCEIVER
D+
USB CONNECTOR
GND
COMD2
GND
Detailed Description
The ISL54200 device is a dual single pole/double throw
(SPDT) analog switch that operates from a single DC power
supply in the range of 2.7V to 5.5V. It was designed to
function as dual 2-to-1 multiplexer to select between a USB
high-speed transceiver and a USB full-speed transceiver in
portable battery powered products. It is offered in a TDFN
package and a small µTQFN package for use in MP3
players, cameras, PDAs, cellphones, and other personal
media players. The device has an enable pin to open all
switches.
The part consist of two 7Ω full speed (FSx) switches and two
4.5Ω high speed (HSx) switches. The FSx switches can
swing from 0V to V
speed (12Mbps) differential data signals with minimal
distortion. The HSx switches have high bandwidth and low
capacitance to pass USB high-speed (480Mbps) differential
data signals with minimal edge and phase distortion.
The ISL54200 was designed for MP3 players, cameras,
cellphones, and other personal media player applications
that have both high-speed and full-speed transceivers and
need to multiplex between these USB sources to a single
USB host (computer). A typical application block diagram of
this functionality is shown above.
A detailed description of the two types of switches are
provided in the sections below.
FSx Switches (FSD1, FSD2)
The two FSx switches (FSD1, FSD2) are bidirectional
switches that can pass rail-to-rail signals. When powered
with a 3.3V supply, these switches have a nominal r
resistance of 7Ω over the signal range of 0V to 3.3V. They
. They were designed to pass USB full-
DD
(ON)
FSD1
FSD2
PORTABLE MEDIA DEVICE
USB
FULL-SPEED
TRANSCEIVER
were specifically designed to pass USB full-speed (12Mbps)
differential signals and meet the USB 2.0 full-speed signal
quality specifications. See eye diagram Figure 8.
The FSx switches can also pass USB high speed signals
(480Mbps) but do not quite meet the USB 2.0 high speed
signal quality eye diagram compliance requirement.
The maximum signal range for the FSx switches is from
-1.5V to V
exceed the V
. The signal voltage should not be allowed to
DD
voltage rail or go below ground by more
DD
than -1.5V.
When operated with a 2.7V to 3.6V supply, the FSx switches
are active (turned ON) whenever the IN logic control voltage
is
≤0.5V and the EN logic voltage ≥1.4V.
HSx Switches (HSD1, HSD2)
The two HSx switches (HSD2, HSD1) are bidirectional
switches that can pass rail-to-rail signals. When powered
with a 3.3V supply these switches have a nominal r
4.5Ω over the signal range of 0V to 400mV with a r
flatness of 0.4Ω. The r
HSD2 switches over this signal range is only 0.01Ω ensuring
minimal impact by the switches to USB high speed signal
transitions. As the signal level increases the r
resistance increases. At signal level of 3.3V the switch
resistance is nominally 20Ω.
The HSx switches were specifically designed to pass USB
2.0 high-speed (480Mbps) differential signals typically in the
range of 0V to 400mV. They have low capacitance and high
bandwidth to pass the USB high-speed signals with
minimum edge and phase distortion to meet USB 2.0 high
speed signal quality specifications. See high-speed eye
diagrams Figures 9 and 10.
matching between the HSD1 and
(ON)
(ON)
of
(ON)
(ON)
switch,
8
FN6408.0
January 24, 2007
ISL54200
The HSx switches can also pass USB full-speed signals
(12Mbps) with minimal distortion and meet all the USB
requirements for USB 2.0 full-speed signaling. See fullspeed eye diagram Figure 11.
The maximum signal range for the HSx switches is from
-1.5V to V
exceed the V
. The signal voltage should not be allow to
DD
voltage rail or go below ground by more
DD
than -1.5V.
The HSx switches are active (turned ON) whenever the IN
voltage is
≥1.4V and the EN logic voltage ≥1.4V when
operated with a 2.7V to 3.6V supply.
ISL54200 Operation
The discussion that follows will discuss using the ISL54200 in
the typical application shown in the block diagram on page 9.
POWER
The power supply connected at the VDD (pin 1) provides the
DC bias voltage required by the ISL54200 part for proper
operation. The ISL54200 can be operated with a VDD
voltage in the range of 2.7V to 5.5V. When used in a USB
application the VDD voltage should be kept in the range of
3.0V to 5.5V to ensure you get the proper signal levels for
good signal quality.
A 0.01µF or 0.1µF decoupling capacitor should be
connected from the VDD pin to ground to filter out any power
supply noise from entering the part. The capacitor should be
located as close to the VDD pin as possible.
computer. The device will be able to transmit and receive
data from the computer at a data rate of 12Mbps.
High-speed Mode
If the IN pin = Logic “1” and EN pin = Logic “1” the part will go
into high-speed mode. In high-speed mode the HSD1 and
HSD2 switches are ON and the FSD1 and FSD2 switches
are OFF (high impedance). When a USB cable from a
computer or USB hub is connected at the common USB
connector and the part is in the high-speed mode a link will
be established between the high-speed driver section of the
media player and the computer. The device will be able to
transmit and receive data fr om the computer at a data rate of
480Mbps.
All Switches OFF Mode
If the IN pin = Logic “0” or Logic “1” and EN pin = Logic “0” all
of the switches will turn OFF (high impedance).
The all OFF state can be used to switch between the two
USB sections of the media player. When disconnecting from
one USB device to the other USB device you can
momentarily put the ISL54400 switch in the “all off” state in
order to get the computer to disconnect from the one device
so it can properly connect to the other USB device when that
channel is turned ON.
LOGIC CONTROL
The state of the ISL54200 device is determined by the
voltage at the IN pin (pin 2) and the EN pin (pin 10). IN is
only active when the EN pin is logic “1” (High). Refer to“Truth
Table” on page 2.
The EN pin is internally pulled low through a 4MΩ
resistor to
ground. For logic “0” (Low) it can be driven low or allowed to
Float. The IN pin must be driven low or high and cannot be
left floating.
Logic control voltage levels:
EN = Logic “0” (Low) when V
EN = Logic “1” (High) when V
IN = Logic “0” (Low) when V
IN = Logic “1” (High) when V
≤0.5V or Floating.
EN
≥1.4V
EN
≤0.5V.
IN
≥1.4V
IN
Full-speed Mode
If the IN pin = Logic “0” and EN pin = Logic “1” the part will be
in the full-speed mode. In this mode the FSD1 and FSD2
switches are ON and the HSD1 and HSD2 switches are OFF
(high impedance). In a typical application V
will be in the
DD
range of 2.8V to 3.6V and will be connected to the battery or
LDO of the portable media device. When a computer or USB
hub is plugged into the common USB connector and the part
is in the full-speed mode a link will be established between
the full-speed driver section of the media player and the
9
FN6408.0
January 24, 2007
Typical Performance Curves T
VOLTAGE (0.5V/DIV)
ISL54200
= +25°C, Unless Otherwise Specified
A
VDD = 3.3V
TIME (10ns/DIV.)
FIGURE 8. EYE PATTERN: 12MBPS USB SIGNAL WITH FSX SWITCHES IN THE SIGNAL PATH
10
FN6408.0
January 24, 2007
ISL54200
Typical Performance Curves T
VOLTAGE (835mV/DIV)
= +25°C, Unless Otherwise Specified (Continued)
A
VDD = 3.3V
TIME (0.2ns/DIV.)
FIGURE 9. EYE PATTERN WITH FAREND MASK: 480MBPS USB SIGNAL WITH HSX SWITCHES IN THE SIGNAL PATH
11
January 24, 2007
FN6408.0
ISL54200
Typical Performance Curves T
VOLTAGE (835mV/DIV)
= +25°C, Unless Otherwise Specified (Continued)
A
VDD = 3.3V
TIME (0.2ns/DIV.)
FIGURE 10. EYE PATTERN WITH NEAREND MASK: 480MBPS USB SIGNAL WITH HSX SWITCHES IN THE SIGNAL PATH
12
January 24, 2007
FN6408.0
ISL54200
Typical Performance Curves T
VOLTAGE (0.5V/DIV)
= +25°C, Unless Otherwise Specified (Continued)
A
VDD = 3.3V
FIGURE 11. EYE PATTERN: 12MBPS USB SIGNAL WITH HSX SWITCHES IN THE SIGNAL PATH
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
SYMBOL
A0.450.500.55A1--0.05A30.127 REF-
b0.150.200.255
D2.052.102.15-
E1.551.601.65-
e0.50 BSC-
k0.20
---
L0.350.400.45-
N102
Nd43
Ne13
θ
0-12
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identi fier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
NOTESMINNOMINALMAX
4
Rev. 3 6/06
0.10 MIN
0.05 MIN
DETAIL “A” PIN 1 ID
15
2.50
1.75
L
2.00
0.275
0.50
0.25
LAND PATTERN
0.80
10
FN6408.0
January 24, 2007
ISL54200
Thin Dual Flat No-Lead Plastic Package (TDFN)
(DAT UM B )
6
INDEX
AREA
(DATUM A)
NX (b)
5
SECTION "C-C"
6
INDEX
AREA
SEATING
PLANE
NX L
8
A
C
D
TOP VIEW
SIDE VIEW
D2
D2/2
12
N
N-1
e
(Nd-1)Xe
REF .
BOTTOM VIEW
(A1)
2X
A3
E2/2
NX b
5
C
L
e
CC
FOR ODD TERMINAL/SIDE
E
87
0.10
ABC0.10
2X
0.10
//
A
NX k
E2
M
TERMINAL TIP
0.10
0.08
L1
CB
BAC
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
A
A1
A3
b
D
D2
E
C
C
E2
e
k
L
N
Nd
0.700.750.80
--0.05
0.20 REF
0.200.250.30
2.953.03.05
2.252.302.35
2.953.03.05
1.451.501.55
0.50 BSC
0.25--
0.250.300.35
10
5
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identi fier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
L
9
NOTESMINNOMINALMAX
-
-
-
5, 8
-
7, 8
-
7, 8
-
8
2
3
Rev. 3 3/06
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN6408.0
January 24, 2007
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