The Intersil ISL54200 dual 2:1 multiplexer IC is a single
supply part that can operate from a single 2.7V to 5.5V supply .
It contains two SPDT (Single Pole/Double Throw) switches
configured as a DPDT. The part was designed for switching
between USB High-Speed and USB Full-Speed sources in
portable battery powered products.
The 7
Ω normally-closed (NC) FSx switches can swing rail to
rail and were specifically designed to pass USB full speed
data signals (12Mbps) that range from 0V to 3.6V. The 4.5
normally-open (NO) HSx switches have high bandwidth and
low capacitance and were specifically designed to pass USB
high speed data signals (480Mbps) with minimal di stortion.
The part can be used in Personal Media Players and other
portable battery powered devices that need to switch between
a high-speed transceiver and a full-speed transceiver while
connected to a single USB host (computer).
The digital logic inputs are 1.8V logic compatible when
operated with a 2.7V to 3.6V supply. The part has an enable
pin to open all switches. It can be used to facilitate pro per bus
disconnect and connection when switching between the USB
sources.
The ISL54200 is available in a 10 Ld 3mmx3mm TDFN and a
small 10 Ld 2.1mmx1.6mm µTQFN packages. It operates
over a temperature range of -40 to +85°C.
Ω
FN6408.0
Features
• High Speed (480Mbps) and Full Speed (12Mbps)
Signaling Capability per USB 2.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
Pinouts
ISL54200
(10 LD TDFN
TOP VIEW
VDD
COMD1
COMD2
GND
1
IN
2
3
4
5
LOGIC
CONTROL
4M
EN
10
9
HSD1
8
HSD2
7
FSD1
6
FSD2
NOTE:
1. ISL54200 Switches Shown for IN = Logic “0” and EN = Logic “1”.
Ordering Information
ISL54200
VDD
COMD1
COMD2
ISL54200
(10 LD µTQFN)
TOP VIEW
EN
10
4M
HSD1
1
IN
2
3
4
LOGIC
CONTROL
5
GND
9
HSD2
8
FSD1
7
FSD2
6
PART NUMBER
(Note)
PART
MARKINGTEMP. RANGE (°C)PACKAGE (Pb-Free)PKG. DWG. #
ISL54200IRZ200Z-40 to +8510 Ld 3x3 TDFN L10.3x3A
ISL54200IRZ-T200Z-40 to +8510 Ld 3x3 TDFN Tape and ReelL10.3x3A
ISL54200IRUZ-TFM-40 to +8510 Ld 2.1x1.6mm μTQFN Tape and ReelL10.2.1x1.6A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Truth Table
ISL54200
ENINFSD1, FSD2HSD1, HSD2
10ONOFF
11OFFON
0XOFFOFF
Logic “0” when ≤0.5V, Logic “1” when ≥1.4V with a 2.7V to 3.6V
Supply. X = Don’t Care
Pin Descriptions
ISL54200
PIN NO.NAMEFUNCTION
1VDDPower Supply
2INSelect Logic Control Input
3COMD1USB Common Port
4COMD2USB Common Port
5GNDGround Connection
6FSD1Full Speed USB Differential Port
7FSD2Full Speed USB Differential Port
8HSD1High Speed USB Differential Port
9HSD2High Speed USB Differential Port
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on FSD1, FSD2, HSD1, HSD2, COMD1, COMD2, EN, IN exceeding V
maximum current ratings.
3. θ
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
OFF IsolationV
FSx Switch -3dB BandwidthSignal = -10dBm, 1.0VDC offset, R
HSx Switch -3dB BandwidthSignal = -10dBm, 0.2VDC offset, R
HSx OFF Capacitance, C
Input Voltage Low, V
Input Voltage High, V
Input Current, I
Input Current, I
Input Current, I
INL, IENL
INH
ENH
INL
INH
, V
, V
ENL
ENH
V
= 2.7V to 3.6VFull--0.5V
DD
V
= 2.7V to 3.6VFull1.4--V
DD
V
= 3.6V, IN = 0V, EN = 0VFull-10-nA
DD
V
= 3.6V, IN = 3.6Full-10-nA
DD
V
= 3.6V, EN = 3.6Full-1-μA
DD
NOTES:
4. V
= Input voltage to perform proper function.
LOGIC
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parameters with limits are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range
matching between channels is calculated by subtracting the channel with the highest max r
8. r
(ON)
r
value, between HSD2 and HSD1 or between FSD2 and FSD1.
(ON)
value from the channel with lowest max
(ON)
Test Circuits and Waveforms
V
tr < 20ns
< 20ns
t
f
90%
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
VIN
VIN
V
INPUT
0V
H
50%
L
t
OFF
V
OUT
90%
t
ON
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
V
SWITCH
INPUT
INPUT
VIN
Repeat test for all switches. C
capacitance.
V
OUT
FIGURE 1B. TEST CIRCUIT
DD
EN
HSx or FSx
IN
V
=
(INPUT)
COMx
GND
includes fixture and stray
L
R
----------------------------
RLr
+
RL
45W
L
ON()
V
OUT
= 1.4V,
C
L
10pF
5
FN6408.0
January 24, 2007
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