intersil ISL5416 DATA SHEET

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ISL5416

Data Sheet August 2004

Four-Channel Wideband Programmable DownConverter

The ISL5416 Four-Channel Wideband Programmable Digital DownConverter (WPDC) is designed for high dynamic range applications such as cellular basestations where the processing of multiple channels is required in a small physical space. The WPDC combines four channels in a single package, each including: an NCO, a digital mixer, digital filters, an AGC and a resampling filter.

All channels are independently programmable and may be updated in real time. Each of the four channels can select any of the four digital input buses. Each of the tuners can process a W-CDMA channel. Channels may be cascaded or polyphased for increased bandwidth. Selectable outputs include I samples, Q samples, and AGC gain. Outputs from the part are available over the parallel, serial or uP interfaces.

Ordering Information

PART

NUMBER

ISL5416KI -40 to 85 256 BGA V256.17x17

ISL5416KIZ

(See Note)

ISL5416EVAL1 25 EVALUATION KIT

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.

TEMP

RANGE (

-40 to 85 256 BGA

C) PACKAGE PKG. DWG. #

(Pb-free)

V256.17x17

FN6006.3

Features

• Up to 95MSPS Input

• Four Parallel 16-bit Fixed or 17-bit Floating Point Inputs

• Programmable RF Attenuator/VGA Control

• 32-Bit Programmable Carrier NCO with > 110dB SFDR

• 20-bit Internal Data Path

• Filter Functions

- Multi-Stage Cascaded-Integrator-Comb (CIC) Filter

- Two programmable FIR Filters (first up to 32-taps, second up to 64-taps)

- Half Band Interpolation Filter

- Resampling FIR Filter

• Overall decimation from 1 to >4096

• Digital AGC with up to 96dB of Gain Range

• Up to Four Independent 16-bit Parallel Outputs

• Serial Output Option

• 16-bit Pa rallel µP Interface

• 1.8V core, 3.3V I/O Operation

• Evaluation Board and Configuration Software available

• Pb-free available

Applications

• Basestation Receivers: GSM/EDGE, CDMA2000, UMTS.

Block Diagram

TEST

AIN(16:0)

ENIA

CLKA

EOUT(15:0)

RESET

INPUT SELECT CLOCK & FORMAT

RANGE CONTROL

INPUT A CHANNEL O

INPUT B

INPUT C

INPUT D

RF ATTENUATOR

VGA CONTROL

INPUT CHANNEL ROUTING

JTAG SYNCHRONIZATION

NCO

MIXER

CIC

SYNCO SYNCIN1 SYNCIN2

1-888-INTERSIL or 321-724-7143

FIR1

FILTER

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

FILTER

FIR2

AGC

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

OUTPUT

AOUT(15:8)

or RD

RD/WR

DSTRB

WR or

P(15:0)

IHBF

µP INTERFACE

RESAMPLER

CHANNEL 1

CHANNEL 2

CHANNEL 3

ADD(2:0)

uP MODE

OUTPUT ROUTING & FORMATTING

AOUT(7:0) FSYNCA

OEA

CLKO1 CLKO2

/INTRPT

TYPICAL CHANNEL

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FILTER CASCADE

GAIN

ROUND

x1, 2, 4, 8

DIGITAL TUNER

OUTPUT

FIR

1-64 TAPS

R=1-8

BYPASS

SATURATE

CHANNEL 0

AGC

OUTPUT FORMAT

24 24

0 - 96 dB

BYPASS

/ /

N D

CASCADE

AIN(16:0) BIN(16:0) CIN(16:0) DIN(16:0)

TEST INPUT

DIGITAL

TUNING

MIXER

MUX

NCO

32-BIT CONTROL

>110 db SFDR

INPUT A

AIN(16:0)

ENIA

CLKA

INPUT

FORMAT

RANGE

CONTROL

INPUTS

CIC

FILTER

1-5 STAGES

R=2-64K BYPASS

MUX

TEST

GAIN

FIR

1-32 TAPS

R=1-8

BYPASS

ROUND

x1, 2, 4, 8

SATURATE

CASCADE IN

MUX

F O

IHBF

/ /

RESAMPLING

FILTER

SLOT CONTROL CH 0, 1 MUXING

TO PARALLEL

SEQUENCING

AND ROUTING

MUX

SELECT

FORMAT

TO SERIAL

TO uP

ROUTING

INTERFACE

AOUT(15:0) FSYNCA

OEA

EXT AGC CNTRL

BIN(16:0)

ENIB

CLKB

INPUT B

INPUT

FORMAT

RANGE

CONTROL

CASCADE OUT

MUX

DIGITAL TUNER

CHANNEL 1

AGC GAIN

OUTPUT FORMAT

MUX

SLOT CONTROL CH 0, 1 MUXING

ISL5416

BOUT(15:0) FSYNCB

OEB

CHANNEL 2

INPUT C

CIN(16:0)

ENIC

CLKC

INPUT

FORMAT

RANGE

CONTROL

MUX

DIGITAL TUNER

OUTPUT FORMAT

SLOT CONTROL CH 2, 3 MUXING

O U T P U T M U L T I P L E X I N G

COUT(15:0) FSYNCC

OEC

INPUT D

DIN(16:0)

ENID

CLKD

INPUT

FORMAT

RANGE

CONTROL

MUX

DIGITAL TUNER

MUX

EOUT(15:0)

TRST

RESET

TMS TCLK TDI TDO

JTAG

SYNCHRONIZATION

SYNCO

SYNCIN1

CHANNEL 3

AGC GAIN

SYNCIN2

OUTPUT FORMAT

SEQUENCED uP READ DATA

uP INTERFACE

SLOT CONTROL CH 2, 3 MUXING

SERIAL OUTPUTS

P(15:0), uPMODE, RD (RD/WR),

(DSTRB), CE, ADD(2:0)

DOUT(15:0) FSYNCD

OED CLKO1 CLKO2/

INTRPT

ISL5416

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256-LEAD BGA

TOP VIEW

123456789 1110

Ain9

Ain8

Ain7

Ain6 Bout9

Ain5 Bout7Ain4

Ain3 Bout4 VccIORESET

Ain2 Bout3Ain1

CLKC

GND Dout15Cin16

Cin14 Dout14Cin15

Cin12

Cin10

Ain10 Ain11 Ain12 Ain14 Eout13

Bin9

Bin10

Bin8

ENIB

Bin7

Bin6 Bout8Bout14

Bin4

Vcc

Bin1 TMS TDI Aout3

Ain0

VccIO

Cin13

Cin11 Din10 Din11 Din4 Din3 Vcc

CLKD Eout6 Eout7 GND GND

Din16 P4

Eout3 Dout13Vcc

Din12 Din13 GND GND WR

Vcc Ain15Vcc

GND

Bin5 Eout10 Bin13 Eout11 Vcc P13 P11 TDO Aout6

Bin3

Bin2

Bin0

Eout4

Din15 Din14 GND Add1 GND

Bin14 Bin15 Eout14 P12

GND GND GND uPmode GND P10

Eout8 Eout9

Vcc

Eout5 Eout2 P3

Ain16

CLKB

Eout12

TRST Add2 P2

Din0

Eout1

SYNCO Aout15SYNCIn1CLKA Aout14 Aout13 GNDENIA

SYNCIn2GNDEout15 Bout13

P15

VccIO OEB

P14

Dout0

Dout2 VccDout1Cin9

OEA

Bout15

GND

P0 Dout3Vcc

P1 OED

Vcc

VccIO FSYNCBBin11 Bin12 Ain13 Bin16

Bout5

GND

Add0 Dout11 Dout12

Dout4

Dout5 Dout6 Dout7Din9 Vcc Din6 ENID Din2 Din1

Bout12

VccIO

Bout6GND

Bout1 Bout2

P6P5

Bout0

CLKO2/ INTRPT

GND VccIO

15 16

Aout12 Aout11

Bout11

FSYNCA

Aout10

Bout10

Aout8

Aout4 Aout5

Aout1 Aout2

CLKO1 Cout15

Cout14

Cout12 Cout11

Dout10 Cout10

Dout9

VccIO

Aout9

Aout7

Vcc

Aout0

Cout13

GND

POWER PIN

GROUND PIN

Vcc = +1.8V CORE SUPPLY VOLTAGE

VccIO = +3.3V I/O SUPPLY VOLTAGE

NOTE: Thermal Balls should be connected to the ground plane

Unused Input Balls should be connected to ground or V

SIGNAL PIN

THERMAL BALL

Eout0

IO as appropriate

Cin0

NC (NO CONNECTION)

Cout2 OECCout0

TCLK Cout3Cout1Cin8

Cout4Din8 Din7 Din5 ENIC Cin2 CE

Cout5 Cout6 FSYNCCCin7 Cin6 Cin5 Cin4 Cin3 Cin1

VccIO FSYNCD

Dout8 Cout9

Cout7

Cout8

ISL5416

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Pin Descriptions

INTERNAL

NAME TYPE

POWER SUPPLY

Vcc - Positive Power Supply Voltage (core), 1.8V ±0.09

VccIO - Positive Power Supply Voltage (I/O), 3.3V ±0.165

GND - Ground, 0V.

INPUTS

PULL-UP/DOWN DESCRIPTION

Ain(16:0) I PULL DOWN Parallel Data Input bus A. Sampled on the rising or falling edge (programmable) of clock when ENIA

Bin(16:0) I PULL DOWN Parallel Data Input bus B. Sampled on the rising or falling edge (programmable) of clock when ENIB

Cin(16:0) I PULL DOWN Parallel Data Input bus C. Sampled on the rising or falling edge (programmable) of cloc k when ENIC

Din(16:0) I PULL DOWN Parallel Data Input bus D . Sampled on the rising or falling edge (prog r ammab le) of cloc k when ENID

ENIA

ENIB

ENIC

ENID

CONTROL

CLKA I PULL DOWN Input clock for data bus A. CLKA or CLKC may be used for Ain(16:0).

I PULL DOWN Input enable for Parallel Data Input bus A. Active low. This pin enables the input to the part in one of

I PULL DOWN Input enable for Parallel Data Input bus B. Active low. This pin enables the input to the part in one of

I PULL DOWN Input enable for Parallel Data Input bus C. Active low. This pin enables the input to the part in one of

I PULL DOWN Input enable for Parallel Data Input bus D. Active low. This pin enables the input to the part in one of

is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).

two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx asserted.

CLKB I PULL DOWN Input clock for data bus B. CLKB or CLKC may be used for Bin(16:0). CLKC I Input clock for data bus C. CLKC is also the master clock for all channels of ISL5416 CLKD I PULL DOWN Input clock for data bus D. CLKD or CLKC may be used for Din(16:0).

SYNCIn1 I PULL DOWN Global synchronization input signal 1. SYNCIn1 can update the carrier NCOs, reset decimation

counters, restart the filter, and restart the output section among other funct ions. For most of the functional blocks, the response to SYNCIn1 is programmable and can be enabled or disabled.

SYNCIn2 I PULL DOWN Global synchronization input signal 2. SYNCIn2 can update the carrier NCOs, reset decimation

counters, restart the filter, and restart the output section among other funct ions. For most of the functional blocks, the response to SYNCIn2 is programmable and can be enabled or disabled.

SYNCO O Synchronization Output Signal. The processing of multiple ISL5416 devices can be synchronized by

RESET

I PULL UP Reset Signal. Active low. Asser ting reset will halt all processing and set cer tain registers to default

tying the SYNCO from one ISL5416 device (the master) to the SYNCIn of all the ISL5416 devices (the master and slaves). An optional internal SYNCO to SYNCInX connection is provided.

values.

Pin Descriptions (Continued)

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ISL5416

NAME TYPE

JTAG

TDO O Test data out

TDI I PULL UP Test data in.

TMS I PULL UP Test mode select. TCLK I PULL DOWN Test clock. TRST

OUTPUTS

Aout(15:0) O Parallel Data Output bus A. A 16-bit parallel data output which can be programmed to consist of I, Q,

Bout(15:0) O Parallel Data Output bus B. A 16-bit parallel data output which can be programmed to consist of I, Q,

I PULL UP Test reset. Active low. If JTAG not used, tie this pin low. If there is a trace connected to the pin and

INTERNAL

PULL-UP/DOWN DESCRIPTION

there is enough board noise, the JTAG port might get into an unexpected state and stop communications with the part

AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus. Information can be sequenced in a programmable order. Can be ones complemented. Can be divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface

Section. See Table 24.

Cout(15:0) O Parallel Data Output bus C . A 16-bit parallel data output which can be programmed to consist of I, Q,

Section.

Dout(15:0) O Parallel Data Output bus D. A 16-bit parallel data output which can be programmed to consist of I, Q,

SERIAL OUTPUT BITS ALLOCATION

SER. OUTPUT A SER. OUTPUT B SER. OUTPUT C SER. OUTPUT D

SCLKX * DOUT0 DOUT4 DOUT8 DOUT12

SSYNCX * DOUT1 DOUT5 DOUT9 DOUT13

SD1X * DOUT2 DOUT6 DOUT10 DOUT14 SD2X * DOUT3 DOUT7 DOUT11 DOUT15

X denotes A, B, C, D as appropriate

Eout(15:0) O A 16-bit parallel VGA/Attenuator control output. Partitionable into separate 4 or 8-bit busses.

CLKO1 O Output Clock 1. Can be programmed to be at CLKC/N for N = 1 to 16. The polarity of CLKO1 is

programmable.

CLKO2/ INTRPT

O Available ONLY on Rev B (final) version of the part. Provides a complementary output or a second

clock to simplify board routing. Polarity is programmable. It can also be programmed as an interrupt from one or more channels for a sequenced read (FIFO-like) mode. See register GWA = 0000h, bit

13.

Pin Descriptions (Continued)

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ISL5416

NAME TYPE

FSYNCA O Frame Synchronization output signal for bus Aout(15:0). FSYNCB O Frame Synchronization output signal for bus Bout(15:0). FSYNCC O Frame Synchronization output signal for bus Cout(15:0). FSYNCD O Frame Synchronization output signal for bus Dout(15:0).

OEA

OEB

OEC

OED

MICROPROCESSOR INTERFACE

P(15:0) I/O Microprocessor Interface Data bus. See Microprocessor Interface Section. P15 is the MSB.

ADD(2:0) I Microprocessor Interface Address bus. ADD2 is the MSB. See Microprocessor Interface Section.

DSTRB

I PULL UP Output three-state enable for Parallel Data Output bus A. Active low. I PULL UP Output three-state enable for Parallel Data Output bus B. Active low. I PULL UP Output three-state enable for Parallel Data Output bus C. Active low. I PULL UP Output three-state enable for Parallel Data Output bus D. Active low.

I Microprocessor Interface Write or Data Strobe Signal. When the Microprocessor Interface Mode

INTERNAL

PULL-UP/DOWN DESCRIPTION

Control (µP MODE) is low, data transf ers (from P(15:0) to the internal write holding register) occur on the low to high transition of WR input functions as a data strobe DSTRB P(15:0) to the internal write holding register) occur on the low to high transition of DSTR B

high the data from the address specified is placed on P(15:0) when DSTRB is low. See the

RD/WR Microprocessor Interface Section.

when CE is asserted (low). When the µP MODE control is high this

control. In this mode with RD/WR low, data transfers (from

. With

RD/WR

µP MODE I PULL DOWN Microprocessor Interface Mode Control. This pin is used to select the Read/Write mode for the

I Microprocessor Interfa ce Read or Read/Write Signal. When the Microprocessor Interface Mode

I Microprocessor Interface Chip Select. Active low. This pin has the same timing requirements as the

Control (µP MODE) is low, the data from the address specified is placed on P(15:0) when RD asserted (low) and CE a Read/Write appropriate register when low. See the Microprocessor Interface Section.

Microprocessor Interface. When 0, RD is 0, the microprocessor interface consists of separate RD interface consists of a RD/WR Section.

address pins.

control input. Data is read from P(15:0) when RD/WR high or written to the

is asserted (low). When the µP MODE control is high this input functions as

and WR, when 1, DSTROBE and RD/WR. When µP MODE

and WR strobes; when µP MODE is 1, the

control and a single data strobe. See the Microprocessor Interface

ISL5416

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Functional Description

The ISL5416 is a four channel digital receiver integrated circuit offering exceptional dynamic range and flexibility. Each of the four channels consists of a front-end NCO, digital mixer, CIC-filter, two FIR filters, AGC, Interpolation Half Band Filter and Re-sampling Filter. The parameters for the four channels are independently programmable.

There are four 17-bit parallel data input busses (Ain(16:0), Bin(16:0), Cin(16:0) and Din(16:0)). The ISL5416 supports both fixed and floating point parallel data input modes. The floating point modes support gain ranging A/D converters or A/D converter and RF/IF Attenuators or VGAs. Gated or interpolated data input modes are supported. Each input can be connected to any or all of the internal signal processing channels, Channels 0, 1, 2 and 3. The four channels share a common processing clock (CLKC). Four input clocks are provided to allow for clock skew between input sources. Each input has a Range Control circuits to monitor the signal level on the parallel data busses and to control the gain prior to the A/D converters. A 16-bit bus (Eout(15:0)) is provided to control the external VGA/RF Attenuators.

Each front end NCO/digital mixer/CIC filter section incl udes a quadrature numerically controlled oscillator (NCO), digital mixer , barrel shifter and a casca ded-integ r ator-comb filter (CIC). The NCO has a 32-bit frequency control word. The SFDR of the NCO is >110dB. The barrel shifter provides a gain of between 2 CIC. The CIC filter order is programmable from 1 to 5 and the CIC decimation factor can be programmed from 2 to 512 for

order, 2048 for 4th order, 32768 for 3rd order, or 65536 for

or 2nd order filters. The CIC filter can also be bypassed.

Each channel back end section includes two FIR filters, an AGC, Interpolation Half Band Filter and Resampler. The first FIR filter can have up to 32 taps and the second can have up to 64 taps. The 32-tap filte r calculates 4 taps per clock, while the 64-tap filter calculates 8 taps per clock. The coefficients for the programmable digital filters are 20 bits wide. Each FIR filter can be bypassed. The AGC section can provide up to 96dB of either fixed or automatic gain control. For automatic gain control, two settling modes and two sets of loop gains are provided. Separate attack and decay slew rates are provided for each loop gain. Programmable limits allow the user to specify a gain range less than 96dB.

A fixed coefficient interpolate-by-2 Half Band Filter and a non-integer resampling filter follow the AGC. Coefficients for the resampling filter are provided in ROM.

Four 16-bit parallel data outputs (Aout(15:0), Bout(15:0), Cout(15:0) and Dout(15:0)) are provided. The output of each channel can be routed to any of the output buses. Outputs from more than one channel can be multiplexed through a common output if the channels are synchronized. Dout(15:0)) can alternately be used as four serial output pairs. A common output clock (CLKO1) is used for the

-45

and 4 to compensate for the gain in the

parallel output buses. A second clock output pin (CLKO2/INTRPT allow a complementary output clocks.

The ISL5416 is programmed through a 16-bit microprocessor interface. The output data can also be read via the microprocessor interface. The ISL5416 is specified to operate to a maximum clock rate of 95 MSPS over the industrial temperature range (-40 supply voltage range is 3.3V ± 0.165V while the core power supply voltage is 1.8V ± 0.09V.

) is provided to simplify board routing or to

C to 85oC). The I/O power

Input Select/Format Block

CLOCKING

The channel processing and output timing is clocked with the rising edge of CLKC. Each input bus can be cloc ked with the rising or falling edge of its o wn cloc k or with the rising or f alling edge of CLKC. The frequency of all the cloc ks m ust be the same, but providing separate clocks allows the inputs from multiple A/D converters to have a small amount of ske w.

INPUT FORMAT

The inputs can be fixed point or floating point with mantissa/exponents sizes of 14/3, 15/2, or 16/1. The exponent inputs are added to the exponent from the internal range control circuits, so if the range control circuits are used, the exponent pins are typically grounded and/or disabled via software in IWA = 0*10h, bit 3. The input format may be twos complement or offset binary format in either fixed or floating point modes (IWA = 0*00h).

GATED/INTERPOLATED MODES

For input sample rates at sub-multiples of the clock rate, gated and interpolated input modes are provided. Each input channel has an input enable (ENIx gated mode, one input sample is processed per clock that the ENIx when ENIx part to minimize delay (latency). In the interpolated mode, the input is zeroed when the ENIx processing inside the part continues. This mode inserts zeros between the data samples, interpolating the input data stream up to the clock rate. The spacing between ENIx signals must be constant in the interpolated mode.

MULTIPLEXED INPUT MODE

Each input section can select one channel from a multiplexed data stream of up to 8 channels. The input enable is delay ed by 0 to 7 cloc k cycles to enab le a selection register. The register following the selection register is enabled by the non-delayed input enable to realign the processing of the channels. The one-clock-wide input enable must align with the data for the first channel. The desired channel is then selected by programming the delay. A delay of zero selects the first channel, a delay of 1 selects the second, etc. Each input section selects only one channel of the multiplexed stream, so a separate input bus must be used for each channel of the multiplexed data stream.

signal is asserted (low). Processing is disabled

is high. The ENIx signal is pipelined through the

, x = A, B, C or D). In the

signal is high, but

CLKC

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CLKX

CLKC

CLKX

ISL5416

R1 R2 R3 R4

INTERPOLATE

BUS REVERSE

ENIX

XIN(16:0)

R E G

CLK/CLK

CLKX/CLKC

CLKX

CLKC

NOTE: To simplify the board routing, each of the four input data busses can be reversed, MSB for LSB (see IWA = 0*00h, bit 4)

M U X

R E G

M U X

R3 R4

(16:0)

(0:16)

FIGURE 1. INPUT SECTION

OBIN

F M T

FLOAT/FIX

SLOT#

M A P

U X

MANTISSA EXPONENT

DIN (ONLY)

PROCESSING ENABLE

TO CHANNELS AND RANGE CONTROL

TO SE RIAL FREQUENCY OFFSET

CLK

SYNCInX Use

SYNCInX main purpose is as a processing start-up signal after a reset to align the start of processing of multiple channels or chips. This assures that the carrier phases have a known relationship and that the output timing aligns for multiplexing outputs. It can also be used after start-up as a system timing synchronization signal. Two SYNCInX signals are provided so that one can be used as a regularly occurring signal (such as at time slot boundaries) and one as an infrequent signal (such as at start up or at 1 pps). If more than one air interface standard is processing in one part, one SYNCInX signal could be used for the slot timing for each standard.

Register updates from a processor write are synchronized to the clock, so that the register updates in multiple channels of the same part are time aligned. However, when synchronizing multiple parts the processor will need knowledge of the SYNCInX timing so that enabling the SYNCInX in multiple parts occurs between SYNCInX pulses. Alternatively, SYNCIn1 could be used as a regularly occurring SYNCI signal and SYNCIn2 could be a gated version. The channel processing control register might only be updated on SYNCIn2 and the other SYNCI functions would respond to SYNCIn1.

ISL5416

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VGA/RF Attenuator (A/D Range Control)

The range control section monitors the output of the A/D and adjusts the RF/IF gain to maintain a desired A/D output range. The gain adjustments are in 6 dB steps. The levels, adjustment rates, and gain to bit mapping are programmable.

The range control section uses three programmable thresholds. Two thresholds, an upper and a lower threshold, are compared against the average magnitude of the A/D output. The range control adjusts the gain to keep the average A/D output between the upper and lower thresholds. If the average is above the upper threshol d, an internal attenuator control register is increased by a programmable amount. If the average is below the lower threshold, the gain attenuator control register is decreased by a separate programmed amount. The number of samples averaged for each decision is programmable. The adjustments to the attenuator control register can be less than 6 dB to further filter the inputs. Only the three MSBs of the attenuator control register are used to control the RF/IF gain, and these are weighted as 6, 12, 24 dB steps.

The third threshold, an immediate threshold, is compared against the magnitude of each A/D sample. If the magnitude of any A/D sample exceeds the threshold, the attenuator control register is immediately increased by the amount programmed for the immediate threshold. Because there will be some time delay from a regist er chan ge unt il the ef fect of the change is seen at the A/D, the immediate threshold is disabled for a programmable number of clock cycles after it has been triggered.

To maximize the input sensitivity the range control also includes a programmable bias. If the average signal is between the upper and lower threshold, the bias value is

added from the attenuator control register. This bias removes attenuation when it is no longer needed to avoid missing small signals due to high input noise figure.

Four counters control the amount of time that the input is averaged and align the adjustments to time slot boundaries. One counts out the time slot period. If desired, this counter can be reset by a SYNCInX signal to align its count to the system timing. A second counter provides a programmable delay from the start of the first counter's period to the start of the integration period. This compensates for system delays or allows the adjustments to be made over a certain portion of the time slot. The third counter sets the integration period for averaging the input samples for the upper and lower threshold decisions. The fourth counter controls the number of integration periods per time slot. See Figure 2 for a block diagram. Note that the counters are ignored for the immediate threshold decisions.

The user can program a separate code for output on the EOUT bus for each of the eight possible states of the three MSBs of the attenuator control register. These codes can be up to 8 bits, but if four gain control sections are used, only four bits are available for each gain control section. The mapping of the gain control bits to EOUT bits is done in GWA = 0001h and the codes are programmed in IWA = 0*17h and 0*18h.

The three MSBs of the attenuator control register can be routed internally to the channels to be used as the floatingpoint exponents. This adds gain in 6 dB steps to compensate for the 6 dB steps of RF attenuator. The MSBs can be added to the input exponent bits if desired. There is a programmable delay from the attenuator control register to the channel input to compensate for RF/IF filter group delay and A/D and ISL5416 pipeline delays.

ISL5416

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SYNC

INTERVAL (SLOT

PERIOD)

DELAY

(SYNC TO START OF INTEGRATION)

INTEGRATION TIME

INTEGRATIONS PER SLOT - 1

DOWN COUNTER

≥0 =0

<0 =0

≥0

ENABLE COUNTERS

ENABLE UPDATES

TH1

FROM INPUT SECTION

MANTISSA

|X|

BYPASS

BW SELECT

REG

DUMP

(-1 TO -16)

TH2

∆

HPF

|X|

REG

BARREL

SHIFT

TH3

∆

EXPONENT

EN INPUT EXP

EN ATTEN EXP

1-256 CLOCKS

PROG

DELAY

CIC SHIFT VALUE

OFFSET TO BASE

EOUT

A<B LOWER

LIMIT

DETECTOR

MUX

R E G

LUT

PRLD(7:0)

DOWN

COUNTER

µP ENABLE

“0” BIAS DELTA1 DELTA2 DELTA3

A>B IMMEDIATE

MUX

REG

DECODE

A>B

UPPER

R E

MAP

8 8 8

FROM OTHER DETECT.

UPPER GAIN LIMIT

LOWER GAIN LIMIT

LUT = LOOK UP TABLE

FIGURE 2. RANGE CONTROL BLOCK DIAGRAM

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NCO/Mixer

After the input select/format section, the samples are multiplied by quadrature sine wave samples from the carrier NCO. The NCO has a 32-bit frequency control, providing sub-hertz resolution at the maximum clock rate. The quadrature sinusoids have exceptional purity. The purity of the NCO should not be the determining factor for the receiver dynamic range performance (A typical spectrum plot is shown in Figure 20). The phase quantization to the sine/cosine generator is 24 bits and the amplitude quantization is 19 bits.

ENA ENB

ENC END

ENµP

EXPA EXPB

EXPC EXPD

EXPµP

MUX

E G

MAX EXP

R E

BASE SHIFT

C L I P

R E

VALUE (from uP)

R E G

The carrier NCO center frequency is loaded via the uP bus. The center frequency control is double buffered -- the input is loaded into a holding register via the uP interface. The data is then transferred from the holding register to the active register by a write to a special address or by a SYNCInX signal, if enabled in IWA = *000h. To synchronize multiple channels, the carrier NCO phase accumulator feedback can be zeroed on loading to restart all of the NCOs at the same phase (see IWA = *005h). The phase of the NCO can be offset by programming IWA = *003h. The phase offset is not double buffered.

DECIMATION

COUNTER

0...-23

R E G

MUX

R E G

MANT

BMANT CMANT DMANT

PMANT

(TEST INPUT)

ENCOF

COF

COFSYNC

MUX

SERIAL

FREQ

OFFSET

0...-15 0...-23

E G

REG REG

SIN/COS

GEN REG

REG

0...-18

0...-23

-45

TO 2

FIXED INPUT GAIN = 2

SHIFT GAIN = 2

R E G

REG

INTEGRATE

REG

INTEGRATE

REG

INTEGRATE

BARREL SHIFTER

69b

53b

62b

34b

44b

CIC ORDER FIR COEFFICIENTS

11-1 21-21

REG

0...-29 FIR

FILTER (COMB)

0...-23

31-33-1

REG

41-46-41 5 1 -5 10 -10 5 -1

CENTER FREQ

PHASE OFFSET

NOTE: BUS NUMBERING SUCH AS 0...-23 INDICATES BIT WEIGHTS SUCH AS 2

... 2

-23

FIGURE 3. NCO, MIXER AND CIC BLOCK DIAGRAM

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TABLE 1. PN GENERATOR BIT WEIGHTING

SIGNAL 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23

PN SSSXXXXXXXXXXXXXXXX

GAIN REG XXXXXXXXXXXXXXXX

PN Generator

After the mixers, a PN (pseudonoise) signal can be added to the data. This feature is provided for test and to digitally reduce the input sensitivity and adjust the receiver range (sensitivity). The effect is the same as increasing the noise figure of the receiver, reducing its sensitivity and overall dynamic range. The one bit PN data is scaled by a 16 bit programmable scale factor. The overall range fo r the PN is 0 to 1/4 full scale. A gain of 0 disables the PN input. The bit weighting for the gain is shown in table 1.

The minimum, non-zero, PN value is 1/2 dBFS) on each axis (-105 dbFS total).

of full scale (-108

CIC Filter

Next, the signal is filtered by a cascaded integrator/comb (CIC) filter. A CIC filter is an efficient architecture for decimation filtering. The power or magnitude squared frequency response of the CIC filter is given by:

 

------------------------

Pf()

 

sin



where

M = Number of delays (1 for the ISL5416)

N = Number of stages

and R = Decimation factor.

The passband frequency response for 1 (N=5) order CIC filters is plotted in Figure 20. The frequency axis is normalized to f sample rate. Figure 19B shows the frequency response for a

order filter but extends the frequency axis to fS/R = 3 (3 times the CIC output sample rate) to show alias rejection for the out-of-band signals. Figure 19A provides the amplitude of the first (strongest) alias as a function of the signal frequency or bandwidth from DC. For exa mp le, with a 5 order CIC and f output rate) Figure 19A shows a first alias level of about -87 dB. Figure 19A is also listed in table form in Table 84.

The CIC filter order is programmable from 0 to 5. The CIC may be bypassed by setting the CIC IWA = *001h bit 15.

A barrel shifter precedes the CIC filter to compensate for the large gain range of the CIC. As the barrel shifter only adjusts in 6 dB steps the total CIC/barrel shifter gain ranges from 0.5 to 1.0.

πMf()sin

πf



---- -



(N=1) though 5th

/R, making fS/R = 1 the CIC output

/R = 0.125 (signal frequency is 1/8 the CIC

The barrel shifter is also used to convert floating point input data to fixed point for processing. The exponent bits from the input and/or range control are added to the shift code programmed by the user to expand the input range. The shift code that the user programs must take the expected exponent range into account i.e. the computed shift control must be reduced by the maximum exponent value. Also note that since the exponent shifting reduces the effective size of the integrators, the maximum decimation factor is reduced (See Tables 2-4).

The integrator bit widths are 69, 62, 53, 44, and 34 for the 1 through 5 are all 24. The integrators are sized for decimation f actors of up to 512 with 5 stages, 2048 with 4 stages, 32768 with 3 stages, and 65536 with 1 or 2 stages. Higher decimations in the CIC should be avoided as they will cause integrator overflow. In the ISL5416, the integrators are slightly oversized to reduce the quantization noise at each stage.

A CIC filter has a gain of R and N is the number of stages. Because the CIC filter gain can become very large with decimation, an attenuator is provided ahead of the CIC to prev ent overflow. The 24 bits of mixer output are placed on the low 24 bits of a 69 bit bus (width of the first CIC integrator) for a gain of 2 barrel shifter then provides a gain of 2 passing the data onto the CIC. The ov er all gain in the pre-C IC attenuator can therefore be programmed to be an y one of 48 values from 2 This shift factor is adjusted to keep the total barrel shifter and CIC filter between 0.5 and 1.0. The equation which should be used to compute the necessary shift factor is:

BASE SHIFT = MAX(0, 45 - CEIL( LOG2( R MAXEXP = sum of the maximum exponent range from a

floating point input and the range control. CIC barrel shifts of greater than 45 will cause MSB bits to be

lost. Most of the floating point modes on the ISL5416 make use of the CIC barrel shifter for gain. This limits the maximum usable decimation. See floating point input mode section for details.

If the CIC is bypassed, BASE SHIFT = 45 - MAXEXP. MAXEXP = sum of the maximum exponent range from a

floating point input and the range control.

stages, respectively, while the comb bit widths

, where R is the decimation factor

-45

to 247 inclusive before

-45

to 4, inclusive (see IW A = *005 h, bits 25:20).

. A 48 bit

) ) - MAXEXP)

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TABLE 2. MAXIMUM ALLOWED CIC DECIMATION VS. NUMBER OF STAGES AND MAXIMUM EXPONENT

CIC STAGES MAXIMUM FLOATING POINT OR RANGE CONTROL EXPONENT

01234567 5 512 445 388 337 294 256 222 194 4 2435 2048 1722 1448 1217 1024 861 724 3 32768 26007 20642 16384 13003 10321 8192 6501 2 65536 65536 65536 65536 65536 65536 65536 65536 1 65536 65536 65536 65536 65536 65536 65536 65536

T ABLE 3. MAXIMUM CIC DECIMATION VERSUS NUMBER OF STA GES AND MAXIMUM EXPONENT TO MAINTAIN AT LEAST 24 BITS

OF DYNAMIC RANGE AT THE CIC OUTPUT

CIC STAGES MAXIMUM FLOATING POINT OR RANGE CONTROL EXPONENT

01234567 5 512 445 256 128 64 32 16 8 4 2435 2048 1722 1448 1217 1024 861 724 3 32768 26007 20642 16384 13003 10321 8192 6501 2 65536 65536 65536 65536 65536 65536 65536 65536 1 65536 65536 65536 65536 65536 65536 65536 65536

T ABLE 4. MAXIMUM CIC DECIMATION VERSUS NUMBER OF STA GES AND MAXIMUM EXPONENT TO MAINTAIN AT LEAST 20 BITS

OF DYNAMIC RANGE AT THE CIC OUTPUT

CIC STAGES MAXIMUM FLOATING POINT OR RANGE CONTROL EXPONENT

01234567 5 512 445 388 337 294 256 222 128 4 2435 2048 1722 1448 1217 1024 861 724 3 32768 26007 20642 16384 13003 10321 8192 6501 2 65536 65536 65536 65536 65536 65536 65536 65536 1 65536 65536 65536 65536 65536 65536 65536 65536

Back-end Routing

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ISL5416

MAG

AGC

LOOP

FILTER

MUX

GAIN

FROM

CIC

YPASS

ASCADED HANNELS

U X

1X 2X 4X 8X

GAIN

UP TO 32 TAPS

FIR1

4 TAPS/CLK HBF MODE

1X 2X 4X 8X

GAIN

UP TO 64 TAPS

FIR2

8 TAPS/CLK

FIR Filter Blocks

There are two programmable FIR filters in each channel. The main function of the first filter, FIR1, is to reduce the CIC output sample rate and maximize the efficiency of the second filter, FIR2. FIR2 provides the final filtering for the channel of interest. FIR1 can compute up to 32 taps and has programmable 20-bit coefficients, 20-bit data inputs, and 24bit outputs. FIR2 can compute up to 64 taps and has programmable 20-bit coefficients, 20-bit input data, and 24bit output data. FIR1 can compute 4 filter taps per clock and FIR2 can compute 8. All of the available taps can be utilized if the overall decimation through the CIC and FIRs is 8 or more. The impulse response of each FIR can be symmetric or asymmetric. The decimation for the each FIR is programmable from 1 to 8.

AGC

MULT

EXTERNAL AGC GAIN

MAG

DETECT

FIFO IHBF

HOIF

NOTE: When loading halfband coefficients, the coefficients must be

centered around the fixed center coefficient, e.g. if there are 23 taps, three compute clocks are required, there are 11 on either side of the center and multiplier 1 computes C0, C2, C4, multiplier 2 C6, C8, C10, etc.

If there are 19 coefficients, multiplier 2 computes C4, C6, C8 and multiplier 1 computes Z, C0, and C2, i.e. an extra zero valued coefficient must be added at each end of the coefficient set to center the coefficients at the fixed coefficient.

The filters will have unity gain if the sum of all coefficients is

equal to 1 for coefficient bit weighting 2

. . . 2

-19

To maximize dynamic range, the output bit width of the CIC and each FIR is 24 bits. A programmable gain stage is provided before each FIR to compensate for losses in preceding stages and round to the 20-bit FIR input bit width. Gains of 1, 2, 4, or 8 can be programmed. Saturation logic is provided to prevent overflow.

FIR1 includes a half-band filter mode where a fixed center coefficient of 0.5 is added and the zero valued half-band coefficients are skipped in the computation. This allows FIR1 to compute a 15-tap half-band filter in two clock cycles or a 31-tap half-band filter in four clock cycles.

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MUX

LIMIT

DET

RND

4...-30

BYPASS

0...-19 1

REG

FILE

0...-19

LIMIT

DET

RND

REG

FILE

A D D

REG

FILE

C O N T R O L

REG

FILE

x1, 2, 4, 8

MUX

0...-23

MUX

LIMIT

DET

RND

4...-30

REG

FILE

0...-19

LIMIT

DET

RND

REG

FILE

REG

0 / 0.5 FIXED

MUX

C O N T R O L

A D D

REG

FILE

REG

FILE

ENABLE

MUX

x1, 2, 4, 8

0...-23

MUX

FIGURE 4. FIR1 AND FIR2 BLOCK DIAGRAMS

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AGC

The automatic gain control (AGC) section adds gain to maintain the output signal level at a programmed level. The AGC moderates signal level variation at the output of the part and reduces the number of bits that must be carried in any post processing. In the ISL5416, the AGC follows the channel filtering. The gains through the NCO, mixer, and FIR filter sections are fixed gains and do not induce AM distortion before the large interfering signals can be filtered out. If large interfering signals are not removed by the filtering prior to the AGC, the gain adjustments by the AGC can AM modulate the large signals and cause AM sidebands to fall inside the frequency band of interest.

A block diagram of the A GC is included in figure 6. The AGC consists of a forward gain path and a loop filter path. In the forward gain path, the I/Q samples are scaled by the AGC forward gain value provided by the loop filter. The forward path gain is divided between a barrel shifter and a multiplier. The overall forward path gain range is 0 to 96.33 dB. The barrel shifter provides 0 to 90 dB of gain in steps of 6 dB. The multiplier provides linear gain between 1.0 and 2.0. Saturation is provided if there is overflow. The AGC only adds gain. The loop filter path computes the gain error, filters it, compares it to gain limits, and provides it to the forward gain path, to the uP interface, and to the output section. In the loop filter path the gain error is computed by first computing the magnitude of the forward path output. The magnitude is then subtracted from a programmable threshold or set point. The resulting error value is then scaled by a programmable loop gain and integrated and provided to the forward path. Programmable limits on the forward gain allow the user to restrict the gain to a smaller range than the 96 dB provided.

The forward gain control word and programmable gain limits are floating-point numbers consisting of a four-bit exponent that controls the barrel shifter and a mantissa portion that controls the multiplier. The barrel shifter gain is 2 multiplier gain is 16 bits, but the two MSBs are fixed at “01” and are not included in the gain control word. The mantissa MSB is therefore weighted as 0.5 and the mantissa gain is

1.0 + MANT. The total AGC gain in dB is then: 20*log The AGC range is then 0 to 96.33 dB for the EXP range of 0

to 15 and MANT range from 0 to 1. Plots of AGC gain versus the control word are provided in figures 5A and 5B.

The AGC gain word is available through the uP interface and as a real time output. The gain word is inversely proportional to the received signal strength in the channel. Signal strength in dB can be easily estimated by complementing the gain word and adding an offset equal to the fixed receive path gain in dB.

EXP

( 2

* (1.0 + MANT)).

EXP

. The

The AGC includes a set of counters to synchronize the AGC to system timing. The counters can be aligned to the SYNCInX signals if enabled in IWA *000h. One counter is programmed to count modulo N clocks where N is the length of the time slot. This counter can be restarted with SYNCInX to align/re-align it with the slots. A second counter counts out a delay from the SYNCInX or counter-generated sync. This delays the AGC timing from the SYNCInX signal to compensate for filter group dela y or other system delays. A third counter counts out an interval. The interval can be used to divide the slot into fast and slow update periods (timed mode) or into measurement and update periods (sampled mode). The counters can also be disabled and the AGC allowed to free run (continuos mode).

A programmable data delay can be inserted in the forward data path. The loop filter uses the samples into the delay for computing the new forward gain. The forward gain is then applied to the samples coming out of the delay. The gain applied to the output can be continuously updated or can be updated under the control of the counters. When updated continuously, the delay causes the forward gain to be based on samples before and after the delayed sample. This moderates large signal variations and minimizes the amount of time that the forward path may be in saturation or be at a small level.

The sampled mode is used for burst type signals where the gain adjustment is made during the first part of the burst and then held for the duration of the burst. The programmable delay can be set so that the first samples of the burst are exiting the delay when the gain is updated. In this mode, the gain may have large instantaneous changes, so proper timing alignment is very important.

In the timed mode, loop filter continuously updates the forward gain but uses one set of loop gains during part of the burst and another set for the rest of the burst. This allows the time slot to be divided into adapt/hold or fast/slow intervals.

The maximum throughput of the AGC depends on the mode. In the continuous (counters disabled) and timed modes without delay, the minimum spacing between samples into the AGC is 2 clocks. When the delay is enabled, this increases to 4. In the sampled mode, the delay is always enabled and the minimum spacing is 4. The minimum spacing is 1 when the AGC is bypassed.

The AGC loop feedback path includes a magnitude computation, an error detector, error scaling (loop gain), and a loop filter. The magnitude computation in the loop filter is a multi-pass operation with one pass computed per clock cycle. The accuracy of the computation depends on the number of passes. The minimum number of clocks between samples into the AGC is 2. There is a gain in the magnitude computation that must be taken into account when programming the AGC set point. This gain also depends on

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the number of passes in the computation. A listing the accuracy and gain is provided below.

TABLE 5. AGC MAGNITUDE COMPUTATION ACCURACY AND

GAIN

PASSES ERROR +/- (dB) GAIN

2 0.48 1.581 3 0.13 1.630 4 0.03 1.642 8 0.0001 1.647

With maximum gain and with full scale I and Q inputs equal to ~+/-1.0, the maximum output from the computation is

1.414 * 1.647 = 2.329. The error detector subtracts the magnitude from the programmable AGC Threshold value. The AGC Threshold value is set in IWA register *009h and should be programmed to K times the desired magnitude of the I/Q where K is the gain of the magnitude computation.

Two adjustment/settling modes are provided in the ISL5416. In the mean settling mode, the loop adjusts the gain so that the average magnitude is equal to the programmed set point. In this mode, the error is scaled by the loop gain and integrated to compute the forward gain. The loop settles to the final value asymptotically because the size of the adjustment decreases as the error decreases. The initial settling from large errors is fast, but the final pull in is slower . After the loop has settled, the small adjustment size causes minimal AM distortion of the signal. The other settling mode is the median mode. In this mode, the sign of the error is used increase or decrease the gain by a fixed amount. The amount of the adjustment is programmed by the loop gain. The loop settles to the point where there are an equal number of samples above and below the set point. The loop settling is roughly linear in dB, but after the loop has settled, the step size remains the same, so the amount of AM distortion may be objectionable. The ISL5416 provides two programmable loop gains, each with a separate attack and decay settling. The micro-processor can control the loop gain, or the AGC counters can select the loop gain, so a large loop gain can be used for initial settling and a smaller one for tracking. The counters can also select the settling mode, so the median mode can be used at the beginning of each time slot and the mean mode used after the initial settling.

The AGC loop filter is an accumulator (integrator). The output of the accumulator is the forward gain word that controls the barrel shifter and multiplier, closing the loop. There are programmable limits on the accumulator range to minimize settling time by restricting the AGC to only that portion of the 96 dB range that is needed. The accumulator can be loaded by the microprocessor. The gain load is double buffered-the gain is first loaded into a holding register by the uP. The gain is then transferred from the holding register to the accumulator by a write to a special address

location or by the SYNCInX if enabled in IWA *000. The AGC can be set to a fixed gain either by setting the both upper and lower gain limits to the desired gain or by setting the loop gain to zero and programming the accumulator directly.

The bit weighting for the AGC loop is provided in Table 86.

0 32768 65536 98304 131072 163840 196608 229376 262144

FIGURE 5A. ISL5416 AGC FORWARD GAIN RESPONSE

0 2048 4096 6144 8192 10240 12288 14336 16384

FIGURE 5B. ISL5416 AGC FORW ARD GAIN RESPONSE

ISL5416 AGC Forward Gain Response

Code

ISL5416 AGC Forward Gain Response

Ma gn i fi ed Vi ew

Code

MAGNIFIED VIEW (ACTUAL AND IDEAL LINEAR IN dB)

ISL5416

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LIMIT

DETECTOR

MUX

DETECT

OVERFLOW

-5

SAT

CLOCKS

UPPER / LOWER

DECAY 2 DECAY 1

ATTACK 2 ATTACK 1

MEAN/MED 2 MEAN/MED 1

LIMITS

MUX

SIGN

∆

SELECT

LOOP GAIN

SET POINT

SHIFT

BARREL

MUX

-4

CLOCKS

| X |

-6

CLOCKS

-A

ΥP DATA

DELAY = MAX(1 SAMPLE, 17 CLOCKS)

SAT

MUX

MODE

SAMPLED

GAIN

UPDATE

FORWARD

SHIFT

BARREL

0 - 63

DELAY

MEMORY

SAMPLES

DETECT

OVERFLOW

SHIFT

BARREL

FIGURE 6. AGC BLOCK DIAGRAM

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Interpolation Half Band Filter / Re-sampling Filter

A rate change section follows the AGC. This section is used to resample the signal from FIR2 to increase the sample rate for finer time resolution and/or to resample the data to another sample spacing. This section consists of an interpolation half-band filter, an interpolating resampling filter, a decimation counter/sampler, a FIFO, a set of NCOs, and a “leap” counter. This processing stage allows the filtering in FIR2 to be done at the lowest sample rate that meets the Nyquist criteria and the data then resampled to the desired final sample rate. The output/input sample rate ratio can be almost any value from 0.125 to >4096. A block diagram is provided below in Figure 8.

The re-sampling filter (HOIF) can accept inputs at any rate up to its maximum output rate of one half the clock rate. Preceding the resampler is an interpolation halfband filte r. This filter can be used to provide a fixed interpolation by 2 when the resampler is bypa sse d or, when used with the resampler, to increase the image-free dynamic range of the output. The IHBF can output at up to the clock rate if the resampling filter is bypassed and up to one half the clock rate if the resampling filter is enabled. Frequency response plots are provided below for the half-band and resampling filters. An example frequency response for a FIR2 response together with the half-band and resampling filters is also provided.

The resampling process produces images of the signal at multiples of the input sample rate. Large interfering signals must be removed from the spectrum with the CIC, FIR1, and FIR2 filters or the images created from them in the resampling process may cause problems. The level of the images created by resampling process has a fixed dBc level for a given se t of filters and samplin g ratio . As the signal le v el in the channel increases and decrease, the images levels will increase and decrease by the same amount. As the ratio of the FIR2 output sample rate to the band edge increases, the level, in dBc, of the images decreases.

-2 0

-4 0

-6 0

-8 0

10 0

0 5 10 15

FIGURE 7A. INTERPOLATION HALF BAND RESPONSE

-1 0

-2 0

-3 0

-4 0

-5 0

-6 0

-7 0

-8 0

0 0.5 1 1.5 2 2. 5 3

FIGURE 7B. IHBF (INTERPOLATE BY 2) AND RE-

SAMPLER (INTERPOLATE BY 2)

-1 0

-2 0

-3 0

-4 0

-5 0

-6 0

-7 0

-8 0

0 5 10 15

x 10

FIGURE 7C. INDIVIDUAL AND COMPOSITE RESPONSES (FIR2

OUTPUT AT 7.68 MHz WITH IHBF, INTERPOLATE BY 2)

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-1 0

-2 0

-3 0

-4 0

-5 0

-6 0

-7 0

-8 0

0 0. 5 1 1. 5 2 2. 5 3

FIGURE 7D. INDIVIDUAL AND COMPOSITE

RESPONSES (FIR2 OUTPUT AT 7.68 MHz WITH IHBF,

INTERPOLATE BY 2 AND RE-SAMPLER, INTERPOLATE BY 2

x 10

ISL5416

Two NCOs and two counters set the sample rates through the rate change section. NCO1 sets the output sample rate of the resampling filter. NCO1 is 48 bits and is updated at the clock rate, so its output frequency is:

Fout

= Fclk * N1 / 248,

where N1 is the 48-bit programming word. The carry output of the phase accumulator is used as the output clock, so there can be one clock period of jitter. NCO2 is programmed for the input sample rate to the resampler (equals the halfband filter output rate). NCO2 is updated at the NCO1 output rate. NCO2 controls the phase of the resampling filter. This NCO also has a 48-bit phase accumulator. The equation for programming the output frequency of NCO2 is:

Fout

= Fout1 * N2 / 248 = Fclk * (N1 / 248) * (N2 / 248)

when the resampling filter is enabled and Fout2 = Fclk * N2 / 248

-1 0

-2 0

-3 0

-4 0

-5 0

-6 0

-7 0

-8 0

0 5 10 15

FIGURE 7E. FIR2 AND IHBF COMPOSITE RESPONSE

-1 0

-2 0

-3 0

-4 0

-5 0

-6 0

-7 0

-8 0

0 0. 5 1 1.5 2 2.5 3

FIGURE 7F. FIR2, IHBF AND RESAMPLER COMPOSITE

RESPONSE

x 10

when the resampling filter is bypassed. NCO2 can have one output sample period (Fout

period) of jitter (one clock

period when the HOIF is bypassed). A static phase offset can be programmed for NCO2. The

range of the phase offset is 0 to 2 NCO2 output sample periods (0 - 2 resampling filter input sample periods). The programming resolution is 1/256 of a resampling filter input sample period. This programmable offset allows the user vary the group delay of one channel relative to another in very fine increments to compensate for differ ences in system delays.

If the resampler is not needed for rate change, it can be used for phase shifting by setting bit 22 in IWA *001h.

While the 48-bit phase accumulators provide very good frequency programming resolution, at some input/output sample rate ratios, there will be a slow phase drift due to the finite word length. To correct for this, a “leap” counter is provided to reset the phase of the NCOs after a programmed interval to remove any accumulated error. The leap counter is 32 bits. If properly programmed, this phase correction will not be seen in the output of the part.

The input rate to the IHBF/RS section must match the output sample rate of FIR2, i.e. the output rate of NCO2 must equal the input sample rate of the part divided by the decimation factors in the CIC, FIR1, and FIR2. The leap counter can guarantees this over the long term, but due to the jitter of the phase accumulator outputs, a FIFO is provided to guarantee that there are no dropped samples. The FIFO is filled at the output sample rate of the AGC and is emptied by Fout Fout

/2 if the IHBF is enabled). After reset, the FIFO is filled

(or

to a depth of two before the NCOs are enabled. This

minimum fill depth guarantees that there are enough samples in the FIFO that the FIFO never empties or overflows due to NCO jitter if the NCOs and leap counter are properly programmed. FIFO reads are enabled after an

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additional 0 to 3 input samples as programmed by the user. This additional depth provides for additional programmable group delay. The additional FIFO depth can only be programmed at reset. Because the NCOs are enabled after a depth of 2 is reached, the data into the IHBF/Resampler is zeroed until the programmed fill depth is reached. If both the half-band and resampling filters are enabled, the programmable FIFO depth, together with the NCO2 phase offset, provides from 0 to 4 FIR2 output sample periods of programmable group delay in 1/512 increments.

Because the IHBF and RS combination can only interpolate, for resampling ratios <1, the signal must first be interpolated to a multiple of the desired sample rate and then decimated

LEAP

R E

COUNTER

R E G

ROUND

FILL DEPTH BEFORE

ENABLING READS

0, 1, 2, or 3

0...-15

R E G

DEPTH = 2 + (0 to 3) SAMPLES

FIFO

Fihbf_in

IHBF

DIVIDE 1 OR 2

R E G

to the final rate. A decimation counter is provided after the resampling filter to down sample to the desired rate.

The NCO1 and NCO2 frequencies are programmed in IWA = *011h - *014h. These registers are double buffered. The uP writes to a holding register. Data is then transf erred to the active registers by a write to IWA = *017h or b y a SYNCInX if enabled in IWA = *000h.

The gain data from the AGC is not interpolated. The output of the AGC is sampled with each I/Q sample to the output section.

PHASE OFFSET

0 TO 511/256 SAMPLES

REG

MUX

DIVIDE

R E G

Fihbf_out

R E

MUX

REG

NCO2

FRACTIONAL

RESAMPLING

INTERPOLATION

FILTER

N x Fout

NCO1

Fclk

BY N

Fout

R E G

FIGURE 8. IHBF AND RESAMPLER BLOCK DIAGRAM

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Data Output Formatter Section

Four 16-bit output data busses are provided on the ISL5416. All of the busses share a common output clock, CLKO1, which is derived from CLKC. CLKO2 signal is provided for easier board routing or for the differential outputs. Each bus has an output SYNC which is typically used as a frame sync. Each bus can be divided into two 8-bit busses if desired. When a new data sample is available from a channel, it starts a time slot counter that sequences through up to 8 output time slots. The data type for each time slot is programmable as well as the FSYNCx assertion. The data from more than one channel can be multiplexed through the same output bus if channels are synchronized. The data from channels 0 and 1 and from channels 2 and 3 can be multiplexed directly. Multiplexing channels 0 and 1 with 2 and 3 is done by ORing multiplexer outputs together. See figures 10 and 11. This means that related channels (such as diversity channels) should be grouped into channels 0 and 1, or into channels 2 and 3 for ease of data routing.

I0 (23:16)

(15:8)

(7:0)

AGC0

AGC1 (15:8)

(23:16)

(15:8)

(7:0)

(15:8)

(7:0)

(23:16)

(15:8)

(7:0)

(23:16)

(15:8)

(7:0)

(15:8)

01AC UPPER 16 x 8-BIT MUX

The data type, SYNC assertion, and bus routing are programmed in registers 0*01h through 0*04h. Two of the eight time slots are programmed in each location.

The I/Q data from each channel is rounded to 4, 6, 8, 12, 16, 20 or 24 bits at the output of the channel. The AGC gain can be rounded to 8, 12, or 16 bits. A 24-bit output is provided to the output section for I and Q data and a 16-bit output is provided for the AGC data. The data is MSB justified in the output bus and the LSBs below the programmed number are zeroed.

24 bits of I/Q data is available from the AGC if the IHBF/HOIF is bypassed. I/Q are 16 bits if the IHBF/HOIF section is enabled.

Serial outputs are availa ble . See GW A = 0000h, IW A = 0*06h, 0*07h, and 0*08h.

I0 (23:16)

(15:8)

(7:0)

AGC0

AGC1 (15:8)

(23:16)

(15:8)

(7:0)

(15:8)

(7:0)

(23:16)

(15:8)

(7:0)

(23:16)

(15:8)

(7:0)

01AC LOWER 16 x 8-BIT MUX

01 AC UPPER

Channels

Output Byte

Outputs

FIGURE 9. MULTIPLEXING CHANNELS

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