intersil ISL54050 DATA SHEET

®

ISL54050

Data Sheet March 28, 2007

Ultra Low ON-Resistance, +1.65V to +4.5V ,
Single Supply, Dual SPDT Analog Switch

The Intersil ISL54050 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.65V to
+4.5V supply . Targeted applications include battery powered
equipment that benefit from low r
switching speeds (t

ON

= 40ns, t

input is 1.8V logic-compatible when using a single +3V supp ly.
Cell phones, for example, often face ASIC functionality

limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL54050 is offered in small form factor package, alleviating
board space limitations.

The ISL54050 is a committed dual single-pole/double-throw
(SPDT) that consist of two normally open (NO) and two
normally closed (NC) switches. This configuration can be
used as a dual 2-to-1 multiplexer. The ISL5 4050 is pin
compatible with the NLAS5223 and NLAS5223L.

TABLE 1. FEATURES AT A GLANCE

Number of Switches 2
SW SPDT or 2-1 MUX

4.3V R

ON

4.3V t

ON/tOFF

3V R

ON

3V t

ON/tOFF

1.8V r

ON

1.8V t

ON/tOFF

Package 10 Ld 1.8mmx1.4mmx0.5mm µTQFN

0.29Ω
40ns/20ns

0.33Ω
50ns/27ns

0.55Ω
70ns/54ns

(0.29Ω) and fast

ON

= 20ns). The digital logic

OFF

ISL54050

FN6356.1

Features

• Pb-Free Plus Anneal Available (RoHS Compliant)

• Pin Compatible Replacement for the NLAS5223 and
NLAS5223L

• ON Resistance (rON)

- V+ = +4.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29Ω

- V+ = +3.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33Ω

- V+ = +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55Ω

Matching Between Channels . . . . . . . . . . . . . . . .0.06Ω

•R

ON

Flatness Across Signal Range . . . . . . . . . . . . . . .0.03Ω

•R

ON

• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V

• Low Power Consumption (PD). . . . . . . . . . . . . . .<0.45µW

• Fast Switching Action (V+ = +4.3V)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns

-t

ON

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns

-t

OFF

• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV

• Break-before-Make

• 1.8V Logic Compatible (+3V supply)

• Low ICC Current when VinH is not at the V+ Rail

• Available in 10 Ld 1.8mmx1.4mmx0.5mm

µTQFN

Applications

• Battery powered, Handheld, and Portable Equipment

- Cellular/mobile Phones

- Pagers

- Laptops, Notebooks, Palmtops

• Portable Test an d Measurement

• Medical Equipment

• Audio and Video Switching

Ordering Information

Related Literature

• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

• Application Note AN557 “Recommended Test Procedures
for Analog Switches”

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

TEMP.

PART NUMBER

(Note)

ISL54050IRUZ-T A -40 to +85 10 Ld µTQFN

NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow t emperatures that meet or exce ed the Pb­free requirements of IPC/JEDEC J STD-020C.

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PART

MARKING

Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved

RANGE

(°C)

PACKAGE

(Pb-free)

T ape and Reel

PKG.

DWG. #

L10.1.8x1.4A

ISL54050

Pinout (Note 1)

ISL54050

(10 LD µTQFN)

TOP VIEW

NC2 GND

IN2

COM2

NO2

7

8

9

10

1

V+ NO1

6

5

NC1

4

IN1

3

COM1

2

NOTE:

1. Switches Shown for Logic “0” Input.

Truth T able

LOGIC NC1 and NC2 NO1 and NO2

0ONOFF
1OFFON

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.

Pin Descriptions

PIN FUNCTION

V+ System Power Supply Input (+1.65V to +4.5V)

GND Ground Connection

IN Digital Control Input

COM Analog Switch Common Pin

NO Analog Switch Normally Open Pin

NC Analog Switch Normally Closed Pin

2

FN6356.1

March 28, 2007

ISL54050

Absolute Maximum Ratings Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 5.5V

Input Voltages

NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)

Output Voltages

COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V t o ((V+) + 0.5V)

Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA

Peak Current NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .>8kV

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . .>500V

Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . >1.4kV

Operating Conditions

Temperature Range

ISL54050IRUZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Extended operation above the recommended
operating conditions could result in decreased reliability. The Absolute Maximum Ratings are stress only ratings and operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. θ

JA

Thermal Resistance (Typical) θ

(°C/W)

JA

10 Ld μTQFN Package (Note 3) . . . . . . . . . . . . . . . 143

Maximum Junction Temperature (Plastic Package). . . . . . . +150°C

Maximum Stor age Temperature Range. . . . . . . . . . . -65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(Lead Tips Only)

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Electrical Specifications - 4.3V Supply Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V

unless otherwise specified

PARAMETER TEST CONDITIONS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V
ON-Resistance, r

ON

ANALOG

V+ = 3.9V, I
(See Figure 5)

r

Matching Between Channels,

ON

Δr

ON

Flatness, r

r

ON

FLAT(ON)

NO or NC OFF Leakage Current,
I

NO(OFF)

or I

NC(OFF)

COM ON Leakage Current,
I

COM(ON)

V+ = 3.9V, I
max r

V+ = 3.9V, I
(Note 6)

V+ = 4.5V, V

V+ = 4.5V, V
3V or floating

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

Turn-OFF Time, t

ON

OFF

Break-Before-Make Time Delay, t

V+ = 3.9V, VNO or VNC = 3.0V, RL =50Ω, CL = 35pF,
(See Figure 1)

V+ = 3.9V, VNO or VNC = 3.0V, RL =50Ω, CL = 35pF,
(See Figure 1)

V+ = 4.5V, VNO or VNC = 3.0V, RL =50Ω, CL = 35pF,

D

(See Figure 3)
Charge Injection, Q C
OFF Isolation R

L
L

(See Figure 4)

TEMP

= 100mA, VNO or VNC = 0V to V+,

COM

ON,

= 100mA, VNO or V

COM

(Note 7)

= 100mA, VNO or VNC = 0V to V+,

COM

= 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 -100 100 nA

COM

= 0.3V, 3V, or VNO or VNC = 0.3V,

COM

= Volt age at

NC

= 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 170 pC
= 50Ω, CL = 5pF, f = 100kHz, V

COM

= 1V

RMS

,

(NOTE 5)

(°C)

Full 0 V+ V

25 0.30 Ω

Full 0.35 Ω

25 0.06 Ω

Full 0.08 Ω

25 0.03 Ω

Full 0.04 Ω

Full -195 195 nA

25 -100 100 nA

Full -195 195 nA

25 40 ns

Full 50 ns

25 20 ns
Full 30 ns
Full 8 ns

25 62 dB

= 1.6V, V

INH

MIN TYP

= 0.5V (Note 4),

INL

(NOTE 5)

MAX UNITS

3

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March 28, 2007

ISL54050

Electrical Specifications - 4.3V Supply Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V

= 1.6V, V

INH

= 0.5V (Note 4),

INL

unless otherwise specified (Continued)

PARAMETER TEST CONDITIONS

Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 100kHz, V

(See Figure 6)
Total Harmonic Distortion f = 20Hz to 20kHz, V
NO or NC OFF Capacitance, C
COM ON Capacitance, C

COM(ON)

f = 1MHz, VNO or VNC = V

OFF

f = 1MHz, VNO or VNC = V

COM

= 2V

P-P

= 0V, (See Figure 7) 25 62 pF

COM

= 0V, (See Figure 7) 25 176 pF

COM

TEMP

COM

= 1V

RMS

,

, RL = 600Ω 25 0.005 %

(°C)

(NOTE 5)

MIN TYP

(NOTE 5)

MAX UNITS

25 -85 dB

POWER SUPPLY CHARACTERISTICS

Power Supply Range Full 1.65 4.5 V
Positive Supply Current, I+ V+ = +4.5V, V

= 0V or V+ 25 0.1 µA

IN

Full 1 µA

Positive Supply Current, I+ V+ = +4.2V, V

= 2.85V 25 12 µA

IN

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V
Input Voltage High, V
Input Current, I

INH

, I

INL

INH

INL

V+ = 4.5V, VIN = 0V or V+ Full -0.5 0.5 µA

Full 0.5 V
Full 1.6 - V

NOTES:

= input voltage to perform proper function.

4. V

IN

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON

7. r

ON

value, between NC1 and NC2 or between NO1 and NO2.

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

unless otherwise specified

PARAMETER TEST CONDITIONS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V
ON-Resistance, r

Matching Between Channels,

r

ON

Δr

ON

Flatness, r

r

ON

FLAT(ON)

ON

ANALOG

V+ = 2.7V, I
(See Figure 5)

V+ = 2.7V, I
max r

V+ = 2.7V, I
(Note 6)

NO or NC OFF Leakage Current,
I

NO(OFF)

or I

NC(OFF)

COM ON Leakage Current,
I

COM(ON)

V+ = 3.3V, V

V+ = 3.3V, V
or floating

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

Turn-OFF Time, t

ON

OFF

V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1)

V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1)

, (Note 7)

ON

TEMP

= 100mA, VNO or VNC = 0V to V+,

COM

= 100mA, VNO or V

COM

= 100mA, VNO or VNC = 0V to V+,

COM

= 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 0.9 nA

COM

= 0.3V , 3V , or VNO or VNC = 0.3V , 3V ,

COM

= Volt age at

NC

(NOTE 5)

(°C)

Full 0 V+ V

25 0.35 0.5 Ω

Full 0.7 Ω

25 0.06 0.07 Ω

Full 0.08 Ω

25 0.03 0.15 Ω

Full 0.15 Ω

Full 30 nA

25 0.8 nA

Full 30 nA

25 50 ns

Full 60 ns

25 27 ns

Full 35 ns

= 1.4V, V

INH

MIN TYP

= 0.5V (Note 4),

INL

(NOTE 5)

MAX UNITS

4

FN6356.1

March 28, 2007

ISL54050

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

unless otherwise specified (Continued)

PARAMETER TEST CONDITIONS

Break-Before-Make Time Delay, tDV+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,

(See Figure 3)
Charge Injection, Q C
OFF Isolation R

= 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 94 pC

L

= 50Ω, CL = 5pF, f = 100kHz, V

L

COM

= 1V

RMS

,

(See Figure 4)
Crosstalk (Channel-to-Channel) R

= 50Ω, CL = 5pF, f = 100kHz, V

L

COM

= 1V

RMS

,

(See Figure 6)

= 2V

Total Harmonic Distortion f = 20Hz to 20kHz, V
NO or NC OFF Capacitance, C
COM ON Capacitance, C

COM(ON)

f = 1MHz, VNO or VNC = V

OFF

f = 1MHz, VNO or VNC = V

COM

, RL = 600Ω 25 0.005 %

P-P

= 0V, (See Figure 7) 25 65 pF

COM

= 0V, (See Figure 7) 25 181 pF

COM

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = +3.6V, V

= 0V or V+ 25 0.01 μA

IN

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V
Input Voltage High, V
Input Current, I

INH

INL

INH

, I

INL

V+ = 3.3V, VIN = 0V or V+ Full -0.5 0.5 μA

TEMP

(NOTE 5)

(°C)

Full 9 ns

25 62 dB

25 -85 dB

Full 0.52 μA

25 0.5 V
25 1.4 V

= 1.4V, V

INH

MIN TYP

= 0.5V (Note 4),

INL

(NOTE 5)

MAX UNITS

Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.65V to +2V, GND = 0V, V

unless otherwise specified

PARAMETER TEST CONDITIONS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V
ON-Resistance, r

ON

ANALOG

V+ = 1.65V, I

(See Figure 5)

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

Turn-OFF Time, t

ON

OFF

Break-Before-Make Time Delay, t

V+ = 1.65V , VNO or VNC = 1.0V , RL =50Ω, CL = 35pF,

(See Figure 1)

V+ = 1.65V , VNO or VNC = 1.0V , RL =50Ω, CL = 35pF,

(See Figure 1)

V+ = 2.0V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,

d

(See Figure 3)
Charge Injection, Q C
NO or NC OFF Capacitance, C
COM ON Capacitance, C

COM(ON)

L

f = 1MHz, VNO or VNC = V

OFF

f = 1MHz, VNO or VNC = V

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V
Input Voltage High, V
Input Current, I

INH

INL

INH

, I

INL

V+ = 2.0V, VIN = 0V or V+ Full -0.5 0.5 μA

TEMP

= 100mA, VNO or VNC = 0V to V+,

COM

= 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 42 pC

= 0V, (See Figure 7) 25 70 pF

COM

= 0V, (See Figure 7) 25 186 pF

COM

(NOTE 5)

(°C)

Full 0 V+ V

25 0.7 0.8 Ω

Full 0.85 Ω

25 70 ns

Full 80 ns

25 54 ns
Full 65 ns
Full 10 ns

25 0.4 V

25 1.0 V

= 1.0V, V

INH

INL

MIN TYP

= 0.4V (Note 4),

(NOTE 5)

MAX UNITS

5

FN6356.1

March 28, 2007

Test Circuits and Waveforms

V+

LOGIC
INPUT

SWITCH

INPUT

SWITCH

OUTPUT

0V

V

NO

0V

50%

t

ON

90%

t

OFF

V

OUT

Logic input waveform is inverted for switches that have the opposite
logic sense.

tr < 5ns

< 5ns

t

f

90%

ISL54050

SWITCH

LOGIC

INPUT

INPUT

NO or NC

IN

Repeat test for all switches. C

capacitance.

V

OUT

V

=

(NO or NC)

V+

C

COM

R

+

RL
50Ω

L

ON()

GND

includes fixture and stray

L

----------------------------

RLr

V

OUT

C

L

35pF

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

V+

R

G

SWITCH

OUTPUT

V

OUT

LOGIC

INPUT

ON

Q = ΔV

OUT

ΔV

x C

OUT

L

OFF

ON

V+

0V

V

G

NO or NC

GND

Repeat test for all switches.

FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

C

V

COM

IN

LOGIC

INPUT

OUT

C

L

LOGIC
INPUT

SWITCH
OUTPUT

V

OUT

V+

0V

0V

t

D

FIGURE 3A. MEASUREMENT POINTS

FIGURE 3. BREAK-BEFORE-MAK E TIME

6

90%

V

NX

LOGIC

INPUT

NO

NC

IN

Repeat test for all switches. C
capacitance.

FIGURE 3B. TEST CIRCUIT

V+

C

COM

GND

includes fixture and stray

L

R

50Ω

V

L

OUT

C

L

35pF

FN6356.1

March 28, 2007

Test Circuits and Waveforms (Continued)

V+

C

SIGNAL
GENERATOR

ANALYZER

R

L

NO or NC

COM

GND

IN

0V or V+

ISL54050

rON = V1/100mA

V

NX

100mA

V

1

NO or NC

COM

GND

V+

IN

C

0V or V+

Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.

FIGURE 4. OFF ISOLATION TEST CIRCUIT FIGURE 5. RON TEST CIRCUIT

V+

C

SIGNAL
GENERATOR

0V or V+

ANALYZER

R

L

Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.

NO or NC

IN

1

COM

COM

NC or NO

GND

50Ω

N.C.

FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT

Detailed Description

The ISL54050 is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
on-resistance (0.29Ω) and high speed operation
(t

=40ns, t

ON

suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(4.5μW max), low leakage currents (195nA max), and the tiny
μTQFN package. The ultra low on-resistance and r
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain

= 20ns). The device is especially well

OFF

ON

Repeat test for all switches.

V+

C

NO or NC

0V or V+

IN

IMPEDANCE

ANALYZER

COM

GND

Repeat test for all switches.

ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.

If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.

Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 8). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-microamp input current

7

FN6356.1

March 28, 2007

ISL54050

produces an insignificant voltage drop during normal
operation.

This method is not acceptab l e for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low R

switch. Connecting schottky

ON

diodes to the signal pins as shown in Figure 8 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These schottky diodes must be sized to handle the
expected fault current.

OPTIONAL
SCHOTTKY
DIODE

V+

OPTIONAL
PROTECTION
RESISTOR

OPTIONAL
SCHOTTKY
DIODE

FIGURE 8. OVERVOLTAGE PROTECTION

IN

X

V

NX

GND

V

COM

Power-Supply Considerations

The ISL54050 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL54050 5.5V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.

The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the Electrical Specification tables and “Typical
Performance Curves” on page 9 for details.

V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.

This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.

The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.

The ISL54050 has been designed to minimize the supply
current whenever the digital input voltage is not driven to the
supply rails (0V to V+). For example, driving the device with

2.85V logic (0V to 2.85V) while operating with a 4.2V supply,
the device draws only 12
V

=2.85V).

IN

μA of current (see Figure 16 for

Frequency Performance

In 50Ω systems, the ISL54050 has a -3dB bandwidth of
120MHz (see Figure 21). The frequency response is very
consistent over a wide V+ range and for varying analog
signal levels.

An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough, while crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 22 details the high off isolation and crosstalk rejection
provided by this part. At 100kHz, off isolation is about 62dB
in 50Ω systems, decreasing approximately 20dB per decade
as frequency increases. Higher load impedances decrease
off isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load
impedance.

Leakage Considerations

Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.

Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the
analog-signal-path leakage current. All analog leakage
current flows between each pin and one of the supply
terminals, not to the other switch terminal. This is why both
sides of a given switch can show leakage currents of the
same or opposite polarity. There is no connection between
the analog signal paths and V+ or GND.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.7V to 4.5V (see Figure 16). At 2.7V
the V

level is about 0.53V. This is still above the 1.8V

IL

CMOS guaranteed low output maximum level of 0.5V, but
noise margin is reduced.

8

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March 28, 2007

ISL54050

Typical Performance Curves T

0.30

0.29

0.28

(Ω)

ON

r

0.27

0.26

0.25

012345

V+ = 3.9V

V+ = 4.3V

V

COM

V+ = 4.5V

(V)

= +25°C, Unless Otherwise Specified

A

I

COM

FIGURE 9. ON-RESISTANCE vs SUPPL Y VOLTAGE vs

SWITCH VOLTAGE

0.70

0.65

0.60

0.55

(Ω)

0.50

ON

r

0.45

0.40

V+ = 1.65V

V+ = 1.8V

V+ = 2V

I

COM

= 100mA

= 100mA

0.35

0.34

0.33

0.32

(Ω)

ON

0.31

r

0.30

0.29

0.28

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

V+ = 2.7V

V+ = 3V

V+ = 3.3V

V

COM

(V)

I

COM

= 100mA

FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

0.35

0.30

(Ω)

ON

r

0.25

+85°C

+25°C

V+ = 4.3V

I

COM

= 100mA

0.35

0.30

0 0.5 1.0 1.5 2.0

V

COM

(V)

FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs

0.20

012345

FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE

-40°C

V

COM

(V)

SWITCH VOLTAGE

0.40

0.35

(Ω)

0.30

ON

r

0.25

0.20

0 0.51.01.52.02.53.03.5

+85°C

+25°C

-40°C

V

COM

(V)

V+ = 3.3V

I

COM

= 100mA

0.40

+85°C

0.35

(Ω)

ON

r

0.30

0.25

0 0.5 1.0 1.5 2.0 2.5 3.0

+25°C

-40°C

V

COM

(V)

V+ = 2.7V

I

COM

FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE

= 100mA

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FN6356.1

March 28, 2007

ISL54050

Typical Performance Curves T

0.60

0.55

0.50

0.45

(Ω)

ON

r

0.40

0.35

0.30

0.25

0 0.5 1.0 1.5 2.0

+85°C

+25°C

-40°C

V

COM

(V)

= +25°C, Unless Otherwise Specified (Continued)

A

V+ = 1.8V

I

COM

= 100mA

200

150

100

(μA)

ON

i

50

0

SWEEPING BOTH LOGIC INPUTS

12345

V

IN1

AND V

IN2

(V)

FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 16. SUPPLY CURRENT vs VLOGIC VOLTAGE

200

150

100

50

Q (pC)

V+ = 1.8V

0

-50

V+ = 4.3V

V+ = 3V

(V)

AND V

V

INL

INH

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

V

INH

V

INL

V+ = 4.2V

-100

012345

V

(V)

COM

0.3

1.5 2.0 2.5 3.0 3.5 4.0 4.5
V+ (V)

FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE

(ns)

OFF

t

200

150

100

50

+85°C

+25°C

-40°C

0

1.5 2.0 2.5 3.0 3.5 4.0 4.5

1.0

V+ (V)

250

200

(ns)

150

ON

t

100

25

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

+85°C

+25°C

-40°C

V+ (V)

FIGURE 19. TURN-ON TIME vs SUPPLY VOLTAGE FIGURE 20. TURN-OFF TIME vs SUPPLY VOLTAGE

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FN6356.1

March 28, 2007

ISL54050

Typical Performance Curves T

V+ = 3V

0

GAIN

-20

PHASE

NORMALIZED GAIN (dB)

RL = 50Ω
VIN = 0.2V

1 10 100 600

to 2V

P-P

FREQUENCY (MHz)

P-P

A

FIGURE 21. FREQUENCY RESPONSE FIGURE 22. CROSSTALK AND OFF ISOLATION

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

114

= +25°C, Unless Otherwise Specified (Continued)

-10
V+ = 4.3V

-20

-30

-40

0

20

40

60

80

100

PHASE (°)

-50

-60

-70

CROSSTALK (dB)

-80

-90

-100

-110
1k 100k 1M 100M500M10k 10M

ISOLATION

CROSSTALK

FREQUENCY (kHz)

10

20

30

40

50

60

70

80

90

100

110

OFF ISOLATION (dB)

PROCESS:

Submicron CMOS

11

FN6356.1

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ISL54050

Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)

INDEX AREA

2X

0.10 C

0.05 C

SEATING PLANE

NX (b)

5

SECTION "C-C"

6

2X

0.10 C

0.10 C

A

A1

(DATUM A)

PIN #1 ID

L1

(A1)

1.00

N

TOP VIEW

SIDE VIEW

7

BOTTOM VIEW

CC

D

e

e

2.20

1.00

0.60

A

B

L10.1.8x1.4A

10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE

E

SYMBOL

21

A 0.45 0.50 0.55 -

MILLIMETERS

NOTESMIN NOMINAL MAX

A1 - - 0.05 ­A3 0.127 REF -

b 0.15 0.20 0.25 5

D 1.75 1.80 1.85 -

C

E 1.35 1.40 1.45 ­e 0.40 BSC ­L 0.35 0.40 0.45 -

L1 0.45 0.50 0.55 -

N102

Nd 2 3

NX L

21

5

5

NX b

10X

0.10 M C A B

0.05 M C

(DATUM B)

Ne 3 3

θ

0-12

Rev. 3 6/06

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

4

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on D and E side,
respectively.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

C

L

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identi fier may be

L

either a mold or mark feature.

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

TERMINAL TIP

9. JEDEC Reference MO-255.

10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.

0.50

1.80

0.40

0.20

10

LAND PATTERN

0.40

0.20

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiari es.

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12

FN6356.1

March 28, 2007