The Intersil ISL54003, ISL54005, ISL54006 family of devices
are integrated audio power amplifier systems that combine a
mono BTL amplifier and stereo headphone a mp lifiers i n a
single device. The devices are designed to operate from a
single +2.7V to +5V power supply. Targeted applications
include handheld equipment such as cell-phones, MP3
players, and games/toys.
These parts contain one class AB BTL type p ower amplifier
for driving an 8Ω mono speaker and two class AB headphone
amplifiers for driving 16Ω or 32Ω headphone speakers.
The BTL when using a 5V supply is capable of delivering
800mW (typ) with 0.4% THD+N and 941mW (typ) with 1%
THD+N of continuous average power into an 8Ω BTL speaker
load.
Each headphone amplifier when using a 5V supply is capable
of delivering 50mW (typ) with 0.3% THD+N and 94mW (typ)
with 1% THD+N of continuous average power into a 32Ω
headphone speaker .
When in Mono Mode these devices automatically mix the
active left and right audio inputs and send the combi ned signal
to the BTL driver. In Head phone Mode the active right channel
input is sent to the right headphone speaker and the active left
channel is sent to the left headphone speaker.
The ISL54005 and ISL54006 feature a 2:1 stereo input
multiplexer front-end. This allows selection between two
stereo sources. In addition the ISL54006 can mix the four
inputs to the BTL driver or the two pairs of inputs to the
headphone drivers.
These parts feature headphone sense circuitry that detects
when a headphone jack has been inserted and automatically
switches the active audio inputs from the mono BTL output
driver to the headphone drivers. These parts also feature a
logic control pin that can override the headphone sense
input circuitry.
All devices in this family feature low power shutdown,
thermal overload protection and click/pop suppression. The
click and pop circuitry eliminates audible transients during
audio source changes and transitioning in and out of
shutdown.
FN6514.1
Features
• Pb-Free Plus Anneal (RoHS Compliant)
• Class AB 94mWHeadphone Amplifiers and 941mW Mono
BTL Speaker Ampli fie r
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and com patible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-0 20.
PKG.
DWG. #
L20.4x4A
L20.4x4A
L20.4x4A
ISL54003 Truth Table
SDHDHOSPK+/SPK-HpRHpL
1XXDisabledDisabledDisabled
00X IN
010-IN
011 INR + IN
R
+ IN
L
L
--
R
IN
--
ISL54005 Truth Table
SDINSHDHOSPK+/SPK-HpRHpL
1XXXDisabledDisabledDisabled
000XIN
0010-IN
0011IN1R + IN
010XIN
0110-IN
0111IN2R + IN
1R
2R
+ IN
+ IN
1L
1L
2L
2L
--
1R
IN
--
--
2R
IN
--
ISL54006 Truth Table
SD MIX INS HD HOSPK+/SPK-HpRHpL
1XXXXDisabledDisabled Disabled
0000XIN
00010-IN1RIN
00011IN1R + IN
0010XIN
00110-IN2RIN
00111IN2R + IN
01X0XIN
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ
1. θ
JA
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
2. For θ
, the “case temp” location is the center of the exposed metal pad on the package underside.
Off-IsolationSD = V
Signal to Noise Ratio, SNRR
Channel Gain Matching
to L
R
CH
CH
Channel Phase Matching
R
to L
CH
CH
= 32Ω, POUT = 50mW, f = 1kHz25-85-dB
L
RL = 32Ω, VINxR = VINxL = 1.3V
same source)
RL = 32Ω, VINxR = VINxL = 1.3V
same source)
LOGIC INPUT
Input Leakage Current, I
I
, IHD, I
MIX
HO
Input Leakage Current, I
I
, IHD, I
MIX
V
V
INH
INL
HO
SD
SD
, I
,
VDD = 5V, SD = 0V, INS = 0V, MIX = 0V, HD = 0V,
INS
HO = 0V
, I
,
VDD = 5V, SD = VDD, INS = VDD, MIX = VDD,
INS
HD = V
= 900mW, f = 1kHz25-85-dB
OUT
= 800mW, f = 1kHz, Signal coupled
OUT
DD, POUT
DD, RL
DD
= 800mW, f = 10kHz, Signal
HO = V
INH,
= 200mV
P-P
= 50mW, f = 1kHz25-0.3-%
OUT
= 50mW, f = 20Hz to 20kHz25-0.4-%
OUT
= 5V
SIGNAL
= 15mW, f = 1kHz25-75-dB
OUT
= 32Ω, P
UNLESS OTHERWISE SPECIFIED
INL,
, HD = 0V,
, f = 1kHz253.64.7-V
P-P
= 15mW, f = 10kHz25-95-dB
OUT
, HO = VDD,
= +5V , GND = 0V, V
DD
F
F
RMS
RMS
= 217Hz25-48-dB
RIPPLE
= 1kHz25-47-dB
RIPPLE
(Connect to the
(Connect to the
= 2.4V , V
INH
TEMP
(°C)
= 0.8V , SD = MIX = INS = HD = V
INL
MIN
(Notes 4, 5)TYP
(Notes 4, 5)UNITS
MAX
25-80-dB
25-110-dB
25-±0.2-dB
25-1.3-°
25-31.93µA
Full-1.9-µA
25-10.021µA
Full-0.02-µA
Full2.4--V
Full--0.8V
INL
RMS
P-P
,
5
FN6514.1
June 27, 2007
ISL54003, ISL54005, ISL54006
Electrical Specifications - 3.6V Supply Test Conditions: V
GSO = GS1 = V
and between Hp_ and GND for SE drivers, Unless Otherwise Specified (Note 3).
PARAMETERTEST CONDITIONS
= +3.6V, GND = 0V, V
DD
, C
INL
= 1µF, RL is terminated between SPK+ and SPK- for BTL driver
REF
TEMP
(°C)
= 1.4V. V
INH
MIN
(Notes 4, 5)TYP
= 0.4V, SD = MIX = INS =
INL
MAX
(Notes 4, 5) UNITS
GENERAL
Quiescent Supply Current, I
Shutdown Supply Current, I
DD
SD
HO = V
INL
MIX = V
INL
(SE), Input AC coupled to ground (0.1µF)
HO = V
INL
MIX = V
INL
ground (0.1µF)
SD = VDD, HO = V
INS = V
INL
(BTL) and R
ground (0.1µF)
BTL AMPLIFIER DRIVER, HD = V
Output Offset Voltage, V
OS
Power Supply Rejection Ratio,
PSRR
HO = V
INH,
Measured between SPK+ and SPK-, Input AC
coupled to ground (0.1µF)
V
R
= 200mV
RIPPLE
= 8Ω, input AC coupled to
L
ground (0.1µF)
Output Power, P
OUT
Total Harmonic Distortion + Noise,
THD + N
Max Output Volt age Swing, V
RL = 8Ω, THD+N = 1%, f = 1kHz25-310-mW
= 8Ω, THD+N = 10%, f = 1kHz25-528-mW
R
L
= 8Ω, P
R
L
= 8Ω, P
R
L
OUTRL
= 8Ω, VSIGNAL = 3.6V
SINGLE ENDED AMPLIFIER DRIVERS, HD = V
Power Supply Rejection Ratio,
PSRR
Output Power, P
OUT
Total Harmonic Distortion + Noise,
THD + N
Max Output Volt age Swing, V
OUTRL
V
R
ground (0.1µF)
RL = 16Ω, THD+N = 1%, f = 1kHz25-80-mW
R
R
R
R
R
= 200mV
RIPPLE
= 32Ω, Ιnput AC coupled to
L
= 32Ω, THD+N = 1%, f = 1kHz25-47-mW
L
= 16Ω, THD+N = 10%, f = 1kHz25-107-mW
L
= 32Ω, THD+N = 10%, f = 1kHz25-58-mW
L
= 32Ω, P
L
= 32Ω, P
L
= 32Ω, V
or V
, HD = V
INH
or V
, RL = 8Ω (BTL) and RL = 32Ω
INH
or V
, HD = V
INH
or V
, RL = None, Input AC coupled to
INH
INL
or V
, MIX = V
INH
= 32Ω (SE), Input AC coupled to
L
UNLESS OTHERWISE SPECIFIED
INH,
, HD = 0V ,
P-P
= 200mW, f = 1kHz25-0.4-%
OUT
= 200mW, f = 20Hz to 20kHz25-0.4-%
OUT
HO = V
INH,
, HD = 0V ,
P-P
= 30mW, f = 1kHz25-0.2-%
OUT
= 30mW, f = 20Hz to 20kHz25-0.3-%
OUT
= 3.6V
SIGNAL
, INS = V
INL
, INS = V
INL
or V
, HD = Float,
INH
or V
INL
F
F
, f = 1kHz25-5.8-V
P-P
UNLESS OTHERWISE SPECIFIED
INL,
F
F
, f = 1kHz25-3.2-V
P-P
or V
INL
INH
or V
INL
INH
, RL = 8Ω
INH
= 217Hz25-49-dB
RIPPLE
= 1kHz25-47-dB
RIPPLE
= 217Hz25-48-dB
RIPPLE
= 1kHz25-47-dB
RIPPLE
25-450mA
,
Full-10-mA
25-2.712mA
,
Full-3-mA
25-1350µA
Full-15-µΑ
25-15038150mV
Full-58-mV
LOGIC INPUT
Input Leakage Current, I
I
, IHD, I
MIX
HO
Input Leakage Current, I
I
, IHD, I
MIX
V
V
INH
INL
HO
SD
SD
VDD = 3.6V , SD = 0V, INS = 0V, MIX = 0V, HD = 0V ,
INS
HO = 0V
, I
,
VDD = 3.6V, SD = VDD, INS = VDD, MIX = VDD,
INS
HD = V
, HO = VDD,
DD
25-1.9-µA
Full-1.9-µA
25-0.02-µA
Full-0.02-µA
Full1.4--V
Full--0.4V
, I
,
NOTES:
= input voltage to perform proper function.
3. V
IN
4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.
P-P
P-P
6
FN6514.1
June 27, 2007
ISL54003, ISL54005, ISL54006
ISL54003 Typical Application Circuit and Block Diagram
RIGHT AUDIO
LEFT AUDIO
0.22µF
0.22µF
IN
R
ROUTER/
IN
L
MIXER
V
BTL
SE
0.1µF
DD
SPK+
SPK-
100kΩ
HpR
HD
THERMAL
PROTECTION
MICRO
CONTROLLER
CLICK AND POP
SD
HO
LOGIC CONTROL
ISL54005 Typical Application Circuit and Block Diagram
RIGHT 1 AUDIO
RIGHT 2 AUDIO
LEFT 1 AUDIO
0.22µF
0.22µF
0.22µF
IN
1R
IN
2R
MUX/
IN
1L
ROUTER/
MIXER
SE
BIAS
GND
V
BTL
SE
DD
HpL
V
DD
REF
0.1µF
SPK+
SPK-
HpR
HD
C
1µF
REF
10k
100kΩ
HEADPHONE JACK
Ω
LEFT 2 AUDIO
CONTROLLER
MICRO
0.22µF
7
IN
2L
CLICK AND POP
SD
INS
HO
PROTECTION
LOGIC CONTROL
THERMAL
SE
BIAS
GND
V
HpL
DD
REF
C
1µF
REF
10k
Ω
HEADPHONE JACK
FN6514.1
June 27, 2007
ISL54003, ISL54005, ISL54006
ISL54006 Typical Application Circuit and Block Diagram
0.1µF
RIGHT 1 AUDIO
RIGHT 2 AUDIO
LEFT 1 AUDIO
LEFT 2 AUDIO
CONTROLLER
MICRO
0.22µF
0.22µF
0.22µF
0.22µF
IN
1R
IN
2R
IN
1L
IN
2L
CLICK AND POP
SD
INS
MIX
HO
MUX/
ROUTER/
MIXER
PROTECTION
LOGIC CONTROL
THERMAL
V
BTL
SE
SE
BIAS
GND
DD
SPK+
SPK-
HpR
HD
HpL
V
DD
REF
C
1µF
REF
100kΩ
10k
Ω
HEADPHONE JACK
Detailed Description
The Intersil ISL54003, ISL54005, and ISL54006 family of
devices are integrated audio power amplifier systems
designed to provide quality audio, while requiring minimal
external components. The low 0.4% THD+N ensures clean,
low distortion amplification of the audio signals. The devices
are designed to operate from a single +2.7V to +5V power
supply . All devices are of fered in a 20 Ld 4x4 TQFN package.
Targeted applications include battery powered equipment
such as cell-phones, MP3 players, and games/toys.
These parts contain one class AB BTL type p ower amplifier
for driving an 8Ω mono speaker and two class AB singleended (SE) type amplifiers for driving 16Ω or 32Ω
headphones.
The BTL when using a 5V supply is capable of delivering
800mW (typ) with 0.4% THD+N and 941mW (typ) with 1%
THD+N of continuous average power into an 8Ω BTL speaker
load. When the speaker load is connected across the
positive and negative terminals of the BTL driver the voltage
is doubled across the load and the power is quadrupled.
Each SE amplifier when using a 5V supply is capable of
delivering 50mW (typ) with 0.3% THD+N and 94mW (typ) with
1% THD+N of continuous average power into a 32Ω
headphone speaker .
When in Mono Mode (BTL driver active) these devices
automatically mix the active left and right audio inputs and
send the combined signal to the BTL driver. In Head phone
Mode the active right channel input is sent to the right
headphone speaker and the active left channel is sent to the
left headphone speaker.
The ISL54005 and ISL54006 feature a 2:1 stereo input
multiplexer front-end. This allows selection between two
stereo sources. The INS control pin determines which stereo
input is active. Applying logic “0” to the INS control pin
selects stereo input 1 (R1 and L1). Applying logic “1” to the
INS control pin selects stereo input 2 (R2 and L2).
The ISL54006 has the capablity of mixing the two stereo
inputs. When in MIX Mode and HEADPHONE Mode, the
part mixes the R1 input with the R2 input and sends the
combined signal to the HpR headphone driver and it mixes
the L1 input with the L2 input and sends the combined signal
to the HpL headphone driver. When in MIX Mode and
MONO Mode, it mixes all four inputs (R1 + R2 + L1 + L2)
and sends the combined signal to the BTL mono driver.
These parts have headphone sense input circuitry that
detects when a headphone jack has been inserted and
automatically switches the active audio inputs from the mono
BTL output driver to the headphone drivers. These parts also
feature a logic control pin (HO) that can override the sense
input circuitry.
8
FN6514.1
June 27, 2007
ISL54003, ISL54005, ISL54006
All devices in this family feature low power shutdown,
thermal overload protection and click/pop suppression. The
click and pop circuitry prohibits switching between input
channels until the audio input signals are at there lowest
point which eliminates audible transients in the speakers
when changing the audio input sources. The click/pop
circuitry also keeps speaker transients to an inaudibile level
when entering and leaving shutdown.
Typical application circuits and block diagrams for each
device in the family are provided on page 7 and page 8.
Truth tables for each device are provided on page 3.
DC Bias Voltage
The ISL54003, ISL54005, and ISL54006 have internal DC
bias circuitry, which DC offsets the incoming audio signal at
V
2. When using a 5V supply, the DC offset will be 2.5V.
DD/
When using a 3.6V supply, the DC offset will be 1.8V.
Since the signal gets biased internally at V
signals need to be AC coupled to the inputs of the device.
The value of the AC coupling capacitor depends on the low
frequency range required for the application. A capacitor of
0.22µF will pass a signal as low as 7.2Hz. The formula
required to calculated the capacitor value is:
C 1 6.28 f 100kΩ••⁄≥
The 100k
Ω is the impedance looking into the input of the
ISL54003, ISL54004, ISL54006 devices.
/2 the audio
DD
(EQ. 1)
Headphone (Single-Ended) Amplifiers
The ISL54003, ISL54005, and ISL54006 contains two
single-ended (SE) headphone amplifiers for driving the left
and right channels of a 32Ω or 16Ω headphone speaker.
One SE amplifier drives the right speaker of the headphone
and other SE amplifier drives the left speaker of the
headphone. The speaker load gets connected between the
output of the amplifier and ground.
The audio signal at the output of each SE driver is biased at
V
/2 and unlike the BTL driver that cancels this offset due
DD
to its differential connection, a capacitor is required at the
output of each SE driver to remove this DC voltage from the
headphone load.
This coupling capacitor along with the resistance of the
speaker load creates a high pass filter that sets the
amplifier’s lower bandpass frequency limit. The value of this
AC coupling capacitor depends on the low frequency range
required by the application. The formula required to calculate
the capacitor value is:
C 1 6.28 f Rspeaker••⁄≥
For an application driving a 32
Ω headphone with a lower
frequency requirement of 150Hz, the required capacitor
value would be :
C 1 6.28 150 32 33μF=••⁄≥
(EQ. 2)
(EQ. 3)
BTL Speaker Amplifier
The ISL54003, ISL54005, and ISL54006 contain one bridgetied load (BTL) amplifier designed to drive an 8Ω speaker
load differentially. The output to the BTL amplifier are SPK+
and SPK-. The speaker load gets connected across these
terminals.
A single BTL driver consists of an inverting and non-inverting
power op amps. The AC signal out of each op amp are equal
in magnitude but 180° out of phase, so the AC signal at
SPK+ and SPK- have the same amplitude but are 180° out
of phase.
Driving the load differentially using a BTL configuration
doubles the output voltage across the speaker load and
quadruples the power to the load. In effect you get a gain of
two due to this configuration at the load as compared to
driving the load with a single-ended amplifier with its load
connected between a single amplifier’s output and ground.
The outputs of the BTL are biased at V
gets connected across the + and - terminal of the BTL the
mid supply DC bias voltage at each output gets cancelled
out eliminating the need for large bulky output coupling
capacitors.
/2. When the load
DD
Use the closest standard value.
Headphone Sense Function
With a logic “1” at the HP control pin while the HO control pin
is low will activate the headphone drivers and disable the
BTL driver.
The application block diagrams on page 7 and page 8 show
the implementation of the headphone control function using
a common headphone jack.
The HP pin gets connected to the mechanical wiper blade of
the headphone jack. Two external resistors are required for
proper operation. A 100kΩ pull-up resistor from the HP pin to
V
and a 10kΩ pull-down resistor from the jack’s audio
DD
signal pin to ground of the jack signal pin to which the wiper
is connected. See the block diagrams on page 7 and page 8.
When no headphone plug is inserted into the jack, the
voltage at the HP pin gets set at a low voltage level due to
the 10kΩ resistor and 100kΩ resistor divider network
connection to V
When a headphone is inserted into the jack, the 10kΩ
resistor gets disconnected from the HP control pin and the
HP pin gets pulled up to V
the headphone drivers are activated.
DD
.
. Since the HP pin is now high,
DD
9
FN6514.1
June 27, 2007
ISL54003, ISL54005, ISL54006
A microprocessor or a switch can be used to drive the HP
pin rather than using the headphone jack contact pin.
Note: With a logic “1” at the HO pin, the BTL driver remains
active regardless of the voltage level at the HD pin. This
allows a headphone to be plugged into the headphone jack
without activating the HP drivers. Music will continue to play
through the internal 8Ω speaker rather than headphones.
Low Power Shutdown
With a logic “1” at the SD control pin the device enters the
low power shutdown state. When in shutdown the BTL and
headphone amplifiers go into an high impedance state and
I
supply current is reduced to 26µA (typ).
DD
In shutdown mode before the amplifiers enter the high
impedance/low current drive state, the bias voltage of V
remains connected at the output of the amplifiers through a
100kΩ resistor.
This resistor is not present during active operation of the
drivers but gets switch in when the SD pin goes high. It gets
removed when the SD pin goes low.
Leaving the DC bias voltage connected through a 100kΩ
resistor while going into and out of shutdown reduces the
transient at the speakers to a small level preventing clicking
or popping in the speakers.
Note: When the SD pin is High it over-rides all other logic
pins.
DD
/2
QFN Thermal Pad Considerations
The QFN package features an exposed thermal pad on its
underside. This pad lowers the package’s thermal resistance
by providing a direct heat conduction path from the die to the
PCB. Connect the exposed thermal pad to GND by using a
large copper pad and multiple vias to the GND plane. The
vias should be plugged and tented with plating and solder
mask to ensure good thermal conductivity.
Best thermal performance is achieved with the largest
practical copper ground plane area.
PCB Layout Considersations and Power
Supply Bypassing
To maintain the highest load dissipation and widest output
voltage swing, the power supply PCB traces and the traces
that connect the output of the drivers to the speaker loads
should be made as wide as possible to minimize losses due
to parasitic trace resistance.
Proper supply bypassing is necessary for high power supply
rejection and low noise performance. A filter network
consisting of a 10µF capacitor in parallel with a 0.1µF
capacitor is recommended at the voltage regulator that is
providing the power to the ISL54003, ISL54004, ISL54006
IC.
Local bypass capacitors of 0.1µF should be put at each VDD
pin of the ISL54003, ISL54004, ISL54006 devices. They
should be located as close as possible to the pin, keeping
the length of leads and traces as short as possible.
Typical Performance Curves T
1
0.9
VDD = 5V
0.8
BTL
0.7
0.6
0.5
0.4
0.3
THD+N (%)
0.2
0.1
= 8Ω
R
L
PO = 800mW
2020k50100 2005001k2k5k10k
FREQUENCY (Hz)
FIGURE 1. THD+N vs FREQUENCYFIGURE 2. THD+N vs FREQUENCY
A 1µF capacitor from the REF pin (pin 10) to ground is
needed for optimum PSRR and internal bias voltage stability.
= +25°C, Unless Otherwise Specified.
A
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
THD+N (%)
0.2
0.1
2020k50100 2005001k2k5k10k
VDD = 3.6V
BTL
R
= 8Ω
L
= 200mW
P
O
FREQUENCY (Hz)
10
FN6514.1
June 27, 2007
ISL54003, ISL54005, ISL54006
Typical Performance Curves T
10
VDD = 5V
5
BTL
R
= 8Ω
L
2
f = 1kHz
1
0.50
0.20
THD+N (%)
0.10
0.05
0.02
0.01
10m120m50m100m200m500m
OUTPUT POWER (W)
FIGURE 3. THD+N vs OUTPUT POWERFIGURE 4. THD+N vs OUTPUT POWER
1
0.9
VDD = 5V
0.8
SE
0.7
0.6
0.5
0.4
= 32Ω
R
L
P
= 50mW
O
= +25°C, Unless Otherwise Specified. (Continued)
A
10
VDD = 3.6V
5
BTL
R
= 8Ω
L
2
f = 1kHz
1
0.50
0.20
THD+N (%)
0.10
0.05
0.02
0.01
10m600m20m40m70m 100m200m
1
0.9
0.8
0.7
0.6
0.5
0.4
VDD = 5V
SE
= 16Ω
R
L
= 50mW
P
O
OUTPUT POWER (W)
0.3
THD+N (%)
0.2
0.1
2020k50100 200500 1k2k5k10k
FREQUENCY (Hz)
FIGURE 5. THD+N vs FREQUENCYFIGURE 6. THD+N vs FREQUENCY
1
VDD = 3.6V
0.50
0.20
0.10
THD+N (%)
0.05
0.02
SE
R
= 32Ω
L
P
= 30mW
O
0.3
THD+N (%)
0.2
0.1
2020k50100 2005001k2k5k10k
FREQUENCY (Hz)
1
VDD = 3.6V
0.50
0.20
0.10
THD+N (%)
0.05
0.02
SE
= 16Ω
R
L
P
= 60mW
O
0.01
2020k50100 200500 1k2k5k10k
FREQUENCY (Hz)
FIGURE 7. THD+N vs FREQUENCYFIGURE 8. THD+N vs FREQUENCY
11
0.01
2020k50100 2005001k2k5k10k
FREQUENCY (Hz)
FN6514.1
June 27, 2007
ISL54003, ISL54005, ISL54006
Typical Performance Curves T
10
5
2
1
0.50
0.20
THD+N (%)
0.10
0.05
0.02
0.01
10m100m20m30m40m 50m70m
0.50
VDD = 5V
SE
= 32Ω
R
L
f = 1kHz
OUTPUT POWER (W)
FIGURE 9. THD+N vs OUTPUT POWERFIGURE 10. THD+N vs OUTPUT POWER
10
5
2
1
VDD = 3.6V
SE
= 32Ω
R
L
f = 1kHz
= +25°C, Unless Otherwise Specified. (Continued)
A
10
5
2
1
0.50
0.20
THD+N (%)
0.10
0.05
0.02
0.01
10m200m20m30m50m 70m 100m
10
5
2
1
0.50
VDD = 5V
SE
RL = 16Ω
f = 1kHz
VDD = 3.6V
SE
R
= 16Ω
L
f = 1kHz
OUTPUT POWER (W)
0.20
THD+N (%)
0.10
0.05
0.02
0.01
10m55m12m15m20m25m35m45m
OUTPUT POWER (W)
0.20
THD+N (%)
0.01
0.05
0.02
0.01
10m100m20m30m40m 50m70m
OUTPUT POWER (W)
FIGURE 11. THD+N vs OUTPUT POWERFIGURE 12. THD+N vs OUTPUT POWER
-50
VDD = 5V
= 15mW
P
O
INxR TO HPL
INxL TO HPR
2020k50100 200500 1k2k5k10k
FREQUENCY (Hz)
CROSSTALK (dB)
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-60
VDD = 5V
-65
-70
-75
-80
-85
-90
-95
-100
OFF ISOLATION (dB)
-105
-110
-115
-120
2020k50 100 200500 1k2k5k 10k
FREQUENCY (Hz)
HPR AND HPL
BTL
FIGURE 13. CROSSTALK vs FREQUENCYFIGURE 14. OFF ISOLATION vs FREQUENCY
12
FN6514.1
June 27, 2007
ISL54003, ISL54005, ISL54006
Typical Performance Curves T
-22
-26
-30
-34
-38
-42
-46
-50
PSRR (dB)
-54
-58
-62
-66
-70
VDD = 5V
BTL
V
= 200mV
RIPPLE
1020k2050 100 200500 1k2k5k 10k
P-P
FREQUENCY (Hz)
FIGURE 15. PSRR vs FREQUENCYFIGURE 16. PSRR vs FREQUENCY
700
600
= +25°C, Unless Otherwise Specified. (Continued)
A
-20
-25
VDD = 5V
SE
-30
V
= 200mV
RIPPLE
-35
-40
-45
-50
-55
-60
PSRR (dB)
-65
-70
-75
-80
-85
-90
1020k2050 100 200500 1k2k5k 10k
400
350
P-P
HPR
HPL
FREQUENCY (Hz)
500
400
300
200
POWER DISSIPATION (mW)
100
0
02505007501000
P
(mW)
OUT
VDD = 5V
BTL
R
= 8Ω
L
300
250
200
150
100
POWER DISSIPATION (mW)
50
0
0100200300400
(mW)
P
OUT
FIGURE 17. POWER DISSIPATION vs OUTPUT POWERFIGURE 18. POWER DISSIPATION vs OUTPUT POWER
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220WGGD-1 ISSUE I)
MILLIMETERS
SYMBOL
A0.700.750.80-
A1-0.020.05-
A2-0.550.809
A30.20 REF9
b0.180.250.305, 8
D4.00 BSC-
D13.75 BSC9
D21.952.102.257, 8
E4.00 BSC-
E13.75 BSC9
E21.952.102.257, 8
e 0.50 BSC-
k0.20 -- -
L0.350.600.758
N202
Nd53
Ne53
P- -0.609
θ--129
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
NOTESMINNOMINALMAX
Rev. 0 11/04
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6514.1
June 27, 2007
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