intersil ISL54004 DATA SHEET

®

ISL54004

Data Sheet June 27, 2007

Integrated Audio Amplifier Systems

The Intersil ISL54004 device is an integrated audio power
amplifier system that combines a mono BTL amplifier and
stereo headphone amplifiers in a single device. It can ope rate
from a single +2.7V to +5V power supply and is offered in a
20 Ld 4x4 TQFN package. Targeted applications include
handheld equipment such as cell-phones, MP3 players, and
games/toys.

The ISL54004 part contains one class AB BTL type power
amplifier for driving an 8Ω mono speaker and two class AB
headphone amplifiers for driving 16Ω or 32Ω headphone
speakers.

The BTL when using a 5V supply is capable of delivering
800mW (typ) with 0.4% THD+N and 941mW (typ) with 1%
THD+N of continuous average power into an 8Ω BTL speaker
load.

Each headphone amplifier when using a 5V supply is capable
of delivering 50mW (typ) with 0.3% THD+N and 94mW (typ)
with 1% THD+N of continuous average power into a 32Ω
headphone speaker.

When in Mono mode the part automatically mixes the left and
right audio inputs and sends the combined signal to the BTL
driver. In Headphone Mode, the active right channel inp ut is
sent to the right headphone speaker and the active lef t
channel is sent to the left headphone speaker.

The ISL54004 has a four-level programmable gain stage to
boost the audio signal. The part requires no external gain
setting resistors.

The ISL54004 part features headphone sense input circuitry
that detects when a headphone jack has been inserted and
automatically switches the audio inputs from the mono BTL
output driver to the headphone drivers. The part also has a
logic control pin that can override the headphone sense
input circuitry.

FN6513.1

Features

• Class AB 94mW Headphone Amplifiers and 941mW Mono
BTL Speaker Amplifier

• THD+N at 1kHz, 800mW into 8Ω BTL . . . . . . . . . . . . . .0.4%

• THD+N at 1kHz, 50mW into 32Ω Headphone . . . . . . . .0.3%

• Single Supply Operation . . . . . . . . . . . . . . . . .+2.7V to +5.5V

• Headphone Sense Input

• Low Power Shutdown

• Thermal Shutdown Protection

• “Click and Pop” Suppression Circuitry

• Selectable Gain Settings

• TTL Logic-Compatible

• Available in 20 Ld 4x4 TQFN

• Pb-Free Plus Anneal (RoHS Compliant)

Applications

• Battery powered, Handheld, and Portable Equipment

- Cellular/mobile Phones

- PDA’s, MP3 Players, DVD Players, Cameras

- Laptops, Notebooks, Palmtops

- Handheld Games and Toys

• Desktop Computers

Simplified Block Diagram

V

DD

R

L

GAIN

ROUTER/

SWITCHER

The part also features low power shutdown, thermal
overload protection and click and pop suppression. The click
and pop circuitry prevents click and pops at the speakers
when transitioning in and out of shutdown.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

CLICK

AND
POP

SD
GS0
GS1

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

LOGIC

CONTROL

HO

ISL54004

Copyright Intersil Americas Inc. 2007. All Rights Reserved

BIAS

THERMAL

SHUTDOWN

ISL54004

Pinout

ISL54004

(20 LD 4X4 TQFN)

TOP VIEW

SPK-

SPK+

VDD

GND

HpR

GND

20 19 18 17 16

1

2

3

4

5

678910

VDD

HpL

GS1

HD

INRNCGSO

REF

GND

HO

15

SD

14

NC

13

VDD

12

INL

11

Ordering Information

TEMP.

PART

NUMBER

PART

MARKING

RANGE

(°C) PACKAGE

ISL54004IR* 540 04IR -40 to +85 20 Ld 4x4 TQFN L20.4x4A
ISL54004IRTZ*

(Note)

540 04IRTZ -40 to +85 20 Ld 4x4 TQFN

Tape and Reel
(Pb-free)

*Add “-T” suffix for tape and reel
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.

PKG.

DWG. #

L20.4x4A

Pin Descriptions

PIN NAME FUNCTION

3, 6, 12 VDD System Power Supply
4, 9, 20 GND Ground Connection

11 IN1L Left Channel Audio Input 1
17 IN1R Right Channel Audio Input 1

5 HpR Headphone Right Ouput
7 HpL Headphone Left Ouput
2 SPK+ Positive Speaker Output
1 SPK- Negative Speaker Output

14 SD Shutdown, High to disable amplifiers, Low

for normal operation.

8 HD Headphone Detection, Internally pulled up to

V

Low in Mono Mode, High in

DD,

Headphone Mode if HO = Low

15 HO Headphone Override, High in Mono Mode,

Low in Headphone Mode if HD = High

16, 18 GS_ Gain Select

10 REF Common-mode Bias V oltage, By-pass with a

1µF capacitor to GND.

ISL54004 Truth Table

SD GS1 GS0 HD HO SPK+/SPK- HpR HpL

1 X X X X Disabled Disabled Disabled
00 00X IN
00 010 - INRIN
00 011 INR + IN
00 10X1.2 x (IN
00 110 - 1.2 x INR1.2 x IN
00 1111.2 x (INR + INL)- ­01 00X2 x (IN
01 010 - 2 x IN
01 0112 x (INR + INL)- ­01 10X4 x (IN
01 110 - 4 x IN
01 1114 x (INR + INL)- -

+ IN

R

L

L

+ INL)- -

R

+ INL)- -

R

+ INL)- -

R

--

--

2 x IN

R

4 x IN

R

L

L

L

L

2

FN6513.1

June 27, 2007

ISL54004

Absolute Maximum Ratings Thermal Information

VDD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V

Input Voltages

InR, InL, SD, H_, G_. . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)

Output Voltages

SPK+, SPK-, Hp_ . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)

Continuous Current (VDD, SPK_, Hp_, GND) . . . . . . . . . . . 750mA

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200kV

Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1kV

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and
result in failures not covered by warranty.

NOTE:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

JA

Tech Brief TB379.

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance (Typical, Note 1, 2) θ

(°C/W) θJC (°C/W)

JA

20 Ld 4x4 TQFN Package . . . . . . . . . . 45 6.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Electrical Specifications - 5V Supply Test Conditions: V

C

= 1µF, R

REF

GND for SE drivers, Unless Otherwise Specified (Note 3).

PARAMETER TEST CONDITIONS

= +5V, GND = 0V, V

DD

is terminated between SPK+ and SPK- for BTL driver and between Hp_ and

L

= 2.4V, V

INH

TEMP

(°C)

(Notes 4, 5) TYP

= 0.8V, SD = GSO = GS1 = V

INL

MIN

MAX

(Notes 4, 5) UNITS

GENERAL

Power Supply Range, V

DD

Quiescent Supply Current, I

Shutdown Supply Current, I

Input Resistance, R
Thermal Shutdown, T

IN

SD

DD

SD

HO = V
R

L

HO = V
coupled to GND (0.1μF)

SD = V
(BTL) and R

or V

INL

= 32Ω (SE), Inputs AC coupled to GND (0.1μF)

INL

INH

, HD = V

INH

or V

, HD = V

INH

, HO = V

INL

= 32Ω (SE), Inputs AC coupled to GND

L

, RL = 8Ω (BTL) and

INL

, RL = None, Inputs AC

INL

or V

, HD = V

INH

, RL = 8Ω

INL

(0.1μF)
INS = 0V or V
INS = MIX = 0V or V

DD

DD

Full 2.7 - 5.5 V

25 - 4.7 50 mA

Full - 10 - mA

25 - 4.6 12 mA

Full - 5.5 - mA

25 - 28 50 mA

Full - 31 - mA

25 - 100 - kΩ

25 - 150 - °C
Thermal Shutdown Hysteresis 25 - 10 - °C
SD to Full Operation, t

SD(ON)

Gain Selection Range Input referred minimum gain

GS0 = GS1 = V

INL, RL

= 32Ω

Input referred maximum gain
GS0 = GS1 = V

INH, RL

= 32Ω

Input referred minimum gain
GS0 = GS1 = V

INL, RL

= 8Ω

Input referred maximum gain
GS0 = GS1 = V

INH, RL

= 8Ω

SE Amplifiers
HD = V

INH

HO = V

INL

BTL Amplifier
HD = V

INH

HO = V

INH

Full - 1 - ms

25 -0.4 0 0.6 dB

25 11.4 12 12.6 dB

25 5.2 6 6.6 dB

25 17.2 18 18.6 dB

INL

,

3

FN6513.1

June 27, 2007

ISL54004

Electrical Specifications - 5V Supply Test Conditions: V

C

= 1µF, R

PARAMETER TEST CONDITIONS

BTL AMPLIFIER DRIVER, HD = V

Output Offset Voltage, V

OS

HO = V

INH,

Measured between SPK+ and SPK-, Inputs AC
coupled to GND (0.1μF)

Power Supply Rejection Ratio, PSRR V

Output Power, P

OUT

Total Harmonic Distortion + Noise,
THD+N

Max Output Voltage S wing, V

OUT

HD = V
coupled to GND (0.1μF)

RL = 8Ω, THD+N = 1%, f = 1kHz 25 - 941 - mW
R
R
R
RL = 8Ω, V

= 200MV

RIPPLE

INL

= 8Ω, THD+N = 10%, f = 1kHz 25 - 1.23 - W

L

= 8Ω, P

L

= 8Ω, P

L

Signal to Noise Ratio, SNR RL = 8Ω, P
Output Noise, N
Crosstalk

R

to LCH, LCH to R

CH

OUT

CH

A - Weight filter, BW = 22Hz to 22kHz 25 - 140 - mV
RL = 8Ω, P

from the input of active amplifier to the output of an
adjacent amplifier with its input AC coupled to GND.

Off-Isolation SD = V

DD, POUT

from input to output of a disabled amplifier.

SINGLE ENDED AMPLIFIER DRIVERS, HD = V

Power Supply Rejection Ratio, PSRR V

HD = 0V, R

RIPPLE

= 200MV

coupled to GND (0.1μF)

Output Power, P

OUT

Total Harmonic Distortion + Noise,
THD+N

Max Output Voltage S wing, V

OUT

Crosstalk
R

to LCH, LCH to R

CH

CH

Off-Isolation SD = V
Signal to Noise Ratio, SNR R
Channel Gain Matching

R

to L

CH

CH

Channel Phase Matching
R

to L

CH

CH

RL = 16Ω, THD+N = 1%, f = 1kHz 25 - 170 - mW

= 32Ω, THD+N = 1%, f = 1kHz 25 - 94 - mW

R

L

= 16Ω, THD+N = 10%, f = 1kHz 25 - 215 - mW

R

L

= 32Ω, THD+N = 10%, f = 1kHz 25 - 116 - mW

R

L

= 32Ω, P

R

L

= 32Ω, P

R

L

RL = 32Ω, V
RL = 32Ω, P

DD, RL

= 32Ω, P

L

RL = 32Ω, VINR = VINL = 1.3V
same source)

RL = 32Ω, VINR = VINL = 1.3V
same source)

LOGIC INPUT

Input Leakage Current, I
I

GSx, IHO

Input Leakage Current, I
I

, I

HD

HO

V

INH

V

INL

SD

SD

, IHD,

, I

GSx

VDD = 5V, SD = 0V, INS = 0V, GSx = 0V, HD = 0V,
HO = 0V

,

VDD = 5V, SD = VDD, INS = VDD, GSx = VDD,
HD = V

DD

REF

GND for SE drivers, Unless Otherwise Specified (Note 3). (Continued)

UNLESS OTHERWISE SPECIFIED

INH,

P-P

, RL = 8Ω, Inputs AC

= 800mW, f = 1kHz 25 - 0.4 - %

OUT

= 800mW, f = 20Hz to 20kHz 25 - 0.7 - %

OUT

= 5V

SIGNAL

= 900mW, f = 1kHz 25 - 85 - dB

OUT

= 800mW, f = 1kHz, Signal coupled

OUT

= 800mW, f = 10kHz, Signal coupled

HO = V

INH,

P-P

= 32Ω, Input AC

L

= 50mW, f = 1kHz 25 - 0.3 - %

OUT

= 50mW, f = 20Hz to 20kHz 25 - 0.4 - %

OUT

= 5V

SIGNAL

= 15mW, f = 1kHz 25 - 75 - dB

OUT

= 32W, P

= 50mW, f = 1kHz 25 - 83 - dB

OUT

, HO = V

DD

L

,

, f = 1kHz 25 7.2 7.7 - V

P-P

UNLESS OTHERWISE SPECIFIED

INL,

,

, f = 1kHz 25 3.6 4.7 - V

P-P

= 15mW, f = 10kHz 25 - 95 - dB

OUT

= +5V, GND = 0V, V

DD

= 2.4V, V

INH

= 0.8V, SD = GSO = GS1 = V

INL

INL

is terminated between SPK+ and SPK- for BTL driver and between Hp_ and

TEMP

(°C)

MIN

(Notes 4, 5) TYP

MAX

(Notes 4, 5) UNITS

25 -150 45 150 mV

Full - 49 - mV
F
F

= 217Hz 25 - 49 - dB

RIPPLE

= 1kHz 25 - 47 - dB

RIPPLE

P-P

RMS

25 - 80 - dB

25 - 110 - dB

F
F

RMS

RMS

= 217Hz 25 - 48 - dB

RIPPLE

= 1kHz 25 - 47 - dB

RIPPLE

(Connect to the

(Connect to the

25 - ±0.2 - dB

25 - 1.3 - °

P-P

25 -3 1.9 3 µA

Full - 1.9 - µA

25 -1 0.02 1 µA
Full - 0.02 - µA
Full 2.4 - - V
Full - - 0.8 V

,

4

FN6513.1

June 27, 2007

ISL54004

Electrical Specifications - 3.6V Supply Test Conditions: V

Cref = 1µF, R
GND for SE drivers, Unless Otherwise Specified (Note 3)

PARAMETER TEST CONDITIONS

= +3.6V , GND = 0V, V

DD

is terminated between SPK+ and SPK- for BTL driver and between Hp_ and

L

= 1.4V . V

INH

TEMP

(°C)

(Notes 4, 5) TYP

= 0.4V , SD = GSO = GS1 = V

INL

MIN

MAX

(Notes 4, 5) UNITS

GENERAL

Quiescent Supply Current, I

Shutdown Supply Current, I

DD

SD

BTL AMPLIFIER DRIVER, HD = V

Output Offset Voltage, V

OS

Power Supply Rejection Ratio, PSRR V

Output Power, P

OUT

Total Harmonic Distortion + Noise,
THD+N

Max Output Volt a ge S wing, V

OUT

SINGLE ENDED AMPLIFIER DRIVERS, HD = V

Power Supply Rejection Ratio, PSRR V

Output Power, P

OUT

Total Harmonic Distortion + Noise,
THD+N

Max Output Volt a ge S wing, V

OUT

HO = V
R

L

HO = V
coupled to GND (0.1μF)

SD = V
(BTL) and R
(0.1μF)

HO = V

INH,

Measured between SPK+ and SPK-, Input AC
coupled to GND (0.1μF)

RIPPLE

HD = 0V, R
coupled to GND (0.1μF)

or V

INL

= 32Ω (SE), Input AC coupled to GND (0.1μF)

INL

INH

INH,

= 200mV

, HD = V

INH

or V

, HD = V

INH

, HO = V

INL

= 32Ω (SE), Input AC coupled to GND

L

UNLESS OTHERWISE SPECIFIED

P-P

= 8Ω, Input AC

L

, RL = 8Ω (BTL) and

INL

, RL = None, Input AC

INL

or V

, HD = V

INH

F

RIPPLE

F

RIPPLE

, RL = 8Ω

INL

= 217Hz 25 - 49 - dB
= 1kHz 25 - 47 - dB

25 - 4 50 mA

Full - 10 - mA

25 - 2.7 12 mA

Full - 3 - mA

25 - 13 50 mA

Full - 15 - mA

25 -150 38 150 mV

Full - 58 - mV

RL = 8Ω, THD+N = 1%, f = 1kHz 25 - 310 - mW

= 8Ω, THD+N =10%, f = 1kHz 25 - 528 - mW

R

L

= 8Ω, P

R

L

= 8Ω, P

R

L

RL = 8Ω, V

RIPPLE

HD = 0V, R
coupled to GND (0.1μF)

= 200mW, f = 1kHz 25 - 0.4 - %

OUT

= 200mW, f = 20Hz to 20kHz 25 - 0.4 - %

OUT

= 3.6V

SIGNAL

HO = V

INH,

= 200MV

P-P

= 32Ω, Input AC

L

, f = 1kHz 25 - 5.8 - V

P-P

UNLESS OTHERWISE SPECIFIED

INL,

,

F

RIPPLE

F

RIPPLE

= 217Hz 25 - 48 - dB
= 1kHz 25 - 47 - dB

RL = 16Ω, THD+N =1%, f = 1kHz 25 - 80 - mW

= 32Ω, THD+N =1%, f = 1kHz 25 - 47 - mW

R

L

R

= 16Ω, THD+N = 10%, f = 1kHz 25 - 107 - mW

L

R

= 32Ω, THD+N = 10%, f =1kHz 25 - 58 - mW

L

= 32Ω, P

R

L

R

= 32Ω, P

L

RL = 32Ω, V

= 30mW, f = 1kHz 25 - 0.2 - %

OUT

= 30mW, f = 20Hz to 20kHz 25 - 0.3 - %

OUT
SIGNAL

= 3.6V

, f = 1kHz 25 - 3.2 - V

P-P

LOGIC INPUT

Input Leakage Current, I
I

, I

HD

HO

Input Leakage Current, I
I

, I

HD

HO

V

INH

V

INL

SD

SD

, I

,

GSx

VDD = 3.6V, SD = 0V, GSx = 0V, HD = 0V , HO = 0V, 25 - 1.9 - µA

Full - 1.9 - µA

, I

,

GSx

VDD = 3.6V, SD = VDD, GSx = VDD, HD = VDD,
HO = V

DD

25 - 0.02 - µA
Full - 0.02 - µA
Full 1.4 - - V
Full - - 0.4 V

NOTES:

= input voltage to perform proper function.

3. V

IN

4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

5. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested

INL

P-P

P-P

,

5

FN6513.1

June 27, 2007

ISL54004

ISL54004 Typical Application Circuit and Block Diagram

RIGHT AUDIO

0.22µF

0.22µF

LEFT AUDIO

IN

R

GAIN

IN

L

ROUTER/

SWITCHER

V

BTL

SE

0.1µF

DD

SPK+

SPK-

100kΩ

HpR

HD

CLICK

AND
POP

SD

MICRO

CONTROLLER

HO
GSO
GS1

LOGIC CONTROL

Detailed Description

The Intersil ISL54004 device is an integrated audio power
amplifier systems designed to provide quality audio, while
requiring minimal external components. Low 0.4% THD+N
ensures clean, low distortion amplification of the audio
signals. It is designed to operate from a single +2.7V to +5V
power supply. It is offered in a 20 Ld 4x4 TQFN package.
Targeted applications include battery powered equipment
such as cell-phones, MP3 players, and games/toys.

The ISL54004 part contains one class AB BTL type power
amplifier for driving an 8Ω mono speaker and two class AB
single-ended (SE) type amplifiers for driving 16Ω or 32Ω
headphones.

The BTL when using a 5V supply is capable of delivering
800mW (typ) with 0.4% THD+N and 941mW (typ) with 1%
THD+N of continuous average power into a stereo 8Ω BTL
speaker load. When the speaker load is connected across
the positive and negative terminals of the BTL driver the
voltage is doubled across the load and the power is
quadrupled.

Each SE amplifier when using a 5V supply is capable of
delivering 50mW (typ) with 0.3% THD+N and 94mW (typ) with
1% THD+N of continuous average power into a 32Ω
headphone speaker .

When in Mono Mode (BTL driver active) the part automatically
mixes the left and right audio inputs and sends the combined

V

HpL

DD

REF

C

1µF

HEADPHONE JACK

10kΩ

REF

THERMAL

PROTECTION

SE

BIAS

GND

signal to the BTL driver. In Head phone Mode the right channel
input is sent to the right headphone speaker and the left
channel is sent to the left headphone speaker.

The ISL54004 features headphone sense input circuitry that
detects when a headphone jack has been inserted and
automatically switches the audio inputs from the mono BTL
output driver to the headphone drivers. It also has a logic
control pin (HO) that can override the sense input circuitry.

The ISL54004 has a four-level programmable gain stage to
boost the audio signal. The part requires no external gain
setting resistors. When GSO = GS1 = Low a driver will have a
gain of 1V/V (0dB). When GSO = High, GS1 = Low a driver
will have a gain of 1.2V/V (1.5dB). When GSO = Low ,
GS1 = High a driver will have a gain of 2V/V (6dB). When
GSO = High, GS1 = High a driver will have a gain of 4V/V
(12dB). When the speaker is connected across the SPK+
terminal and SPK- terminal of the mono BTL driver you get an
additional gain of 2V/V (6dB) due to the BTL configuration.
The overall gain will be 2 times the values discussed above.
For example with GS1 = GS0 = High the overall gain will be
2 x 4 = 8V/V (18dB).

The part features low power shutdown, thermal overload
protection and click and pop suppression. The click and pop
circuitry prevents click and pops at the speakers when
transitioning in and out of shutdown.

6

FN6513.1

June 27, 2007

ISL54004

The Typical application circuit and block diagram for this
device is provided on page 6. The Truth table for the device
is provided on page 2.

DC Bias Voltage

The ISL54004 has internal DC bias circuitry which DC
offsets the incoming audio signal at V

/2. When using a 5V

DD

supply the DC offset will be 2.5V. When using a 3.6V supply
the DC offset will be 1.8V.

Since the signal gets biased internally at V

/2 the audio

DD

signals need to be AC coupled to the inputs of the device.
The value of the AC coupling capacitor depends on the low
frequency range required for the application. A capacitor of

0.22

μF will pass a signal as low as 7.2Hz. The formula

required to calculate the capacitor value is in Equation 1:

1

-----------------------------------------------

C

≥

6.28()f()100k()[]

The 100k

Ω is the impedance looking into the input of the

(EQ. 1)

ISL54004 device.

BTL Speaker Amplifier

The ISL54004 contains one bridge-tied load (BTL) amplifier
designed to drive an 8Ω speaker load differentially. The
output to the BTL amplifier are SPK+ and SPK-. The
speaker load gets connected across these terminals.

A single BTL driver consists of an inverting and non-inverting
power op amps. The AC signal out of each op amp are equal
in magnitude but 180° out of phase, so the AC signal at
SPK+ and SPK- have the same amplitude but are 180° out
of phase.

Driving the load differentially using a BTL configuration
doubles the output voltage across the speaker load and
quadruples the power to the load. In effect you get a gain of
two due to this configuration at the load as compared to
driving the load with a single-ended amplifier with its load
connected between a single amplifier’s output and GND.

The outputs of the BTL are biased at V

/2. When the load

DD

gets connected across the + and - terminal of the BTL the
mid supply DC bias voltage at each output gets cancelled
out eliminating the need for large bulky output coupling
capacitors.

Headphone (Single-Ended) Amplifiers

The ISL54004 contains two single-ended (SE) headphone
amplifiers for driving the left and right channels of a 32Ω or
16Ω headphone speakers.

The audio signal at the output of each SE driver is biased at
V

/2 and unlike the BTL driver that cancels this offset due

DD

to its differential connection, a capacitor is required at the
output of each SE driver to remove this DC voltage from the
headphone load.

This coupling capacitor along with the resistance of the
speaker load creates a high pass filter that sets the
amplifier’s lower bandpass frequency limit. The value of this
AC coupling capacitor depends on the low frequency range
required for the application. The formula required to
calculate the capacitor value is in Equation 2:

--------------------------------------------------------------

C

≥

6.28()f()Rspeaker()[]

For an application driving a 32

1

Ω headphone with a lower

(EQ. 2)

frequency requirement of 150Hz the required capacitor value
is in Equation 3:

1

------------------------------------------------

C

≥ 33μF=

6.28()150()32()[]

(EQ. 3)

Use the closest standard value.

Headphone Sense Function

With a logic “1” at the HP control pin while the HO control pin
is low will activate the headphone drivers and disable the
BTL driver.

The “ISL54004 Typical Application Circuit and Block
Diagram” on page 6 shows the implementation of the
headphone control function using a common headphone
jack.

The HP pin gets connected to the mechanical wiper blade of
the headphone jack. Two external resistors are required for
proper operation. A 100kΩ pull-up resistor from the HP pin to
VDD and a 10kΩ pull-down resistor from the jack’s audio
signal pin to GND of the jack signal pin to which the wiper is
connected. See “ISL54004 Typical Application Circuit and
Block Diagram” on page 6.

When no headphone plug is inserted into the jack the
voltage at the HP pin gets set at a low voltage level due to
the 10kΩ resistor and 100kΩ resistor divider network
connection to V

When a headphone is inserted into the jack the 10kΩ
resistor gets disconnected from the HP control pin and the
HP pin gets pulled up to V
the headphone drivers are activated.

A microprocessor or a switch can be used to drive the HP
pin rather than using the headphone jack contact pin.

DD

.

. Since the HP pin is now high

DD

One SE amplifier drives the right speaker of the headphone
and other SE amplifier drives the left speaker of the
headphone. The speaker load gets connected between the
output of the amplifier and ground.

7

Note: With a logic “1” at the HO pin the BTL driver remains
active regardless of the voltage level at the HD pin. This
allows a headphone to be plugged into the headphone jack
without activating the HP drivers. Music will continue to play
through the internal 8Ω speaker rather than headphones.

FN6513.1

June 27, 2007

ISL54004

Low Power Shutdown

With a logic “1” at the SD control pin the device enters the
low power shutdown state. When in shutdown the BTL and
headphone amplifiers go into an high impedance state and
I

supply current is reduced to 26µA (typ).

DD

In shutdown mode before the amplifiers enter the high
impedance/low current drive state, the bias voltage of V

DD

/2
remains connected at the output of the amplifiers through a
100kΩ resistor.

This resistor is not present during active operation of the
drivers but gets switched in when the SD pin goes high. It
gets removed when the SD pin goes low.

Leaving the DC bias voltage connected through a 100kΩ
resistor while going into and out of shutdown reduces the
transient at the speakers to a small level preventing clicking
or popping in the speakers.

Note: When the SD pin is High it overrides all other logic
pins.

QFN Die Attach Paddle Considerations

The QFN package features an exposed thermal pad on its
underside. This pad lowers the package’s thermal resistance
by providing a direct heat conduction path from the die to the
PCB. Connect the exposed thermal pad to GND by using a

large copper pad and multiple vias to the GND plane. The
vias should be plugged and tented with plating and solder
mask to ensure good thermal conductivity.

Best thermal performance is achieved with the largest
practical copper ground plane area.

PCB Layout Considerations and Power
Supply Bypassing

To maintain the highest load dissipation and widest output
voltage swing the power supply PCB traces and the traces
that connect the output of the drivers to the speaker loads
should be made as wide as possible to minimize losses due
to parasitic trace resistance.

Proper supply bypassing is necessary for high power supply
rejection and low noise performance. A filter network
consisting of a 10µF capacitor in parallel with a 0.1µF
capacitor is recommended at the voltage regulator that is
providing the power to the ISL54004 IC.

Local bypass capacitors of 0.1µF should be put at each V
pin of the ISL54004 device. They should be located as close
as possible to the pin, keeping the length of leads and traces
as short as possible.

A 1µF capacitor from the REF pin (pin 10) to GND is needed
for optimum PSRR and internal bias voltage stability.

DD

Typical Performance Curves T

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

THD+N (%)

0.2

0.1

VDD = 5V
BTL

= 8Ω

R

L

= 800mW

P

O

20 20k50 100 200 500 1k 2k 5k 10k

FREQUENCY (Hz)

FIGURE 1. THD+N vs FREQUENCY

= +25°C, Unless Otherwise Specified

A

THD+N (%)

1.0

0.9

VDD = 3.6V

0.8

BTL

0.7

0.6

0.5

0.4

0.3

0.2

0.1

= 8W

R

L

= 200mW

P

O

20 20k50 100 200 500 1k 2k 5k 10k

FREQUENCY (Hz)

FIGURE 2. THD+N vs FREQUENCY

8

FN6513.1

June 27, 2007

ISL54004

Typical Performance Curves T

10

VDD = 5V

5

BTL
R

= 8Ω

L

f = 1kHz

2
1

0.50

0.20

THD+N (%)

0.10

0.05

0.02

0.01
10m 120m 50m 100m 200m 500m

FIGURE 3. THD+N vs OUTPUT POWER FIGURE 4. THD+N vs OUTPUT POWER

1.0

0.9

V

= 5V

DD

0.8

SE

0.7

= 32Ω

R

L

0.6

P

= 50mW

O

0.5

0.4

OUTPUT POWER (W)

= +25°C, Unless Otherwise Specified (Continued)

A

10

VDD = 3.6V

5

BTL

= 8Ω

R

L

f = 1kHz

2
1

0.50

0.20

THD+N (%)

0.10

0.05

0.02

0.01
10m 600m20m 40m 70m 100m 200m

1.0

0.9

VDD = 5V

0.8

SE

0.7

= 16Ω

R

L

0.6

= 50mW

P

O

0.5

0.4

OUTPUT POWER (W)

0.3

THD+N (%)

0.2

0.1
20 20k50 100 200 500 1k 2k 5k 10k

FREQUENCY (Hz)

FIGURE 5. THD+N vs FREQUENCY

1.00
VDD = 3.6V

SE

0.50

R

= 32Ω

L

P

= 30mW

O

0.20

0.10

THD+N (%)

0.05

0.02

0.3

THD+N (%)

0.2

0.1
20 20k50 100 200 500 1k 2k 5k 10k

FREQUENCY (Hz)

FIGURE 6. THD+N vs FREQUENCY

1.00

VDD = 3.6V

0.50

0.20

0.10

THD+N (%)

0.05

0.02

SE

= 16

Ω

R

L

PO = 60mW

0.01
20 20k50 100 200 500 1k 2k 5k 10k

FREQUENCY (Hz)

FIGURE 7. THD+N vs FREQUENCY FIGURE 8. THD+N vs FREQUENCY

9

0.01
20 20k50 100 200 500 1k 2k 5k 10k

FREQUENCY (Hz)

FN6513.1

June 27, 2007

ISL54004

Typical Performance Curves T

10.0
VDD = 5V

5.00

SE

= 32Ω

R

L

2.00

f = 1kHz

1.00

0.50

0.20

THD+N (%)

0.10

0.05

0.02

0.01

10m 100m20m 30m 40m 50m 70m

OUTPUT POWER (W)

FIGURE 9. THD+N vs OUTPUT POWER FIGURE 10. THD+N vs OUTPUT POWER

10.0
VDD = 3.6V

5.00

SE
R

= 32Ω

2.00

1.00

0.50

L

f = 1kHz

= +25°C, Unless Otherwise Specified (Continued)

A

10.0
V

= 5V

DD

5.00

SE

RL = 16

2.00

f = 1kHz

1.00

0.50

0.20

THD+N (%)

0.10

0.05

0.02

0.01

10m 200m20m 30m 50m 70m 100m

10.0
VDD = 3.6V

5.00

SE
R

= 16Ω

L

f = 1kHz

2.00

1.00

0.50

Ω

OUTPUT POWER (W)

0.20

THD+N (%)

0.10

0.05

0.02

0.01
10m 55m12m 15m 20m 25m 35m 45m

OUTPUT POWER (W)

FIGURE 11. THD+N vs OUTPUT POWER

-50

-55

-60

-65

-70

-75

-80

-85

-90

CROSSTALK (dB)

-95

-100

-105

-110

VDD = 5V

= 15mW

P

O

INxR to HPL

INxL to HPR

20 20k50 100 200 500 1k 2k 5k 10k

FREQUENCY (Hz)

0.20

THD+N (%)

0.10

0.05

0.02

0.01
10m 100m20m 30m 40m 50m 70m

OUTPUT POWER (W)

FIGURE 12. THD+N vs OUTPUT POWER

-60
VDD = 5V

-65

-70

-75

-80

-85

-90

-95

-100

OFF ISOLATION (dB)

-105

-110

-115

-120
20 20k50 100 200 500 1k 2k 5k 10k

FREQUENCY (Hz)

HPR and HPL

BTL

FIGURE 13. CROSSTALK vs FREQUENCY FIGURE 14. OFF ISOLATION vs FREQUENCY

10

FN6513.1

June 27, 2007

ISL54004

Typical Performance Curves T

-20

-22

VDD = 5V

-24
BTL

-26

-28

V

= 200MV

RIPPLE

-30

-32

-34

-36

-38

-40

-42

-44

-46

-48

-50

PSRR (dB)

-52

-54

-56

-58

-60

-62

-64

-66

-68

-70

10 20k20 50 100 200 500 1k 2k 5k 10k

FIGURE 15. PSRR vs FREQUENCY FIGURE 16. PSRR vs FREQUENCY

700

VDD = 5V
BTL

600

R

= 8Ω

L

500

400

300

200

POWER DISSIPATION (mW)

100

P-P

FREQUENCY (Hz)

= +25°C, Unless Otherwise Specified (Continued)

A

-20
VDD = 5V

-25
SE

-30

V

RIPPLE

-35

-40

-45

-50

-55

-60

PSRR (dB)

-65

-70

-75

-80

-85

-90

10 20k20 50 100 200 500 1k 2k 5k 10k

400

VDD = 3.6V

BTL

POWER DISSIPATION (mW)

350

300

250

200

150

100

= 8Ω

R

L

50

= 200mV

P-P

HPR

HPL

FREQUENCY (Hz)

0

0 250 500 750 1000

P

OUT

(mW)

0

0 100 200 300 400

P

(mW)

OUT

FIGURE 17. POWER DISSIPATION vs OUTPUT POWER FIGURE 18. POWER DISSIPATION vs OUTPUT POWER

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

PROCESS:

Submicron CMOS

11

500

FN6513.1

June 27, 2007

ISL54004

Thin Quad Flat No-Lead Plastic Package
(TQFN)
Thin Micro Lead FramePlastic Package
(TMLFP)

L20.4x4A

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220WGGD-1 ISSUE I)

MILLIMETERS

SYMBOL

A 0.70 0.75 0.80 -

A1 - 0.02 0.05 -

A2 - 0.55 0.80 9

A3 0.20 REF 9

b 0.18 0.25 0.30 5, 8

D 4.00 BSC -

D1 3.75 BSC 9

D2 1.95 2.10 2.25 7, 8

E 4.00 BSC -

E1 3.75 BSC 9

E2 1.95 2.10 2.25 7, 8

e 0.50 BSC -

k0.20 - - -

L 0.35 0.60 0.75 8

N202

Nd 5 3

Ne 5 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

NOTESMIN NOMINAL MAX

Rev. 0 11/04

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

12

FN6513.1

June 27, 2007