intersil ISL5314 DATA SHEET

®

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ISL5314

Data Sheet July 28, 2005

Direct Digital Synthesizer

The 14-bit ISL5314 provides a complete Direct Digital
Synthesizer (DDS) system in a single 48-pin LQFP package.
A 48-bit Programmable Carrier NCO (numerically controlled
oscillator) and a high speed 14-bit DAC (digital to analog
converter) are integrated into a stand alone DDS.

The DDS accepts 48-bit center and offset frequency control
information via a parallel processor interface. A 40-bit
frequency tuning word can also be loaded via an asynchronous
serial interface. Modulation control is provided by 3 external
pins. The PH0 and PH1 pins select phase offsets of 0, 90,
180 and 270 degrees, while the ENOFR pin enables or zeros
the offset frequency word to the phase accumulator.

The parallel processor interface has an 8-bit write-only data
input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe
(WR), and a Write Enable (WE

). The processor can update
all registers simultaneously by loading a set of master
registers, then transfer all master registers to the slave
registers by asserting the UPDATE

pin.

Ordering Information

PART # TEMP. RANGE (°C) PACKAGE PKG. DW G . #

ISL5314IN -40 to 85 48 LQFP Q48.7x7A
ISL5314INZ

(See Note)

-40 to 85 48 LQFP
(Pb-free)

Q48.7x7A

ISL5314EVAL2 25 Evaluation Board

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.

Block Diagram

C(7:0)
A(3:0)

WR
WE

UPDATE

SDATA

SSYNC

SCLK

ENOFR
PH(1:0)

MASTER

SLAVE

CONTROL

SERIAL

MODULATION

CONTROL

PHASE

ACCUM.

∑

SINE

WAVE

ROM

COMPOUT

­+

14 BIT

DAC

INT
REF

IN­IN+

COMP1
COMP2

IOUTA
IOUTB

REFIO
REFLO

FN4901.2

Features

• 125MSPS output sample rate with 5V digital supply

• 100MSPS output sample rate with 3.3V digital supply

• 14-bit digital-to-analog (DAC) with internal reference

• Parallel control interface for fast tuning (50MSPS control
register write rate) and serial control interface

• 48-bit programmable frequency control

• Offset frequency register and enable pin for fast FSK

• Small 48-pin LQFP packaging

• Pb-Free plus anneal available (RoHS compliant)

Applications

• Programmable local oscillator

• FSK, PSK modulation

• Direct digital synthesis

• Clock generation

Pinout

48-PIN LQFP (Q48.7X7A)

TOP VIEW

WR

DGND

AVDD

COMP2

WE

AGND

NC

IN+

A0

IN-

A1

373839404142434445464748

36
35
34
33
32
31
30
29
28
27
26
25

2423222120191817

AGND

A2
A3
PH0
PH1

SSYNC
DVDD

SCLK
DGND

DGND
SDATA
DVDD
DGND

C2
C1
C0

ENOFR

DGND

CLK

DVDD

RESET

UPDATE

COMPOUT

REFLO

REFIO

C3

C4

1
2

3
4
5
6

7
8
9
10
11

12

13 14 15 16

FSADJ

COMP1

C6

C7

DVDD

C5

ISL5314

AGND

AGND

IOUTA

IOUTB

RESET

CLK

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved

ISL5314

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Typical Application Circuit (Parallel Control Mode, Sinewave Generation)

CLOCK

SOURCE

f

CLK

µPROCESSOR/

FPGA/CPLD

DV

PP

0.1µF

SDATA, SSYNC, SCLK (IN PARALLEL CONTROL MODE,
SERIAL CONTROL CAN ALSO BE USED IF DESIRED.)
WRITE CLOCK (WR)

WRITE ENABLE

C2
C1
C0

ENOFR

DGND

CLK

DVDD

RESET

UPDATE

REFLO

REFIO

4

C3

C6

C7

C5

DVDD

ISL5314

WR

1
2

3
4
5
6

7
8
9
10
11

12

13 14 15 16

C4

A3:A0 BUS

8

C7:C0 BUS

0.1µF

COMPOUT

DGND

WE

NC

A0

3

A1

373839404142434445464748

36
35
34
33
32
31
30
29
28
27
26
25

2423222120191817

A2
A3
PH0
PH1

SSYNC
DVDD

SCLK
DGND

DGND
SDATA
DVDD
DGND

DV

0.1µF

PP

DV

PP

0.1µF

+5V POWER SOURCE

+

+

10µF

10µF

R

SET

2kΩ

0.1µF

FERRITE

BEAD

10µH

FERRITE

BEAD

10µH

AV

FSADJ

PP

AGND

COMP1

50Ω

0.1µF

0.1µF

AGND

50Ω

DGND

AGND

AVDD

AGND

IOUTA

IOUTB

COMP2

0.1µF

(IOUTA) ANALOG OUTPUT

1µF

1µF

IN-

IN+

AGND

0.1µF

(DIGITAL POWER PLANE)

DVPP

AVPP

(ANALOG POWER PLANE)

AV

PP

2

ISL5314

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Functional Description

The ISL5314 is an NCO with an integrated 14-bit DAC
designed to run in excess of 125MSPS. The NCO is a 16-bit
output design, which is rounded to fourteen bits for input to the
DAC. The frequency control is the sum of a 48-bit center
frequency word, a 48-bit offset frequency word, and a 40-bit
serially loaded tuning word. The three components are added
modulo 48 bits with the alignment shown in T able 1. Each of the
three terms can be zeroed independently (via the
microprocessor interface for the center and serial frequency
registers and via the ENOFR pin for the offset frequency term).

Frequency Generation

The output frequency of the part is determined by the
summation of three registers:

f

= f

OUT

where CF is the center frequency register, OF is the offset
frequency register, SF is the serial frequency register and
f

CLK

With a 125MSPS clock rate, the center frequency can be
programmed to

(125 x 10
The addition of the frequency control words can be interpreted

as two’s complement if conv enient. F or example, if the center
frequency is set to 4000...00h and the offset frequency set to
C000..00h, the programmed center frequency would be f
and the programmed offset frequency -f
be 10000..00h, but because only the lower 48 bits are retained,
the effective frequency would be 0. In reality, frequencies above

8000...00h alias below f
the MSB is only provided as a convenience for two’s
complement calculations.

The frequency control of the NCO is the change in phase per
clock period or dφ/dt. This is integrated by the phase
accumulator to obtain frequency . The most significant 24 bits
of phase are then mapped to 16 bits of amplitude in a sine
look-up table function. The range of dφ/dt is 0–1 with 1
equaling 360 degrees or (2 x pi) per clock period. The phase
accumulator output is also 0–1 with 1 equaling 360 degrees.
The operations are modulo 48 bits because the MSB (bit 47)
aligns with the most significant address bit of the sine ROM
and the ROM contains one cycle of a sinusoid. The MSB is
weighted at 180 degrees. Full scale is 360 degrees minus
one LSB and the phase then rolls over to 0 degrees for the
next cycle of the sinusoid.

The DDS can be clocked with either a sinusoidal or a square
wave. Refer to the digital inputs V
electrical specifications table.

x ((CF + OF +SF) mod (248))/ (248),

CLK

is the DDS clock rate.

6

)/(248) = 0.4 µHz resolution.

/2 (the output of the part is real), so

CLK

/4. The sum would

CLK

and VIL values in the

IH

CLK

/4

four address pins (A3:A0), a write strobe (WR), and a write
enable (WE
processor interface loads a set of master registers. The
contents of the master set of registers is then transferred to a
slave set of registers by asserting a pin (UPDATE
allows all of the bits of the frequency control to be updated
simultaneously.

The rate which the user writes (WR) to these registers does not
have to be the same rate as the DDS clock rate (the rate of the
NCO and DAC; pin CLK). It is e x pected that most applications
will have a slower register write rate than the DDS clock rate. It
takes one WR cycle at the write rate for each register that is
written and another eleven CLK cycles at the DDS r ate to write
and obtain a new output, assuming that the UPDATE
always active . If the UPD ATE
word has been written, it takes fourteen CLK cycles, rather than
eleven. F or cases which require the output to be updated with
all of the new frequency information present, it is necessary that
the UPDATE
has been written to the device. See the Timing Diagrams for
more information. The parallel registers can be written at a rate
of CLK/2, such that updated control words can be pipelined. If
the application does not require all registers to be written, then
the output frequency can be changed more quickly . For
example, if only 32 bits of frequency information are needed
and it is desired that the output be updated all at once, then it
takes four WR cycles, then the ass ertion low of the UPD ATE
pin, plus another fourteen CLK cycles at the DDS rate to write
and update a new frequency.

The timing is the same whether writing to the center or offset
frequency registers. For f aster frequ ency update, consider the
ENOFR (Enable Offset Fr equency Register) option. Once the
values have been written to the center and offset frequency
registers, the user can enable and disab le the offset frequency
register, which is added to the center frequency value when
enabled. The ENOFR pin has a latency of fourteen CLK
cycles, but simplifies the interface because the only pin that
has to be toggled is the ENOFR pin. See the FSK explanation
for more information.

). The interface is a master/slave type. The

). This

pin is

pin is not active until after the new

be inactive until after all of the new frequency word

Serial Interface

A serial interface is provided for loading a tuning frequency .
This interface can be asynchronous to the master clock of the
part. When the tuning word has been shifted into the part, it is
loaded into a holding register by the serial interface clock,
SCLK. This loading triggers a synchronization circuit to transfer
the data to a slave register synchronous with the master clock.
A minimum of eleven serial clocks (at minimum serial word size
of eight) are necessary to complete the transfer to the slave
register. Another twelv e DDS CLK cycles are necessary before
the output of the DDS reflects the new frequency .

Parallel Interface

The processor interface is an 8-bit parallel write only
interface. The interface consists of eight data bits (C7:C0),

3

Serial loading latency = ((8 x N + 3) x SCLK)+ 12 x f

CLK

,

ISL5314

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TABLE 1. FREQUENCY CONTROL BIT ALIGNMENTS

48 Bits
(Individual Bit Alignment)

Phase Accumulator xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Center Frequency xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Offset Frequency xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Serial Frequency, 8 Bits xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Serial Frequency, 16 Bits xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000
Serial Frequency, 24 Bits xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000
Serial Frequency, 32 Bits xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000
Serial Frequency, 40 Bits xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000

4444 4444 3333 3333 3322 2222 2222 1111 1111 1100 0000 0000
7654 3210 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210

where N = 1–5 (for 8–40 bit serial data) and f
clock rate. Three e xtr a SCLKs are required (one f or the SYNC
pulse plus two additional for register transfer). The latency in
seconds depends on how many bits of serial data are being
written and the speeds of both clocks. The center and offset
frequency registers cannot be written using the serial pins.
They must be programmed using the parallel interface.

In order to use the three wire serial interface in a mode that is
not the default mode, the parallel control bus must be used to
reprogram register 12. Register 12 can be set according to the
desired options of the serial interface that are described in the
register description table. Since the serial register defaults
enabled, it must be disabled in register 13 (bit 6) if it is not used.

is the DDS

CLK

Register 14

The parallel control bus must be used to program register 14
with 0x00h or 0x30h after assertion of RESET
Register table in the back of the datasheet for more information.

. See the Control

Control Pins

There are three control pins provided for phase and frequency
control. The PH0 and PH1 pins select phase offsets of 0, 90,
180, and 270 degrees and can be used for low speed,
unfiltered BPSK or QPSK modulation. These pins can also be
used for providing sine/cosine when using two ISL5314s
together as quadrature local oscillators. The ENOFR pin
enables or zeros the offset frequency word to the phase
accumulator and can be used for FSK or MSK modulation.
These control pins and the UPDATE
special cells to minimize the probability of metastability . Writing
anything to register 15 behaves like an UPDA TE
user can save one control pin if desired.

pin are passed through

so that the

Reset

A RESET pin is available which resets all registers to their
defaults. Register 14 must always be written with 0x00h or
0x30h after a RESET
take the RESET
and then take the RESET
the RESET
is eleven CLK cycles. See the register description table in
the back of the data sheet for the default states of all bits in

pin going high until the output reflects the reset

. In order to reset the part, the user must

pin low, allow at least one CLK rising edge,

pin high again. The latency from

all registers. After RESET
is required before the control registers can be written to
again. The center frequency register resets to f
offset frequency register resets to an unknown frequency but
is disabled. The serial frequency register resets to an
unknown frequency and is enabled. If the serial register is
not used, disable it in register 13 using the parallel interface.

goes high, one rising edge of CLK

/4. The

CLK

Comparator

A comparator is provided for square wave output generation.
The user can take the DDS analog output, filter it, and then
send it back into the comparator. A square wa ve will be
generated at the comparator output (COMPOUT pin) at an
amplitude level that is dependent on the digital power supply
(DV

). The comparator was designed to operate at speeds

DD

comparable to the DDS output frequency range (approximately
0–50MHz). It is not intended for low jitter applications (<0.5ns).
The comparator has a sleep mode that is activated by
connecting both inputs (IN- and IN+) to the analog power
supply plane. This will save appro ximately 4mA of current (as
shown in the Typical Application Circuit). If the comparator is
not used, leave the COMPOUT pin floating.

DAC Voltage Reference

The internal voltage reference for the DAC has a nominal
value of +1.2V with a ±60ppm/
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(11) selects the reference. The internal reference can be
selected if pin 11 is tied low (ground). If an external reference
is desired, then pin 11 should be tied high (the analog supply
voltage) and the external reference driven into REFIO, pin

12. The full-scale output current of the converter is a function

of the voltage reference used and the value of R
should be within the 2mA–20mA range, though operation
below 2mA is possible, with performance degradation.

If the internal reference is used, V
approximately 1.2V (pin 13). If an external reference is used,
V

I

will equal the external reference.

FSADJ

(Full Scale) = (V

OUT

FSADJ/RSET)

o

C drift coefficient over the

. I

SET

will equal

FSADJ

X 32.

OUT

4

ISL5314

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Analog Output

IOUT A and IOUTB are complementary current outputs. They
are generated by a 14-bit DA C that is capab le of running at the
full 125MSPS rate. The DDS clock also clocks the D A C. The
sum of the two output currents is always equal to the full scale
output current minus one LSB. If single-ended use is desired, a
load resistor can be used to convert the output current to a
voltage. It is recommended that the unused output be equally
terminated. The voltage developed at the output must not
violate the output voltage compliance range of -1.0V to +1.25V.
R

(the impedance loading each current output) should be

LOAD

chosen so that the desired output voltage is produced in
conjunction with the output full scale current. If a known line
impedance is to be driven, then the output load resistor should
be chosen to match this impedance. The output voltage
equation is:

V

= I

OUT

X R

OUT

These outputs can be used in a differential-to-single-ended
arrangement. This is typically done to achieve better harmonic
rejection. Because of a mismatch in IOUT A and IOUTB , the
transformer does not improve the harmonic rejection. Howev er ,
it can provide voltage gain without adding distortion. The SFDR
measurements in this data sheet were performed with a 1:1
transformer on the output of the DDS (see Figure 1). With the
center tap grounded, the output swing of pins 17 and 18 will be
biased at zero volts. The loading as shown in Figure 1 will result
in a 500mV

signal at the output of the transformer if the full

P-P

scale output current of the DAC is set to 20mA.

REQ IS THE IMPEDANCE

LOADING EACH OUTPUT

PIN 17

PIN 18

ISL5314

FIGURE 1. TRANSFORMER OUTPUT CIRCUIT OPTION

V

= 2 x I

OUT

OUT

center tap to float will result in identical transformer output,
howeve r the output pins of the DAC will have positive DC
offset, which could limit the voltage swing available due to
the output voltage compliance range. The 50Ω load on the
output of the transformer represents the load at the end of a
‘transmission line’, typically a spectrum analyzer,
oscilloscope, or the next function in the signal chain. The
necessity to have a 50Ω impedance looking back into the
transformer is negated if the DDS is only driving a short
trace. The output voltage compliance range does limit the
impedance that is loading the DDS output.

.

LOAD

IOUTB

IOUTA

50Ω

100Ω

50Ω

= (2 x I

V

OUT

50Ω REPRESENTS THE
SPECTRUM ANALYZER

50Ω

OUT

x REQ)V

x REQ, where REQ is 12.5Ω. Allowing the

PP

Application Considerations

Ground Plane

Separate digital and analog ground planes should be used. All
of the digital functions of the device and their corresponding
components should be located over the digital ground plane
and terminated to the digital ground plane. The same is true for
the analog components and the analog ground plane. Pins 11
through 24 are analog pins, while all the others are digital.

Noise Reduction

To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the power supply pins, AV
and DV

. Also, the layout should be designed using

DD

separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DV

and to the analog ground for A VDD. Additional filtering

DD

of the power supplies on the board is recommended.

Power Supplies

The DDS will provide the best SFDR (spurious free dynamic
range) when using +5V analog and +5V digital power supply .
The analog supply must always be +5V (±10%). The digital
supply can be either a +3.3V (±10%), a +5V (±10%) supply,
or anything in between. The DDS is rated to 125MSPS when
using a +5V digital supply and 100MSPS when using a
+3.3V digital supply.

Improving SFDR

+5V power supplies provides the best SFDR. Under some
clock and output frequency combinations, particularly when
the f

CLK/fOUT

ratio is less than 4, the user can improve
SFDR even further by connecting the COMP2 pin (19) of the
DDS to the analog power supply. The digital supply must be
+5V if this option is explored. Improvements as much as
6dBc in the SFDR-to-Nyquist measurement were seen in the
lab.

FSK Modulation

Binary frequency shift keying (BFSK) can be done by using
the offset frequency register and the ENOFR pin. M-ary FSK
or GFSK (Gaussian) can be done by continuously loading in
new frequency words. The maximum FSK data rate of the
ISL5314 depends on the way the user programs the device
to do FSK, and the form of FSK.

For example, simple BFSK is efficiently performed with the
ISL5314 by loading the center frequency register with one fre­quency, the offset frequency register with another frequency ,
and toggling the ENOFR (enable offset frequency register)
pin. The latency is fourteen CLK cycles between assertion of
the ENOFR pin and the change occurring at the analog out­put. However, the change in frequency can be pipelined such
that the ENOFR can be toggled at a rate up to

ENOFR
where f

= f

MAX

is the frequency of the master CLK.

CLK

CLK

/2,

DD

5