intersil ISL5239 DATA SHEET

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ISL5239

Data Sheet September 2, 2005 FN8039.2

Pre-Distortion Linearizer

The ISL5239 Pre-Distortion Linearizer (PDL) is a full featured component for P o wer Amplifier (PA) linearization to improve PA power efficiency and reduce PA cost.

The Radio Frequency (RF) PA is one of the most expensive and power-consuming devices in any wireless communication system. The ideal RF P A would hav e an entirely linear relationship between input and output, expressed as a simple gain which applies at all power levels. Unf ortunately, realizable RF amplifiers are not completely linear and the use of predistortion techniques allows the substitution of lower cost/power PA’s for higher cost/power PA’s.

The ISL5239 pre-distortion linearizer enables the linearization of less expensive PA’s to provide more efficient operation closer to saturation. This provides the benefit of improved linearity and efficiency , while reducing PA cost and operational expense.

The ISL5239 features a 125MHz pre-distortion bandwidth capable of full 5th order intermodulation correction for signal bandwidths up to 20MHz. This bandwidth is particularly well suited for 3G cellular deployments of UMTS and CDMA2000. The device also corrects for PA memory effects that limit predistortion performance including self heating.

The ISL5239 combines an input formatter and interpolator, predistortion linearizer, an IF converter, correction filter , gain/phase/offset adjustment, output formatter, and input and feedback capture memories into a single chip controlled by a 16bit linearizer interface.

The ISL5239 supports log of power, linear magnitude, and linear power based pre-distortion, utilizing two Look-Up T ab le (LUT) based algorithms for the pre-distortion correction. The device provides progr ammable scaling and offset corre ction, a nd provides for phase imbalance adjustment.

Features

• Output Sample Rates Up to 125MSPS

• Full 20MHz Signal Bandwidth

• Dynamic Memory Effects Compensation

• Input and Feedback Capture Memories

• LUT-based Digital Pre-distortion

• Two 18-bit Output Busses with Programmable Bit-Width

• 16-Bit Parallel µProcessor Interface

• Input Interpolator x2, x4, x8

• Programmable Frequency Response Correction

• Low Power Architecture

• Threshold Comparator for Internal Triggering

• Quadrature or Digital IF Architecture

• Lowest-Cost Full-Featured Part Available

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Base Station Power Amplifier Linearization

• Operates with ISL5217 in Software Radio Solutions

• Compatible with the ISL5961 or ISL5929 D/A Converters

Ordering Information

PART

NUMBER

ISL5239KI ISL5239KI -40 to 85 196 Ld BGA V196.15x15 ISL5239KIZ

(Note) ISL5239EVAL1 25 Evaluation Kit

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

ISL5239KIZ -40 to 85 196 Ld BGA

TEMP

RANGE

C) PACKAGE

(

(Pb-free)

PKG. DWG.

V196.15x15

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

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CLK

TRIGIN

IIN<17:0>

QIN<17:0>

CLKOUT

ISTRB

TRIGOUT

A<5:0>

P<15:0>

BUSY

RESET

INPUT

FORMATTER

AND

INTERPOLATOR

X1, X2, X4, X8

uP INTERFACE

PRE-DISTORTER

WITH

TWO 1K x 60

LUTs

INPUT

MEMORY

(2k x 32)

ISL5239

IF CONVERTER

REAL 1X REAL 2X

COMPLEX

CORRECTION

FILTER REAL 1X REAL 2X

COMPLEX

GAIN /

PHASE OFFSET ADJUST

OUTPUT

DAT A

FORMATTER

8-18 BIT-WIDTH

FEEDBACK

MEMORY

(1k x 20)

SERCLK SERSYNC SEROUT SERIN

IOUT<17:0> QOUT<17:0>

FBCLK FB<19:0>

Functional Block Diagram

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ISL5239 Pre-Distortion Linearizer

IIN<17:0>

QIN<17:0>

CLKOUT

ISTRB

TMS

TDI

TCK

TRST

TDO

TRIGIN

OFFSET BINARY

DE-MUX

INPUT TYPE

(PAR/SERIAL)

PD MAG.

MAX

IFIP I,Q

PD I,Q

PD MAG.

THRESHOLD

MIN

TRIG SEL

INPUT

SEL STATE

BYPASS BYPASS BYPASS

HALF BAND

FILTER

MUX

JTAG

COMPARE

INPUT DELAY

COUNT

INPUT

HALF BAND

FILTER

/ /

IFIP I,Q

LUT DELTA DATA Q

LUT ADDR AUTO INCR.

PWR INTGR PER.

TRIG

STATE

SER. OUTPUT EN.

HALF

BAND

FILTER

CM TEST

FUNC. SEL.

LUT DELTA DATA I

PWR HIGH

FB DELAY COUNT

FORMAT

TEST

OFFSET

SCALE

PD MAG.

LUT DATA I

LUT DATA Q

ACTIVE LUT

LUT ADDR

PWR LOW

INPUT OR TEST

LUT

ADDRESS

CALCULATION

ADDR

DATA

LUT

POWER

INTEGRATOR

PAR. TO SERIAL

BYPASS BYPASS BYPASS

CONV.

PD I,Q

PRE-D OR BYPASS

BYPASS

CHANNEL 3

MEMORY EFFECT

COMPENSATION

POWER

COEF. A COEF. B

SERIAL TO PAR.

MODE

CORRECTION

FILTER REAL 1X REAL 2X

COMPLEX

HM, KM, LM, GM, DC OFFSETS

OUTPUT WORD WIDTH SEL.

COEF. DATA REAL PIPELINE SEL. COEF. ADDR.

SERIAL INPUT EN.

COEF . B SELECT

GAIN /

PHASE

OFFSET

ADJUST.

OUTPUT VALUE TYPE

OUTPUT

DATA

FORMATTER

8-18 BIT-WIDTH

SERIN

SERCLK

SERSYNC

SEROUT

IOUT<17:0> QOUT<17:0>

EXTERNAL

MEMORY EFFECTS

FPGA

FBCLK

FB<19:0>

ISL5239

ADDR DATA

FEEDBACK

CAPTURE

MEMORY 1K

TRIGOUT

CLK

A<5:0>

P<15:0>

BUSY

RESET

DATA ADDR

CM TEST I,Q

MEMORY SELECT

INPUT

CAPTURE

MEMORY 2K

uP INTERFACE

Pinout

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ISL5239

196 CABGA

TOP VIEW

123456789 1110

NCISTRB IIN3

P13

TRST NC IOUT1

A1 A5 IIN13 IIN1 QOUT2 QOUT5

VCCC RD

P7 FB11 SERINP6

GND

TDO VCCC

NC QIN10 VCCC IOUT17

QOUT17 FB17IIN10 IIN6

P1 GND

GND FB9

VCCIO

RESET

BUSY

TCK FB3 FB4

TMS

QIN11 IOUT16QIN4 IOUT0 IOUT2

P11

P15

QIN6

QIN9

QIN5 GND

QOUT11 GNDGNDQOUT15 VCCIO VCCC NCVCCC IIN16 IIN12 IIN9 IIN4 IIN0

QOUT9VCCIOVCCIOIIN17 IIN14 IIN7VCCC

VCCCQOUT12QOUT16 QOUT1 QOUT3IIN15 IIN11 IIN8 IIN2

QOUT8

QOUT13

QOUT14VCCCWR IIN5 GND QOUT10

FB13

SEROUT

SERSYNC

TRIGOUT

IOUT11GNDQIN0 VCCC

GND

VCCCIOUT9DCTEST FB2QIN2 VCCIO

VCCIO IOUT3IOUT7QIN16 GND

IOUT8QIN14 QIN3 IOUT10

QOUT6 QOUT4 NC GND

QOUT7

FB14 VCCCA4

FB16VCCIO FB15 FB10P3

GNDP10 VCCIO CLKOUTP12 P8

FB7CLK FB8P14

FB0

GNDIIOUT12

IOUT6VCCIONC IOUT14 IOUT5 VCCC NCVCCC QIN12 QIN8 QIN1 IOUT15

VCCIO

FB12

FB6

FB1IOUT4IOUT13QIN17TDI

VCCIO

13 14

QOUT0

FB18FB19

SERCLK

FB5

TRIGIN

FBCLKQIN15 QIN13 QIN7

POWER PIN GROUND PIN

SIGNAL PIN THERMAL BALL

NC (Do not connect)

Pin Descriptions

NAME TYPE DESCRIPTION

POWER SUPPLY

VCCC - Positive Device Core Power Supply Voltage, 1.8V ±0.18V.

VCCIO - Positive Device Input/Output Power Supply Voltage, 3.3V ±0.165V.

GND - Common Ground, 0V

MICROPROCESSOR INTERFACE AND CONTROL

CLK I Input Clock. Rising edge drives all of the devices synchronous operations, except feedback capture.

RESET

I Reset. (Active Low). Asserting reset will clear all configuration registers to their default values, reset all internal

states, and halt all processing.

P<15:0> I/O 16-bit bi-directional data bus that operates with A<5:0>, CS

internal control registers. When the host system asserts CS under all other conditions, it is an input bus. Bit 15 is the MSB.

, RD, and WR to write to and read from the devices and RD simultaneously, P<15:0> is an output bus,

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Pin Descriptions (Continued)

NAME TYPE DESCRIPTION

A<5:0> I 6-bit address bus that operates with P<15:0>, CS, RD, and WR to write to and read from the devices internal

control registers. Bit 5 is the MSB.

BUSY

EXTERNAL SERIAL INTERFACE

SERCLK O Serial Clock. Clock signal provided to external device for serial input and output, derived from rising edge of

SERSYNC O Serial Sync. Active high single-cycle pulse that is time coincident with the first sample of the 32-bit serial data

SEROUT O Serial Output. Output data bit for the serial interface. Derived from the rising edge of CLK.

SERIN I Serial Input .In put d at a bi t for se ria l int erfa ce. Derived from rising ed ge of C LK.

FEEDBACK INTERFACE

FB<19:0> I Feedback Input Data. Parallel or serial data to be stored in the feedback memory. In parallel mode, all 20-

FBCLK I Input clock used for sampling the FB<19:0> pins.

TRIGGER INTERFACE

TRIGIN I Trigger input. Hardwired trigger source to be used to trigger an input/feedback capture. Sampled internally

TRIGOUT O Trigger output. Indicated that the capture system has been triggered, either internally or externally.

DATA INPUT

IIN<17:0> I I input data. Real component of the complex input sample when input format is parallel. Alternating real and

QIN<17:0> I Q input data. Imaginary component of the complex input sample when input format is parallel. Unused in serial

ISTRB I I data strobe. (active high). Used in the muxed input format. When asserted, the input data buses contains valid

CLKOUT O Input data clock. Output clock for the data source driving the IIN<17:0> and QIN<17:0> inputs. Input data

DATA OUTPUT

IOUT<17:0> I I output data. Real component of the complex output sample driven by the rising edge of CLK. Selectable as

QOUT<17:0> I Q output data. IMaginary component of the complex output sample driven by the rising edge of CLK. Selectable

TEST ACCESS

DCTEST O DC tree output. NAND tree output for DC threshold test. Do not connect for normal operation.

JTAG TEST ACCESS PORT

TMS I JTAG Test Mode Select. Internally pulled up.

TDI I JTAG Test Data In. Internally pulled up.

TCK I JTAG Test Clock.

TRST I JTAG Test Reset (Active Low). Internally pulled-up.

TDO O JTAG Test Data Out.

I Chip Select. (active low). Enables device to respond to µP access by enabling read or write operations. I Write Strobe, (active low). The data on P<15:0> is written to the destination selected by A<5:0> on the rising

edge of WR

I Read Strobe (Active Low). The d a t a at the ad d r e s s selected by A(5:0) i s placed on P < 1 5:0> when R D is

asserted (low) and CS

O µP Busy. (Active Low) Indicates that the µP interface is busy. The device asserts BUSY during a read operation

to indicate that the output data on P<15:0> is not ready, and it asserts this signal during a write operation to indicate that it is not available for another read or write operation yet.

CLK.

frame. Derived from by rising edge of CLK.

bits are stored on the rising edge of FBCLK. In serial mode, bit 0 is serial input data and bit 1 is serial sync, sampled at the rising edge of FBCLK.

with rising edge of CLK.

imaginary when input format is muxed. Selectable as 2’s complement or offset binary.

input format.

I data.

busses sampled on the rising edge of CLK that generates the rising edge of CLKOUT.

2’s complement or offset binary.

as 2’s complement or offset binary.

when CS is asserted (low).

is asserted (low).

ISL5239

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Functional Description

The ISL5239 is a full-featured digital pre-distortion part featuring a high-performance lookup-table based predistortion (PD) processing unit. It includes an interpolator for upsampling and supports all varieties of upconversion architectures with a programmable correction filter for equalization including both sin(x)/x correction and removal of frequency response imbalance between quadrature paths. It also features gain, phase, and offset compensation for direct upconversion, digital IF output for heterodyning, and input/output capture memories with internal/external triggering capabilities to facilitate closedloop feedback processing. System implementation is typically as shown in Figure 1. Although the power detect feedback is shown with one Analog to Digital Converter (ADC), coherently demodulated feedback signalsLO configurations with 1 or 2 ADC’s are also supported.

The block diagram on page 1 shows the internal functional units within the ISL5239. In the following sections each functional unit is described. The operation of the ISL5239 is controlled by the register map listed in Table 3. Detailed descriptions for each control/status register are given in Tables 4 through 48. The control/status registers are ref erred to in the discussion below.

The clock divider generates the CLKOUT signal which is used to clock data from the input signal source. Typical input sources include the ISL5217 quad programmable upconverter, which is designed to operate seamlessly with the ISL5239.

The interpolation factor is selectable in control word 0x02, bits 6:4 as x1, x2, x4, and x8. The x1 mode bypasses all three half-band filters. The x2 mode utilized HB1 and bypasses HB2 and HB3. The x4 mode utilized HB1 and HB2 and bypasses HB3. Finally, the x8 mode utilizes all three HBFs. Saturation status bits are provided for each of the three HBFs in the status register 0x03.

Input data rates up to the CLK rate are supported, based on the requirement CLK >= Fs * IP, where Fs is the input rate of the incoming data and IP is the interpolation factor selected in control word 0x02.

BYPASS BYPASS

HALF BAND

FILTER

HALF BAND

FILTER

I Q

BYPASS

IIN<17:0>

QIN<17:0>

FIGURE 2. INPUT FORMATTER AND INTERPOLAT OR

BLOCK DIAGRAM

HALF BAND

FILTER

INPUT

FORMATTER

FIGURE 1. SYSTEM OVERVIEW

Input Formatter and Interpolator (IFIP)

The Input Formatter and Interpolator interfaces to the data source to provide for parallel data input via the IIN<17:0>, QIN<17:0> busses, or serial input via the IIN<17:0> input bus. In parallel input mode, both 18-bit input busses are used to allow for parallel I and Q sample loading. In serial mode, the data is input via the IIN<17:0> bus only, as the I sample followed by the Q sample with the ISTRB input asserted with each I sample. In this mode, the QIN<17:0> bus is not utilized. The input data format is selectable as either two’s complement or offset binary.

The Interpolator function is necessary because predistorting a signal results in a much wider bandwidth signal (typically 5x to 7x wider). The Input Formatter and Interpolator is depicted in Figure 2.

Each half-band filter performs a x2 interpolation by inserting one zero between each input data sample, causing the sampling frequency to double. The resulting zero-stuffed data is then low pass filtered to reject the upsampling image.

The half-band filter frequency responses are as shown in Figure 3.

-20

-40

-60

-80

MAGNITUDE (dB)

-100

-120

-140

FIGURE 3. x2, HB1 ENABLED FREQUENCY RESPONSE

HALFBAND FILTER 1 RESPONSE

0 0.1 0.2 0.3 0.4 0. 5 0.6 0.7 0.8 0.9 1

NORMALIZED FREQUENCY (NYQUIST=1)

Three interpolation rates (x2, x4, and x8) are supported by the cascade of three Half-Band (HB) Filters. The ISL5239 includes an on-chip clock divider to facilitate input clocking.

ISL5239

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-20

-40

-60

-80

MAGNITUDE (dB)

-100

-120

-140

FIGURE 3A. X4, HB1 AND HB2 ENABLED FREQUENCY

-20

-40

-60

-80

MAGNITUDE (dB)

-100

-120

-140

FIGURE 3B. X8, HB1-HB3 ENABLED FREQUENCY RESPONSE

HALFBAND FILTER 2 RESPONSE

0 0.1 0.2 0.3 0.4 0. 5 0.6 0.7 0.8 0.9 1

NORMALIZED FREQUENCY (NYQUIST=1)

RESPONSE

HALFBAND FILTER 3 RESPONSE

0 0.1 0.2 0.3 0.4 0. 5 0.6 0.7 0.8 0.9 1

NORMALIZED FREQUENCY (NYQUIST=1)

Pre-Distorter (PD)

The function of the Pre-distorter is to compute the magnitude of the input signal, look up a complex distortion vector based on the magnitude, and apply that distortion to the input signal.

The signal magnitude may be computed by any of three different methods: log of power, linear magnitude or linear power. The result is scaled and offset by programmable amounts and becomes the address into a Look-up Table (LUT).

Two LUTs are available, one of which is ‘live’ in the circuit and the other is offline and can be loaded via the processor interface. This configuration allo ws instantaneou s s witching of pre-distortion characteristics without unpredictable effects on the processed signal.

The LUTs contain a complex distortion vector, as well as complex delta values which interact with an external Thermal/Memory calculation circuit to predict the effects of temperature changes on the RF amplifier’s behavior and compensate. The average power into the amplifier is computed and transmitted serially off chip. The external circuits compute one or two memory effect coefficients which are combined with the complex delta values in the LUT to derive the final distortion vector. The distortion vector is a rectangular complex value which is multiplied with the input signal resulting in a magnitude based nonlinearity. Access to the LUT is optimized by the use of an auto incrementing address register which allows the tables to be updated with only one address register write operation. Control words 0x10 through 0x1d apply to the

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pre-distorter. The pre-distorter block diagram is shown in Figure 4.

FROM

IFIP

CM TEST

LUT ADDR AUTO INCR.

SERIAL INPUT EN.

PWR INTGR PER.

SER. OUTPUT EN.

INPUT OR TEST

TEST

FUNC. SEL.

OFFSET

SCALE

PD MAG.

LUT DATA I

LUT DATA Q

LUT DELTA DATA I

LUT DELTA DATA Q

ACTIVE LUT

LUT ADDR

COEF. B SELECT

PWR LOW

PWR HIGH

LUT

ADDRESS

CALCULATION

POWER

ADDR

LUT

DATA

POWER

INTEGRATOR

PAR. TO SERIAL

BYPASS

MEMORY EFFECT

COMPENSATION

COEF. A COEF. B

SERIAL TO PAR.

SERCLK

SERSYNC

SEROUT

EXTERNAL

MEMORY

EFFECTS

FPGA

PRE-D OR BYPASS

SERIN

FIGURE 4. PRE-DISTORTER BLOCK DIAGRAM

Serial Interface

The serial interface for the external memory effects calculation consists of outputs SERCLK, SERSYNC, and SEROUT and input SERIN. The serial output sends the 32bit unsigned average power off-chip for further processing. The data is transmitted via the SEROUT pin MSB first, with the first bit marked by a high pulse on the SERSYNC pin. The SERCLK rate is scaled such that 32 bits are transmitted in one period of the power integrator as controlled by register 0x18 bits 5:4. SEROUT is enabled by register 0x18 bit 12.

IF Converter (IFC)

The output of the pre-distorter is a complex baseband signal sampled at the system CLK rate. To provide greater system flexibility, the IF Converter function can change this in one of three different ways, providing frequency shifts, sample rate changes and complex to real conversions.

Real 1X

The real 1x operating mode shifts the signal up by Fs/4 and performs a complex to real conversion without changing the base sample rate. This mode has 1/2 the bandwidth of the original input signal, with the I output channel active and the Q output channel set to 0. The operation of the IF converter in this mode is shown in Figure 5.

BYPASS

FROM

FIGURE 5. IF CONVERTER IN REAL 1X MODE OPERATION

Real 2X

The real 2x operating mode converts complex to real at 2x the sample rate and shifts the signal up to Fs/2 (Fs/4 of the output rate). This mode has the same bandwidth as the original signal with the I channel carrying the first of twwo samples/clock and the Q channel carrying the second sample. The operation of the IF Converter in this mode is shown in Figure 6.

FROM

FIGURE 6. IF CONVERTER IN REAL 2X MODE OPERATION

HALF

BAND

FILTER

j(pi/2)(n)

BYPASS

HALF

BAND

FILTER

j(pi/2)(n)

Re{*}

-1

The SERIN receives the thermal compensation parameters from external processing using the same SERCLK and SERSYNC used by the SEROUT. The chip expects to receive 32 bits of data sequentially on the SERIN pin: the MSB of A, followed by the rest of A, then the MSB of B, followed by the rest of B. The SERIN is enabled by register 0x18 bit 8. When SERIN is disabled, registers 0x19 and 0x1a supply the A and B parameters for the thermal compensation calculations. See Figure 16 for a detailed timing diagram of the serial interface.

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The IF converter frequency response is as shown in Figure 7, with the folding effect shown in Figure 7A for the x2, Fs/4 upconverter case.

-20

-40

-60

-80

MAGNITUDE (dB)

-100

-120

-140

-20

-40

-60

IFC FILTER RESPONSE (x2 MODE)

0 0.1 0.2 0.3 0.4 0. 5 0.6 0.7 0.8 0.9 1

NORMALIZED FREQUENCY (NYQUIST=1)

FIGURE 7. x2, IFC FREQUENCY RESPONSE

IFC FILTER RESPONSE (x2 MODE, WITH FOLDING)

Correction Filter (CF)

To compensate for imperfections in the analog filtering which takes place after D/A conversion, the correction filter provides an independent 13-tap FIR filter on each channel. These filters may be programmed to remove differential group delay and ripple characteristics of external analog circuits including sin(x)/x correction and frequency response imbalance between the I and Q channels using either amplitude or group delay. This allows for correction of the two physically separate I and Q analog response paths from the DAC’s through the quadrature up-converter. It also provides correction of the bandpass response when operating in a complex frequency shifted IF mode. There are two possible correction fi lter modes.

Real 2X

When the IF Converter is set to generate 2x sampled real data, the Correction Filter must be reconfigured to process this data correctly. In this mode it effectively pro vides one 13tap block-mode filter when the coefficients for the two filters are programmed identically.

BYPASS

FROM

IFC

-1

I/Q FIRs

-1

-80

MAGNITUDE (dB)

-100

-120

-140 0 0.1 0.2 0.3 0.4 0. 5 0.6 0.7 0.8 0.9 1

NORMALIZED FREQUENCY (NYQUIST=1)

FIGURE 7A. x2, IFC FREQUENCY RESP. WITH FOLDING

Complex

The complex operating mode simply shifts the complex baseband signal up by Fs/4 without any filtering or real conversion. The operation of the IF converter in this mode is shown in Figure 8.

BYPASS

FROM

j(pi/2)(n)

FIGURE 8. IF CONVERTER IN COMPLEX MODE OPERATION

FIGURE 9. CORRECTION FILTER IN REAL 2X MODE

Complex or Real 1x

When configured for operation in the complex mode, one 13tap filter is provided for each the I and Q channels. In Real 1x mode, the Q channel is not used.

BYPASS

FROM

IFC

I-CHAN

FIR

Q-CHAN

FIR

FIGURE 10. CORRECTION FILTER IN COMPLEX MODE

Output Data Conditioner (ODC)

The Output Data Conditioner can apply I/Q balance corrections, DC offset corrections and output format conversions.

To compensate for gain/phase imperfections in external analog modulation circuits which can result in poor image rejection and reduced dynamic range, the ODC provides an I/Q balance corrector. The I/Q balance corrector provides four coefficients to control the magnitude of the direct and

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cross-coupled term on both the I and Q channels. Typical implementation is as shown in Figure 10.

FIGURE 11. IMBALANCE CORRECTION

The Output formatter also provides DC offset correction to 1/4 LSB for 18-bit outputs to reduce analog DC offsets introduced in external D/A conversion and modulation circuits which can degrade system performance by causing carrier feed through in complex baseband systems, or spurs at DC for IF systems.

The ODC also provides programmable output precision 8 to 18-bits, with unbiased (convergent) rounding, since practical system designs will require D/A converters with fewer than 18-bits. Internal accuracy is in excess of 18-bits, and utilizes 20-bit data paths in critical areas. Additionally, both two’s complement and offset binary formats are supported.

Capture Memory (CM)

The Capture Memory allows the capture and viewing of data from various points in the chip. The primary function is to capture the digital signals coming into the pre-distorter. The CM also provides a secondary mode, as it can provide stimulus directly to the pre-Distorter. The CM is comprised of both the Input and the Feedback Memories. The processor interface provides the access to view, input, and alter the memory data. Synchronized (triggered) capture of both input and feedback signals is a typical requirement of adaptive digital pre-distortion systems.

Input Memory

The input capture memory observes the signals going into the amplifier. The 2K deep memory grabs complex samples of data at one of three possible locations, either at the input to the pre-distorter, the output of the pre-distorter, or from its magnitude calculation. In addition to capturing input data, this memory may also be configured as a data source. The input capture memory may be pre-loaded with user defined data and ‘played’ into the pre-distorter to stimulate the system with signals that will elicit a desired response.

Feedback Memory

The feedback memory allows the user to capture data from an external system and to view the memory through the processor interface. The feedback memory is used to observe the signals coming out of the amplifier. The 1K deep memory grabs 20-bit data, either in parallel or serial format. The feedback capture memory has its own clock input, FBCLK, which must be synchronously derived from CLK and meet the timing requirements.

Capture operations may be triggered by an external signal (TRIGIN), by magnitude threshold crossings detection programmed in the magnitude threshold maximum and minimum values, or by system software writing to the processor trigger bit in control word 0x04, bit 6. Separate programmable delays of up to 32k samples are provided for both input memory and feedback capture, allowing system delays to be calibrated out for optimum alignment prior to analysis. A TRIGOUT output is provided to indicates when a capture operation has begun.

The processor interface to the capture memories is designed to minimize the time required for loading/unloading. Although access to the memories takes place through indirect address and data registers, auto incrementing of the address is supported so the address only needs to be written once to access the entire memory. The capture memory is as shown in Figure 13.

TRIGIN

MAG COMP

IFC I,Q

PD I,Q

PD MAG

CM TEST I,Q

MEMORY SELECT

TRIG SEL

INPUT DELAY

COUNT

INPUT

SEL STATE

DATA ADDR

INPUT

CAPTURE

MEMORY 2K

FIGURE 12. CAPTURE MEMORY BLOCK DIAGRAM

TRIG

INPUT

uP INTERFACE

STATE

FB DELAY COUNT

ADDR DATA

FEEDBACK

CAPTURE

MEMORY 1K

FORMAT

FBCLK

FB<19:0>

Memory Modes and Programming Instructions

Unless noted, the following discussion applies to both the input memory and feedback memory operations. Prior to invoking the memory to capture or send data, the control word 0x06, bits 14:0 input trigger delay counter, 0x08 bits 14:0 feedback trigger delay count, 0x05, bits 10:0 input length, 0x04, bits 2:1 input memory datain source or 0x04, bit 8 feedback input format, and 0x04, bits 5:4 trigger select registers must be loaded.

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