intersil ISL5216 DATA SHEET

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ISL5216

Data Sheet July 13, 2007

Four-Channel Programmable Digital Downconverter

The ISL5216 Quad Programmable Digital Downconverter (QPDC) is designed for high dynamic range applications such as cellular basestations where multiple channel processing is required in a small physical space. The QPDC combines into a single package a set of four channels which include: digital mixers, a quadrature carrier NCO, digital filters, a resampling filter, a Cartesian-to-polar coordinate converter and an AGC loop.

The ISL5216 accepts four channels of 16-bit fixed or up to 14-bit mantissa/3-bit exponent floating point real or complex digitized IF samples which are mixed with local quadrature sinusoids. Each channel carrier NCO frequency is set independently by the microprocessor. The output of the mixers are filtered with a CIC and FIR filters, with a variety of decimation options. Gain adjustment is provided on the filtered signal. The digital AGC provides a gain adjust range of up to 96dB with programmable thresholds and slew rates. A cartesian to polar coordinate converter provides magnitude and phase outputs. A frequency discriminator is also provided to allow FM demodulation. Selectable outputs include I samples, Q samples, Magnitude, Phase, Frequency and AGC gain. The output resolution is selectable from 4-bit fixed point to 32-bit floating point.

FN6013.3

Features

• Up to 95MSPS Input

• Four Independently Programmable Downconverter Channels in a single package

• Four Parallel 17-Bit Inputs providing 16-bit fixed or one of several 17-bit floating point formats

• 32-Bit Programmable Carrier NCO with > 115dB SFDR

• 110dB FIR Out of Band Attenuation

• Decimation from 4 to >65536

• 24-bit Internal Data Path

• Digital AGC with up to 96dB of Gain Range

• Filter Functions

- 1- to 5-Stage CIC Filter

- Halfband Decimation and Interpolation FIR Filtering

- Programmable FIR Filtering

- Resampling FIR Filtering

• Cascadable Filtering for Additional Bandwidth

• Four Independent Serial Outputs

• 2.5V Core, 3.3V I/O Operation

• Pb-Free Plus Anneal Available (RoHS Compliant)

Output bandwidths in excess of 1MHz are achievable using a single channel. Wider bandwidths are available by cascading or polyphasing multiple channels.

Applications

• Narrow-Band TDMA through IS-95 CDMA Digital Software Radio and Basestation Receivers

• Wide-Band Applications: W-CDMA and UMTS Digital Software Radio and Basestation Receivers

Ordering Information

PART NUMBER PART MARKING TEMP RANGE (°C) PACKAGE PKG. DWG. #

ISL5216KI ISL5216KI -40 to +85 196 Ld 0.8mm BGA V196.12x12 ISL5216KI-1 ISL5216KI-1 -40 to +85 196 Ld 1.0mm BGA V196.15x15 ISL5216KIZ (Note) ISL5216KIZ -40 to +85 196 Ld 0.8mm BGA (Pb-free) V196.12x12 ISL5216KI-1Z (Note) ISL5216KI-1Z -40 to +85 196 Ld 1.0mm BGA (Pb-free) V196.15x15

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

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μP

TEST

INPUT SELECT,

FORMAT,

DEMUX

ISL5216

LEVEL

DETECTOR

SCLK

A(15:-1)

ENIA

B(15:-1)

ENIB

C(15:-1)

ENIC

D(15:-1)

ENID

INPUT SELECT,

FORMAT,

DEMUX

INPUT SELECT,

FORMAT,

DEMUX

INPUT SELECT,

FORMAT,

DEMUX

INPUT SELECT,

FORMAT,

DEMUX

NCO/MIXER/CIC

CHANNEL 0

NCO/MIXER/CIC

CHANNEL 1

NCO/MIXER/CIC

CHANNEL 2

NCO/MIXER/CIC

CHANNEL 3

BUS

ROUTING

FIR FILTERS,

AGC,

CARTESIAN-TO-POLAR

COORDINATE

CONVERTER

FIR FILTERS,

AGC,

CARTESIAN-TO-POLAR

COORDINATE

CONVERTER

FIR FILTERS,

AGC,

CARTESIAN-TO-POLAR

COORDINATE

CONVERTER

FIR FILTERS,

AGC,

CARTESIAN-TO-POLAR

COORDINATE

CONVERTER

SYNCA

SD1A

SD2A

SYNCB

SD1B

SD2B

OUTPUT SELECT,

FORMAT,

SERIALIZE

SYNCC

SD1C

SD2C

SYNCD

SD1D

SD2D

CLK RESET SYNCI

SYNCO SYNCI0

SYNCI1 SYNCI2 SYNCI3

TRST TCLK

TMS TDI TDO

P(15:0) ADD(2:0) WR

μP INTERFACE

RD/WR

DSTRB

INTRPT

μP MODE

FN6013.3

July 13, 2007

Pinout

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ISL5216

196 LD BGA

TOP VIEW

123456789 1110

B14

A0 P13RESET

B15 P12

B13 P10GND

B11 GND P8VCC1

B9 VCC1 P6GND

CLK

VCC2

B7P2GND

B5 GND P0VCC1

B3 WR

C15

B12

ENIB

C12C6C4C2C0

C14 C10 C8 GND VCC1 GND

A10 GNDVCC1

Am1 TDO

TMS

B10

TCLK

GND

TRST

B4 P1

Bm1

VCC1

SD1B

SYNCI3

TDI Cm1 Dm1

D15 D3D1D0

VCC1

ENIC

D13

SCLK SYNCCSYNCBSYNCA SYNCD SYNCI SYNCOA7 A9 A11 A13 A15 SD1A

SD1CGNDVCC2GND ADD0

SD2C SD2DSD2B

ADD2

SYNCI2

SYNCI1

SYNCI0

μP MODE

D11 ENID

VCC2 D9GND

D12 D10D14C13

SD1D

INTRPT

D8 D6 D4C11C9C7C5C3C1

13 14

ADD1

P15ENIA A12 A14 SD2A

VCC2P11

GND P4

VCC1P3

RDCE

D5 D2

P14

POWER PIN GROUND PIN

VCC1 = +2.5V CORE SUPPLY VOLTAGE VCC2 = +3.3V I/O SUPPLY VOLTAGE

SIGNAL PIN THERMAL BALL

NC (NO CONNECTION)

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ISL5216

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Pin Descriptions

NAME TYPE DESCRIPTION

POWER SUPPLY

VCC1 - Positive Power Supply Voltage (core), 2.5V ±0.125 VCC2 - Positive Power Supply Voltage (I/O), 3.3V ±0.165

GND - Ground, 0V.

INPUTS

A(15:0), Am1 I Parallel Data Input bus A. Sampled on the rising edge of clock when ENIA

B(15:0), Bm1 I Parallel Data Input bus B. Sampled on the rising edge of clock when ENIB

C(15:0), Cm1 I Parallel Data Input bus C. Sampled on the rising edge of clock when ENIC

D15 I Parallel Data Input D15 or tuner channel 0 COF. D14 I Parallel Data Input D14 or tuner channel 0 COFSync. D13 I Parallel Data Input D13 or tuner channel 0 SOF. D12 I Parallel Data Input D12 or tuner channel 0 SOFSync. D11 I Parallel Data Input D11 or tuner channel 1 COF. D10 I Parallel Data Input D10 or tuner channel 1 COFSync.

D9 I Parallel Data Input D9 or tuner channel 1 SOF. D8 I Parallel Data Input D8 or tuner channel 1 SOFSync. D7 I Parallel Data Input D7 or tuner channel 2 COF. D6 I Parallel Data Input D6 or tuner channel 2 COFSync. D5 I Parallel Data Input D5 or tuner channel 2 SOF. D4 I Parallel Data Input D4 or tuner channel 2 SOFSync. D3 I Parallel Data Input D3 or tuner channel 3 COF. D2 I Parallel Data Input D2 or tuner channel 3 COFSync. D1 I Parallel Data Input D1 or tuner channel 3 SOF.

D0 I Parallel Data Input D0 or tuner channel 3 SOFSync. Dm1 I Parallel Data Input Dm1 for extended floating point input modes. Dm1 has internal weak pull-down. ENIA

ENIB

ENIC

ENID

CONTROL

CLK I Input clock. All processing in the ISL5216 occurs on the rising edge of CLK.

SYNCI I Global synchronization input signal. Used to align the processing with an external event or with other ISL5216

SYNCI0 I Synchronization input signal for channel 0. Same functions as SYNCI but connects only to channel 0. This pin

SYNCI1 I Synchronization input signal for channel 1. Same functions as SYNCI but connects only to channel 1. This pin

SYNCI2 I Synchronization input signal for channel 2. Same functions as SYNCI but connects only to channel 2. This pin

I Input enable for Parallel Data Input bus A. Active low. This pin enables the input to the part in one of two modes,

I Input enable for Parallel Data Input bus B. Active low. This pin enables the input to the part in one of two modes,

I Input enable for Parallel Data Input bus C. Active low. This pin enables the input to the part in one of two

I Input enable for Parallel Data Input bus D. Active low. This pin enables the input to the part in one of two

weak pull-down.

gated or interpolated. In gated mode, one sample is taken per CLK when ENI

modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI

or HSP50216 devices. SYNCI can update the carrier NCO, reset decimation counters, restart the filter compute engine, and restart the output section among other functions. For most of the functional blocks, the response to SYNCI is programmable and can be enabled or disabled. This signal is connected to all four channels and is included for backward compatibility with HSP50216 designs.

is internally pulled low to allow it to be left unconnected.

is active (low). Am1 has internal

is active (low). Bm1 has internal

is active (low). Cm1 has internal

is asserted.

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ISL5216

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Pin Descriptions (Continued)

NAME TYPE DESCRIPTION

SYNCI3 I Synchronization input signal for channel 3. Same functions as SYNCI but connects only to channel 3. This pin

SYNCO O Synchronization Output Signal. The processing of multiple ISL5216 or HSP50216 devices can be

RESET

JTAG

TDO O Test data out

TDI I Test data in. Contains weak internal pull-up.

TMS I Test mode select. Contains weak internal pull-up.

TCLK I Test clock. Contains weak internal pull-down. TRST

OUTPUTS

SD1A O Serial Data Output 1A. A serial data stream output which can be programmed to consist of I1, Q1, I2, Q2,

SD2A O Serial Data Output 2A. This output is provided as an auxiliary output for Serial Data Output 1A to route data to

SD1B O Serial Data Output 1B. See description for SD1A. SD2B O Serial Data Output 2B. See description for SD2A. SD1C O Serial Data Output 1C. See description for SD1A. SD2C O Serial Data Output 2C. See description for SD2A. SD1D O Serial Data Output 1D. See description for SD1A. SD2D O Serial Data Output 2D. See description for SD2A. SCLK O Serial Output Clock. Can be programmed to be at 1, 1/2, 1/4, 1/8, or 1/16 times the clock frequency. The

SYNCA O Serial Data Output 1A sync signal. This signal is used to indicate the start of a data word and/or frame of data.

SYNCB O Serial Data Output 1B sync signal. This signal is used to indicate the start of a data word and/or frame of data.

SYNCC O Serial Data Output 1C sync signal. This signal is used to indicate the start of a data word and/or frame of data.

SYNCD O Serial Data Output 1D sync signal. This signal is used to indicate the start of a data word and/or frame of data.

MICROPROCESSOR INTERFACE

P(15:0) I/O Microprocessor Interface Data bus. See Microprocessor Interface Section. P15 is the MSB.

ADD(2:0) I Microprocessor Interface Address bus. ADD2 is the MSB. See Microprocessor Interface Section. Note: ADD2

DSTRB

I Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default values.

I Test reset. Active low. Contains weak internal pull-down.

I Microprocessor Interface Write or Data Strobe Signal. When the Microprocessor Interface Mode Control, μP

is internally pulled low to allow it to be left unconnected.

synchronized by tying the SYNCO from one ISL5216 device (the master) to the SYNCI of all the ISL5216/HSP50216 devices (the master and slaves).

magnitude, phase, frequency (dφ/dt), AGC gain, and/or zeros. In addition, data outputs from Channels 0, 1, 2 and 3 can be multiplexed into a common serial output data stream. Information can be sequenced in a programmable order. See Serial Data Output Formatter Section and Microprocessor Interface Section.

a second destination or to output two words at a time for higher sample rates. SD2A has the same programmability as SD1A except that floating point format is not available. See Serial Data Output Formatter

Section and Microprocessor Interface Section.

polarity of SCLK is programmable.

The polarity and position of SYNCA is programmable.

The polarity and position of SYNCB is programmable.

The polarity and position of SYNCC is programmable.

The polarity and position of SYNCD is programmable.

is not used but designated for future expansion.

MODE, is a low data transfers (from either P(15:0) to the internal write holding register or from the internal write holding register to the target register specified) occur on the low to high transition of WR (low). When the μP MODE control is high this input functions as a data read/write strobe. In this mode with

low data transfers (from either P(15:0) to the internal write holding register or from the internal write

RD/WR holding register to the target register specified) occur on the low to high transition of Data Strobe. With RD/WR high the data from the address specified is placed on P(15:0) when Data Strobe is low. See Microprocessor Interface Section.

when CE is asserted

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ISL5216

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Pin Descriptions (Continued)

NAME TYPE DESCRIPTION

RD/WR

μP MODE I Microprocessor Interface Mode Control. This pin is used to select the Read/Write mode for the Microprocessor

INTRPT

I Microprocessor Interface Read or Read/Write Signal. When the Microprocessor Interface Mode Control, μP

I Microprocessor Interface Chip Select. Active low. This pin has the same timing as the address pins.

O Microprocessor Interrupt Signal. Asserted for a programmable number of clock cycles when new data is

MODE, is a lo w the data from the address specified is placed on P(15:0) when RD is asserted (low). When the μP MODE control is high this input functions as a Read/Write is read from P(15:0) when high or written to the appropriate register when low. See Microprocessor Interface Section.

Interface. Internally pulled down. See Microprocessor Interface Section.

available on the selected Channel.

is asserted (low) and CE

control input. Data

Functional Description

The ISL5216 is a 4-channel digital receiver integrated circuit offering exceptional dynamic range and flexibility. Each of the four channels consists of a front-end NCO, digital mixer, and CIC-filter block and a back-end FIR, AGC and Cartesian to polar coordinate-conversion block. The parameters for the four channels are independently programmable. Four 17-bit parallel data input busses (A(15:-1), B(15:-1), C(15:-1) and D(15:-1)) and four pairs of serial data outputs (SDxA, SDxB, SDxC, and SDxD; x = 1 or 2) are provided. Each input can be connected to any or all of the internal signal processing channels, Channels 0, 1, 2 and 3. The output of each channel can be routed to any of the serial outputs. Outputs from more than one channel can be multiplexed through a common output if the channels are synchronized. The four channels share a common input clock and a common serial output clock, but the output sample rates can be synchronous or asynchronous. Bus multiplexers between the front end and back end sections provide flexible routing between channels for cascading back-end filters or for routing one front end to multiple back ends for polyphase filtering or systolic arrays (to provide wider bandwidth filtering). A level detector is provided to monitor the signal level on any of the parallel data input busses, facilitating microprocessor control of gain blocks prior to an A/D converter.

Each front end NCO/digital mixer/CIC filter section includes a quadrature numerically controlled oscillator (NCO), digital mixer, barrel shifter and a cascaded-integrator-comb filter (CIC). The NCO has a 32-bit frequency control word for

22.1mHz tuning resolution at an input sample rate of 95MSPS. The SFDR of the NCO is >115dB. The CIC filter order is programmable between 1 and 5 and the CIC decimation factor can be programmed from 4 to 512 for 5 order, 2048 for 4

or 2nd order filters.

order, 32768 for 3rd order, or 65536 for

Each channel back end section includes an FIR processing block, an AGC and a cartesian-to-polar coordinate converter. The FIR processing block is a flexible filter compute engine that can compute a single FIR or a set of cascaded decimating, interpolating or resampling filters. A single filter in a chain can have up to 256 taps and the total number of taps in a set of filters can be up to 384 provided that the decimation is sufficient. The ISL5216 calculates two taps per clock (on each channel) for symmetric filters, generally making decimation the limiting factor for the number of taps available. The filter compute engine supports a variety of filter types including decimation, interpolation and resampling filters. The coefficients for the programmable digital filters are 22 bits wide. Coefficients are provided in ROM for several halfband filter responses and for a resampler. The AGC section can provide up to 96dB of either fixed or automatic gain control. For automatic gain control, two settling modes and two sets of loop gains are provided. Separate attack and decay slew rates are provided for each loop gain. Programmable limi ts allow the user to select a gain range less than 96dB. The outputs of the cartesian-to-polar coordinate conversion block, used by the AGC loop, are also provided as outputs to the user for AM and FM demodulation.

The ISL5216 supports both fixed and floating point parallel data input modes. The floating point modes support gain ranging A/D converters. Gated, interpolated and multiplexed data input modes are supported. The serial data output word width for each data type can be programmed to one of ten output bit widths from 4-bit fixed point through 32-bit IEEE 754 floating point.

The ISL5216 is programmed through a 16-bit microprocessor interface. The output data can also be read via the microprocessor interface for all channels that are synchronized. The ISL5216 is specified to operate to a maximum clock rate of 95MSPS over the industrial temperature range (-40°C to 85°C). The I/O power supply voltage range is 3.3V ± 0.165V while the core power supply voltage is 2.5V ± 0.125V. The I/Os are 5V tolerant.

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Input Select/Format Block

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ISL5216

(IWA *000 - 12

or GWA F804 - 12)

μP TEST

(GWA F807 - 15:0)

TESTENBIT

(IWA *000 - 11

or GWA F804 - 11)

TESTENSTRB

(GWA F808)

A(15:-1)

ENIA

B(15:-1)

ENIB

C(15:-1)

ENIC

D(15:-1)

ENID

NOTE: ENI* SIGNALS

ARE ACTIVE HIGH

(INVERTED AT THE I/O PAD)

EXTERNAL DATA

INPUT SELECT

(IWA *000 - 14:13

GWA F804 - 14:13)

TEST ENI

SELECT

TESTEN

MUX

CARRIER OFFSET

FREQUENCY (COF)

EXTERNAL/TEST

SELECT

(IWA *000 - 15

or GWA F804 - 15)

15:0

ENI

OFFSET BINARY

TWO’s COMPLEMENT

(IWA *000 - 10

or GWA F804 - 10)

15:0

FORMAT

MUX

INPUT ENABLE HOLD OFF

(ENABLED BY SYNCI)

(GWA F802 - 30)

ENABLE PN

(IWA *000 - 0)

COF TO CARRIER NCO/MIXER

11/3, 12/3, 13/3

14/2, 14/3, 15/2, 16/1

(IWA *000 or

GWA F804 - 17:16, 8:7)

FLOATING POINT

FIXED POINT

PROGRAMMABLE

DE-MULTIPLEX CONTROL (0-7)

(IWA *000 - 6:4

or GWA F8O4 - 6:4)

OFFSET FREQUENCY

DELAY

PN TO CARRIER NCO/MIXER

FIXED POINT

FLOATING POINT

(IWA *000 - 9

or GWA F804 - 9)

MUX

RESAMPLER

(SOF)

R E G

INTERPOLATED/GATED

MODE

(IWA *000 - 3

or GWA F804 - 3)

15:0

DATA TO NCO/MIXER OR

LEVEL DETECTOR

DATA SAMPLE ENABLE

SOF TO RESAMPLER NCO

COF SYNC

ENABLE

COF

(1WA *000 - 2)

Each front end block and the level detector block contains an input select/format block. A functional block diagram is provided in the above figure. The input source can be any of the four parallel input busses (see Microprocessor Interface Section Table 1, IWA *000h) or a test register loaded via the processor bus (see Microprocessor Interface Section, GWA register F807h).

The input to the part can operate in a gated or interpolated mode. Each input data bus has an input enable (ENIx

,x=A, B, C or D). In the gated mode, one input sample is processed per clock that the ENIx Processing is disabled when ENIx

signal is asserted (low).

is high. The ENIx signal is pipelined through the part to minimize delay (latency). In the interpolated mode, the input is zeroed when the ENIx

signal is high, but processing inside the part continues. This mode inserts zeros between the data samples, interpolating the input data stream up to the clock rate. On reset, the part is set to gated mode and the input enables are disabled. The

COF SYNC TO CARRIER NCO/MIXER

SOF SYNC

ENABLE

SOF

(IWA *000 - 1)

inputs are enabled by the first global SYNCI signal or SYNCIx signal, where X = 0, 1, 2 or 3.

The input section can select one channel from a multiplexed data stream of up to eight channels. The input enable is delayed by zero to seven clock cycles to enable a selection register . Th e re gi ster following the selection register is enabled by the non-delayed input enable to realign the processing of the channels. The one-clock-wide input enable must align with the data for the first channel. The desired channel is then selected by programming the delay. A delay of zero selects the first channel, a delay of one selects the second, etc.

The parallel input busses are 17 bits wide allowing for up to 16 bits of fixed-point data or 14 bits of mantissa with three bit s of exponent for floating-point data. The input format may be twos complement or offset binary format in either fixed or floating

SOF SYNC TO RESAMPLER NCO

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July 13, 2007

ISL5216

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point modes. The floating point modes and the mapping of the parallel 17-bit input format is discussed below.

as those which follow it in the tables below use the CIC’s barrel shifter to provide the gain. This places a limit on the CIC’s largest available decimation. As an example, assume

Floating Point Input Mode Bit Mapping

The input bit weighting for fixed point inputs on busses A, B, C, and D is:

bit 15 (MSB): 2

, bit 14: 2-1, bit 13: 2-2, ..., bit 0: 2

For floating point modes, the least significant two or three bits are used as exponent bits (See Floating Point Input Mode Bit Mapping Tables).

The first three floating point modes shown below are included for backward compatibility with the HSP50216 and th eir functionality remains unchanged. The 14-bit mantissa/2-bit exponent mode present in the HSP50216 has been extended

-15

the CIC is set for 5th order and the decimation needs to be

300. The CIC’s gain, 300 shifter with a shift factor of 45 - ceil(log

, is compensated for in the barrel

(3005)) = 3 where

shifts are from LSB towards MSB and a shift of 45 corresponds to no attenuation. If the shift factor is set as 0 in this example, there is room for 3 * 6 = 18dB of gain. Raising the CIC decimation lowers the shift factor (to further attenuate the CIC input signal) and limits the available gain range. This CIC decimation/floating point gain range trade off is hand led automatically by the evaluation board software. Additi onal information on the CIC can be found in the CIC Filter section of this data sheet.

from a 12dB range to 18dB in the ISL5216. This mode as well

Floating Point Input Mode Bit Mapping Tables

((

EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING

X(2:0) = 000 0 X15 X15 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X(2:0) = 001 6 X15 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X(2:0) = 010 12 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X(2:0) = 011 18 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 X(2:0) = 100 24 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 X(2:0) = 101

(Note 1)

NOTES:

1. Or 110 or 111, the exponent input saturates at 101.

2. “Xnn” = input A, B, C, or D bit nn.

3. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 0.

11-BIT MODE: 11 TO 13-BIT MANTISSA (15:3), 3-BIT EXPONENT (2:0), 30dB EXPONENT RANGE (Note 3)

30 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 0

12-BIT MODE: 12 TO 13-BIT MANTISSA (15:3), 3-BIT EXPONENT (2:0), 24dB EXPONENT RANGE (Note 5)

EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING

X(2:0) = 000 0 X15 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X(2:0) = 001 6 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X(2:0) = 010 12 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 X(2:0) = 011 18 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 X(2:0) = 100

(Note 4)

NOTES:

4. Or 101, 110, or 111, the exponent input saturates at 100.

5. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 0, 0, 0 and 1 respectively.

24 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 0

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ISL5216

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13-BIT MODE: 13-BIT MANTISSA (15:3), 3-BIT EXPONENT (2:0), 18dB EXPONENT RANGE (Note 7)

EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING

X(2:0) = 000 0 X15 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X(2:0) = 001 6 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 X(2:0) = 010 12 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 X(2:0) = 011

(Note 6)

NOTES:

6. Or 100, 101, 110, or 111, the exponent input saturates at 011.

7. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 0, 0, 1 and 0 respectively.

EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING

X(1:0) = 00 0 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2 0 0 X(1:0) = 01 6 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2 0 0 X(1:0) = 10 12 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 0 0 X(1:0) = 11 18 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 0 0

NOTE:

8. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 0, 0, 1 and 1 respectively.

EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING

X(-1,1,0) = 0000 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2 0 0 X(-1,1,0) = 0016 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2 0 0 X(-1,1,0) = 010 12 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 0 0 X(-1,1,0) = 011 18 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2 0 0 X(-1,1,0) = 100 24 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 0 0 X(-1,1,0) = 101 30 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 0 0 X(-1,1,0) = 110 36 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2 0 0 X(-1,1,0) = 111 42 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2 0 0

NOTE:

9. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 1, 0, 1 and 1 respectively.

18 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 0

14-BIT MODE: 14-BIT MANTISSA (15:2), 2-BIT EXPONENT (1:0), 18dB MAXIMUM EXPONENT RANGE (Note 8)

14-BIT MODE: 14-BIT MANTISSA (15:2), 3-BIT EXPONENT (-1,1,0), 42dB MAXIMUM EXPONENT RANGE (Note 9)

11, 12, 13-BIT MODE: 11, 12, 13-BIT MANTISSA, 3-BIT EXPONENT (-1,1,0) (Note 10), 42dB MAXIMUM EXPONENT RANGE (Note 11)

EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING

X(-1,1,0) = 0000 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3 0 0 0 X(-1,1,0) = 0016 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3 0 0 0 X(-1,1,0) = 010 12 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 0 X(-1,1,0) = 011 18 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3 0 0 0 X(-1,1,0) = 100 24 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 0 X(-1,1,0) = 101 30 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0 0 X(-1,1,0) = 110 36 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3 0 0 0 X(-1,1,0) = 111 42 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3 0 0 0

NOTES:

10. For compatibility with legacy HSP50216 11, 12 and 13 bit floating point modes as well as the new ISL5216 modes, the most significant exponent

bit is taken as X2 OR’d with X-1. Either input may be used for the MSB of the exponent when the other is tied low.

11. T o select these modes, set IW A *000H/GWA F804H bits 17 and 16 to 1 and 0, respectively , and bit s 8 and 7 to 0 and 0 for 1 1/3, 0 and 1 for 12/3, and 1 and 0 for 13/3.

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ISL5216

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15-BIT MODE: 15-BIT MANTISSA (15:1), 2-BIT EXPONENT (-1, 0), 18dB MAXIMUM EXPONENT RANGE (Note 12)

EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING

000 0 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2X1 0 001 6 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2X1 0 010 12 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 0 011 18 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2X1 0

NOTE:

12. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 1, 1, 0 and 0 respectively.

16-BIT MODE: 16-BIT MANTISSA (15:0), 1-BIT EXPONENT (-1), 6dB MAXIMUM EXPONENT RANGE (Note 13)

EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING

X(-1) = 0 0 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 X(-1) = 1 6 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0

NOTE:

13. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 1, 1, 0 and 1 respectively.

Level Detector

An input level detector is provided to monitor the signal level on any of the input busses. The input bus, input format, and the level detection type are programmable (see Microprocessor Interface , GWA registers F804h, F805h and F806h). This signal level represents the wideband signal from the A/D and is useful for controlling gain/attenuation blocks ahead of the converter.

The supported monitoring modes include integrated magnitude (like the HSP50214 w/o the threshold) and leaky integration (Y

-16

or 2

(see GWA = F805h). The measurement interval can

n=Xn

xA+Y

x (1-A)) where A = 1, 2-8, 2

n-1

be programmed from 2 to 65537 samples (or continuous for the leaky integrator case). The output is 32 bits and is read via the μP interface.

Note that the accumulators in the input level detector are 32 bits wide. This may limit the integration range to as few as 512 samples (for a 42dB exponent range).

ABSOLUTE

VALUE

-12

0, -8, -12, -16

FIGURE 2. PEAK DETECTOR (See “Errata” on page 63)

BARREL SHIFTER

MODE NOT

BARREL SHIFTER

A > B

PPORTED

R E G

YN = A * X + (1 - A) * Y

R E

N-1

MSB

FIGURE 1. INTEGRATED MODE

BARREL SHIFTER

0, -8, -12, -16

ACCUMULATOR

0, -8, -12, -16

A =

BARREL SHIFTER

FIGURE 3. LEAKY INTEGRATOR

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ISL5216

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Complex Input Mode

In this mode, complex (I/Q) data can be input using two clock cycles with I input first and Q input second. The ENIx indicates the clock cycle when I is valid. The Q data is taken on either the next input clock or two clocks after I, as determined by IWA *000H bit 23. The complex multiply is done in two clock cycles: I * COS and I * SIN on the first clock and Q * (-SIN) and Q * COS on the second clock cycle. The first integrator of the CIC is enabled on both clock cycles to add the two products. The rest of the stages are enabled only on the first cycle.

In complex input mode, the input level detector uses only I samples for its magnitude computation.

The CIC decimation counter is programmed for two times the number of complex input samples. The exponent input must be the same for I and Q for the floating point modes.

See IWA *000h for details on controlling the complex input mode.

signal

NCO/Mixer

After the input select/format section, the samples are multiplied by quadrature sine wave samples from the carrier NCO. The NCO has a 32-bit frequency control, providing sub-hertz resolution at the maximum clock rate. The quadrature sinusoids have exceptional purity. The purity of the NCO should not be the determining factor for the receiver dynamic range performance. The phase quantization to the sine/cosine generator is 24 bits and the amplitude quantization is 19 bits.

The carrier NCO center frequency is loaded via the μP bus. The center frequency control is double buffered - the input is loaded into a center frequency holding register via the μP interface. The data is then transferred from the holding register to the active register by a write to a address IWA *006h or by a SYNCI signal, if loading via SYNCI is enabled. To synchronize multiple channels, the carrier NCO phase accumulator feedback can be zeroed on loading to restart all of the NCOs at the same phase. A serial offset frequency input is also available for each channel through the D(15:0) parallel data input bus (if that bus is not needed for data input). This is legacy support for HSP50210 type tracking signals. See IWA=*000 and *004 for carrier offset frequency parameters.

After the mixers, a PN (pseudo noise) signal can be added to the data. This feature is provided for test and to digitally reduce the input sensitivity and adjust the receiver range (sensitivity). The effect is th e same as increasing the noise figure of the receiver, reducing its sensitivity and overall dynamic range. For testing, the PN generator provides a wideband signal which may be used to verify the frequency response of a filter. The one bit PN dat a is scale d by a 16-bit programmable scale factor. The overall range for the PN is 0

to 1/4 full scale (see IWA = *001h). A gain of 0 disables the PN input. The PN value is formed as:

PN VALUE

-32-4............2-172-18

SSS X X XXXXXXXXXXXX X X

where S is the sign extension of the 16 bit PN gain register value (IWA = *001H) times the PN chip value and the 16 X’s refer to the PN gain register times the PN chip value.

The minimum, non-zero, PN value is 2 (-108dBFS) on each axis (-105dBFS total). For an input noise level of -75dBFS, this allows the SNR to be decreased in steps of 1/8dB or less. The I and Q PN codes are offset in ti me to decorrelate them. The PN code is selected and enabled in the test control register (F800h). The PN is added to the signal after the mix with the three sign bits aligned with the most significant three bits of the signal, so the maximum level is 12dBFS and the minimum, non-zero level is -108dBFS. The PN code can be 2

-1, 223-1 or 215-1 * 223-1.

-18

of full scale

CIC Filter

Next, the signal is filtered by a cascaded integrator/comb (CIC) filter. A CIC filter is an efficient architecture for decimation filtering. The power or magnitude squared frequency response of the CIC filter is given by:

πMf()sin

πf

⎛⎞

---- -

⎝⎠

max

⎛⎞ ⎜⎟

------------------------

Pf()

⎜⎟ ⎜⎟

sin

⎝⎠

where

M = Number of delays (1 for the ISL5216)

N = Number of stages

and R = Decimation factor.

The passband frequency response for first (N=1) though fifth (N=5) order CIC filters is plotted in Figure 13. The frequency axis is normalized to f sample rate. Figure 15 shows the frequency response for a

order filter but extends the frequency axis to fS/R = 3 (3 times the CIC output sample rate) to show alias rejection for the out of band signals. Figure 14 uses information from Figure 15 to provide the amplitude of the first (strongest) alias as a function of the signal frequency or bandwidth from DC. For example, with a 5 (signal frequency is 1/8 the CIC output rate) Figure 14 shows a first alias level of about -87 dB. Figure 14 is also listed in table form in Table 51 (CIC Passband and Alias Levels).

The CIC filter order is programmable from 0 to 5. The CIC may be bypassed by setting the CIC filter order to 0 (IWA = *004h bits 13:9 are all set equal to 1) and the CIC barrel shift (IWA = *004h bits 19:14) to 45 decimal. The CIC output rate must, however, be no more than CLK where CLK the device (see electrical specifications section).

is the maximum clock frequency available on

max

/R, making fS/R = 1 the CIC output

order CIC and fS/R = 0.125

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The integrator bit widths are 69, 62, 53, 44, and 34 for the

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first

through fifth stages, respectively, while the comb bit widths are all 32. The integrators are sized for decimation factors of up to 512 with five stages, 2048 with fou r stages, 32768 with three stages, and 65536 with one o r two stages. Higher decimations in the CIC should be avoided as they will cause integrator overflow. In the ISL5216, the integrators are slightly oversized to reduce the quantization noise at each stage.

A CIC filter has a gain of R and N is the number of stages. Because the CIC filter gain can become very large with decimation, an attenuator is provided ahead of the CIC to prevent overflow. The 24 bits of sample data are placed on the low 24 bits of a 69 bit bus (width of the first CIC integrator) for a gain of 2 barrel shifter then provides a gain of 2 before passing the data to the CIC. The overall gain in the pre-CIC attenuator can therefore be programmed to be any one of 48 values from 2 bits 19:14). This shift factor is adjusted to keep the total barrel shifter and CIC filter gain between 0.5 and 1.0. The equation which should be used to compute the necessary shift factor is:

, where R is the decimation factor

-45

to 247 inclusive

-45

to 4, inclusive (see IWA=*004,

. A 48 bit

ISL5216

Shift Factor = 45 - Ceiling(log CIC barrel shifts of greater than 45 will cause MSB bits to be

lost. Most of the floating point modes on the ISL5216 make use of the CIC barrel shifter for gain. This limits the maximum usable decimation. In particular, shift factor minus maximum exponent must be greater than or equal to zero. Maximum exponent ranges from 0 to 1, 3, or 7 for 1, 2 and 3 exponent bits, representing up to 6, 18, or 42dB of gain, respectively. See F loating Point Input Mode section for details.

(RN)).

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Back End Data Routing

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ISL5216

MAG: I

PATH 0

(4:0)

M U X

FROM

CIC

DESTINATION BIT MAP (BITS 28:18 OF FIR INSTRUCTIONS BIT FIELD)

FILTER

COMPUTE

ENGINE

FIFO/

TIMER

PATH 2

AGC

LOOP

FILTER

MUX

AGC

MULT

EXT AGC

GAIN

PATH 1

PATH 3

CART

POLAR

SHIFT

d/dt

x1, x2 x4, x8

M U X

dphi/dt: Q

I1 Q1

GAIN

MAG

PHASE

I2 Q2

28 27 25 24 23 22 21 20 19 18

28 27 26, 25

24 23 22:18

AGC LOOP GAIN SELECT (PATH 01 ONLY) UPDATE AGC LOOP (PATH 01 ONLY) PATH 00 - - IMMEDIATE FILTER PROCESSOR FEEDBACK PATH

01 - - FIFO/AGC PATH TO I1 AND Q1 10 - - DIRECT OUT/CASCADE PATH TO I2 AND Q2

11 - - FIFO/AGC PATH TO I2 AND Q2 STROBE OUTPUT SECTION (START SERIAL OUTPUT WITH THIS SAMPLE) FEED MAG/PHASE BACK TO FILTER PROCESSOR

FILTER PROCESSOR SEQUENCE STEP NUMBER

Back End Section

One back-end processing section is provided per channel. Each back end section consists of a filter compute engine, a FIFO/timer for evenly spacing samp l es (important when implementing interpolation filters and resamplers), an AGC and a cartesian-to-polar coordinate conversion block. A block diagram showing the major functional blocks and data routing is shown above. The data input to the back end section is through the filter compute engine. There are two other inputs to the filter compute engine, they are a data recirculation path for cascading filters and a magnitude and dφ/dt feedback path for AM and FM filtering. There are seven outputs from each back end processing section. These are I and Q directly out of the filter compute engine (I2, Q2), I and

Q passed through the FIFO and AGC multipliers (I1, Q1), magnitude (MAG), phase (or dφ/dt), and the AGC gain control value (GAIN). The I2/Q2 outputs are used when cascading back end stages. The routing of signals within the back end processing section is controlled by the filter compute engine. The routing information is embedded in the instruction bit fields used to define the digital filter being implemented in the filter compute engine.

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Filter Compute Engine

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R/dφ/dt

0..-23

INMUX (1:0)

ADDRA (8:0) ADDRB (8:0)

M U X

RAMR/Wb

WORDS

RAM

384

ISL5216

DOWN SHIFT

1..-25

WITH RND

0..-23

A P

1..-23

A L U

0, 1, 2 PLACES

∑

0..-21

S H

9..-31

F T

R E G

S H F T

R E G

E G

0..-23

I I

E G

IFUNCT

QFUNCT

COEF (21:0), SHIFT (1:0)

RAMAEN

RAMBEN

IQSWAP

The filter compute engine is a dual multiply-accumulator (MAC) data path with a microcoded FIR sequencer. The filter compute engine can implement a single FIR or a set of filters. For example, the filter chain could include two halfband filters, a shaping (matched) filter and a resampling filter, all with different decimations. The following filter types are currently supported by the architecture and microcode:

• Even symmetric with even # of taps decimation filters

• Even symmetric with odd # of taps decimation filters (including HBFs)

• Odd symmetric with even # of taps decimation filters

• Odd symmetric with odd # of taps decimation filters

• Asymmetric decimation filters

• Complex filters

• Interpolation filters (up to interpolate by 4)

• Interpolation halfband filters

• Resampling filters (under resampler NCO control)

• Fixed resampling ratio filter (within the available number of coefficients)

• Quadrature to real filtering (w/ fs/4 up conversion)

The input to the filter compute engine comes from one of three sources—a CIC filter output (which can also be another backend section), the output of the filter compute engine (fed back to the input) or the magnitude and dφ/dt fed back from the cartesian-to-polar coordinate converter.

COEF

ENFB, RNDSEL (2:0)

REGEN4

SHIFT (1:0)

ENLIMIT

NOTE: PIPELINE DELAYS

OMITTED FOR CLARITY

ENHR1

ENHR2

OUTSEL

The number and size of the filters in the chain is limited by the number of clock cycles available (determined by the decimation) and by the data and coefficient RAM/ROM resources. The data RAM is 384 words (I/Q pairs) deep. The data addressing is modulo in power-of-2 blocks, so the maximum filter size is 256. The block size and the block starting memory address for each filter is programmable so that the available memory can be used efficiently . The coef ficient RAM is 192 words deep. It is half the size of the data memory because filter coefficients are typically symmetric. ROMs are provided with halfband filter coefficients, resampling filter coefficients, and constants. The filter compute engine exploits symmetry where possible so that each MAC can compute two filter taps per clock by doing a pre-add before multiplying. In the case of halfband filters, the zero-valued coefficients are skipped for extra efficiency . There is an overhead of one clock cycle per input sample for each filter in the chain (for writing the data into the data RAM) and (except in special cases) a two clock cycle overhead for the entire chain for program flow control instructions.

The output of the filter compute engine is routed through a FIFO in the main output path. The FIFO is provided to more evenly space the FIR outputs when they are produced in bursts (as when computing resampling or interpolation filters). The FIFO is four samples deep. The FIFO is loaded by the output of the filter when that path is selected. It is unloaded by a counter. The spacing of the output samples is specified in clock periods. The spacing can be set from 1 (fall through) to 4096 samples

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ISL5216

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(approximately the spacing for a 16KSPS output sample rate when using 65MSPS clock) using IWA = *00Ah bits 11:0.

The number and order of the filtering in the filter chain is defined by a FIR control program. The FIR control program is a sequence of up to 32 instruction words. Each instruction word can be a filter or program flow instruction. The filter instruction defines a FIR in the chain, specifying the type of FIR, number of taps, decimation, memory allocation, etc. For program flow, a wait for input sample(s) instruction, a loop counter load, and several jumps (conditional and unconditional) are provided. The ISL5216 evaluation board includes software for automatically generating FIR control programs for most filter requirements. Examples of programs FIR control programs are given below.

The simplest filter program computes a single filter. It has three instructions (see Sample Filter #1 Program Instructions below):

SAMPLE FILTER #1 PROGRAM

STEP INSTRUCTION

0 Wait for enough input samples

(equal to the decimation factor)

1FIR

Type = even symmetric 95 taps Decimate by 2 Compute one output Decrement wait counter Memory block size 128 Memory block start at 64, Coefficient block start at 64 Step size 1 Output to AGC

2 Jump, Unconditional, to step 0

The parameters of the FIR (including type, number of taps, decimation and memory usage) are specified in the bit fields of the step 1 instruction word. T o change the filtering the only other change needed is the number of samples in the wait threshold register (IWA = *00C, bits 9:0). The filter in this example requires 52 clock cycles to compute, allocated as follows:

SAMPLE FILTER #1 CLOCK CYCLES CALCULATION

CLOCK

CYCLES FUNCTION PERFORMED

48 Clocks for FIR computation (two taps/clock due to

symmetry)

2 Clocks for writing the input data into the data RAMs

(Decimate by 2 requires 2 inputs per output)

2 Clocks for the program flow instructions (wait and

jump)

52 Total

Using a 65MSPS clock, the output sample rate could be as high as 65MSPS/52 clocks = 1.25MSPS. The input sample rate to the FIR from the CIC filter would be 2. 5MSPS. The impulse response length would be 38μs (95 taps at

0.4μs/tap). Each additional filter added to the signal processing chain

requires one instruction step. As an example of this, a typical filter chain might consist of two decimate-by-2 halfband filters being followed by a shaping filter with the final filter being a resampling filter. The program for this case might be (see Sample Filter Program #2 Instructions below):

SAMPLE FILTER #2 PROGRAM

STEP INSTRUCTION

0 Wait for enough input samples (usually equal to the

total decimation—8 in this case)

1FIR

Type = even symmetry 15 taps Halfband Decimate by 2 Compute four outputs Memory block size 32 Memory block start at 0 Coefficient block start at 13 Output to step 2 Decrement wait count

2FIR

Type = even symmetry 23 taps Halfband Decimate by 2 Compute two outputs Memory block size 32 Memory block start at 32 Coefficient block start at 24 Output to step 3

3FIR

Type = even symmetry 95 taps Decimate by 2 Compute one output Memory block size 128 Memory block start at 64 Coefficient block start at 64 Step size 1 Output to step 4

4FIR

Type = resampler Increment NCO 6 taps Compute one output Memory block size 8 Memory block starts at 192 Coefficient block start at 512 Step size 32 Output to AGC

5 Jump, Unconditional, to 0

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Sample filter #2 requires:

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• 32 + 32 + 128 + 8 = 200 data RAM locations

• (95+1)/2 = 48 coefficient RAM location (resampler and HBF coefficients are in ROM).

The number of clock cycles required to compute an output for Sample filter #2 is calculated as follows:

SAMPLE FILTER #2 CLOCK CYCLES CALCULATION

CLOCK

CYCLES FUNCTION PERFORMED

20 Halfband 1 compute clocks

(5 per compute x 4 computes)

8 Halfband 1 input sample writes (8 input samples)

14 Halfband 2 compute clocks

(7 per compute x 2 computes)

4 Halfband 2 input sample writes (4 input samples)

48 95 tap symmetric FIR, 2 clocks per tap

2 FIR input sample writes (2 input samples)

6 Resampler (6 taps, nonsymmetric)

1 Resampler input sample write (1 input samples)

1 Jump instruction

1 Wait instruction

105 Clock cycles per output

Total decimation is 8, so the input sample rate for the FIR chain (CIC output rate) could be up to:

/(ceil(105/8)) = f

CLK

/14.

With a 65MHz clock, this would support a maximum input sample rate to the FIR processor of 4.6MHz and an output sample rate up to 0.580MHz. The shaping filter impulse response length would be:

(95 x 2)/580,000 = 82μs. The maximum output sample rate is dependent on the

length and number of FIRs and their decimation factors. Illustrating this concept with Filter Example #3, a higher

speed filter chain might be comprised of one 19 tap decimate-by-2 halfband filter followed by a 30 tap shaping FIR filter with no decimation. The program for this example could be:

ISL5216

SAMPLE FILTER #3 PROGRAM

STEP INSTRUCTION

0 Wait for enough input samples (2 in this case) 1FIR

Type = even symmetry 19 taps Halfband Decimate by 2 Compute one output Memory block size 32 Memory block start at 0 Coefficient block start at 18 Output to step 2 Reset wait count

2FIR

Type = even symmetry 30 taps Decimate by 1 Compute one output Memory block size 64 Memory block start at 32 Coefficient block start at 64 Step size 1 Output to AGC

3 Jump, Unconditional, to 0

The number of clock cycles required to compute an output for Sample filter #3 is calculated as follows:

SAMPLE FILTER #3 CLOCK CYCLES CALCULATION

CLOCK

CYCLES FUNCTION PERFORMED

6 19 tap halfband, one output 2 halfband input writes (2 input samples)

15 30 tap symmetric FIR, 2 taps per clock

1 1 FIR input write 11 wait 11 jump

26 Clock cycles per output

For Filter Example #3 and a 65MSPS input, the maximum FIR input rate would be 65MSPS/ceil(26/2) = 5MSPS giving a decimate-by-2 output sample rate of 2.5MSPS. At 80MSPS, the FIR could have up to 42 taps with the same output rate.

Channels 0, 1, 2 and 3 can be combined in a polyphase structure for increased bandwidth or improved filtering.

Filter Example #4 will be used to demonstrate this capability. Symbol rate of 4.096 MSym. The desired output sample rate

is 8.192MSPS. Arrange the four back end sections as four filters operating on the same CIC output at a rate of

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65.536MHz/4 = 16.384MHz, where the factor of 4 is the CIC

decimation we have chosen. Each channel computes the same sequence, offset by one

output sample from the previous sample (see IWA = *00Bh). Each channel decimates down to 2.048M and then the channels are multiplexed together in the output formatter to get the desired 8.192MSPS. The input sample rate to the final filter of each channel must meet Nyquist requirements for the final output to assure that no information is lost due to aliasing.

SAMPLE FILTER #4 PROGRAM

STEP INSTRUCTION

0 Wait for enough input samples (8 in this case) 1FIR

type = even symmetry 44 taps decimate by 8 compute one output memory block size 64 memory block start at 0 coefficient block start at 64 step size 1 output to AGC offset memory read pointers by 0, -2, -4, -6

2 Jump, Unconditional, to 0

The number of FIR taps available for these requirements is calculated as follows:

65536/2048 = 32 clocks minus (8 writes + 1 wait + 1 jump = 10 clocks) = 22 clocks Therefore, the number of taps available is: 22 x 2 = 44 taps. Multiplexing the four outputs gives a final output sample rate

of 8.192MSPS. The impulse response is 44 taps at 16.384M or 22 output

samples (11 symbols at 4.096M). The AGC loop filter output of channel 4 can be routed to

control the forward AGC gain control of all four channels. This assures that the gains of the four back end sections are the same. The gain error, however, is only computed from every fourth output sample.

The filter sequencer is programmed via an instruction RAM and several control registers. These are described below.

Instruction RAMs

The filter compute engine is controlled by a simple sequencer supporting up to 32 steps. Each step can be a filter or one of four sequence flow instructions—wait, jump (conditional or unconditional), load loop counter, or NOP. There are 128 bits per instruction word with each word consisting of condition code selects, FIR parameters and data routing controls. Not all of the instruction word bits are used for all instruction types. The actual sequencer instruction is only 9 bits. The rest of the bits are used for filter parameters or for the loop counter preload. Each sequence step is loaded by the microprocessor in four 32-bit writes. The mapping of the bit fields for the instruction types is shown in the instruction bit field table that follows. These FIR instruction words can be generated using software tools provided with the ISL5216 evaluation board.

When the filter is reset, the instruction pointer is set to 31 (the last instruction step). The read and write pointers are initialized on reset, so a reset must be done when the channel is initialized or restarted.

A fixed offset can be added to the starting read address of one of the filters in the program. This function is provided to offset the data reads of the filters in a polyphase filter bank; all filters in the bank will write the same data to the same RAM location. To offset the computations the RAM read address is offset. See IWA = *00Bh for details.

The instruction word bits (127:0) are assigned to memory words as follows:

31:0 to destination C C C C 0 0 0 1 0 x x x x x 0 0 63:32 to destination C C C C 0 0 0 1 0 x x x x x 0 1

95:64 to destination C C C C 0 0 0 1 0 x x x x x 1 0 127:96 to destination C C C C 0 0 0 1 0 x x x x x 1 1 where CCCC is the channel number and xxxxx is the

instruction sequence step number (0–31 decimal). Note the μPHold bit in the filter compute engine control register (IWA = *00Ah) must be set for the microproce s sor to read from or write to the instruction or coefficient RAMs.

The back end processing sections of two or more ISL5216s can be combined using the same polyphase approach, but the AGC gain from one part cannot be shared with another part (except via the μP interface), so polyphase filter using multiple parts would typically usually use a fixed gain.

FN6013.3

July 13, 2007

Filter Sequencer

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ISL5216

NEW DATA, FIR #

RESET

SYNC

THRESHOLD

DECREMENT 1 DECREMENT 2

LOOP

COUNTER

INSTRUCTION RAM,

SEQUENCER

WAIT

COUNTER

LOOP COUNTER PRELOAD

FIR# - WRITE DESTINATION

FIR# - COMPUTE

DATA ADDRESS STEP SIZE COMPUTE TO COMPUTE

FIR TYPE

NUMBER OF OUTPUTS

TAPS/OUTPUT READS/TAP INSTR/TAP

RAM ADDR BLOCK START RAM ADDR BLOCK SIZE RAM ADDR STEP SIZE 1

FIR

PARAMETER

RAM

RAM ADDR STEP SIZE 2 RAM ADDR BLOCK TO BLOCK STEP

RAM ADDR INITIAL OFFSET RAM ADDR OFFSET STEP

RAM ADDR BLOCK TO BLOCK STEP

ALIAS MASK

READ

POINTER

REG FILE

START ADDRESS

COMPUTE

COUNTERS

WRITE

POINTER

REG FILE

FIR OUTPUT DESTINATION

DATA PATH

CONTROL

ROM

RAM

ADDR

GEN

RAM

ADDR

GEN

CONTROL SIGNALS

DATA RAM A

READ/WRITE

DATA RAM B

READ ADDRESS

ENABLE OFFSET

DATA PATH

ADDRESS

RESAMPLER

NCO

COEF ADDR BLOCK START COEF ADDR BLOCK SIZE COEF ADDR STEP SIZE PER TAP ADDR STEP SIZE PER OUTPUT

ADDRESS OFFSET

COEF

ADDR

GEN

COEFFICIENT

READ ADDRESS

FN6013.3

July 13, 2007

ISL5216

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Instruction Bit Fields

INSTRUCTION BIT FIELDS

BIT

POSITIONS FUNCTION DESCRIPTION

8:0 Instruction Instruction Field Bit Mapping

Bit876543210 Type WAIT00XXXXCCC FIR 0 1 Start IncrRS DecrSel DecrEn LdLp DecrLp EnU/C JUMP1JJJJJCCC (NOPs and loading the loop counter are special cases of the FIR instruction).

XXXX = ignored. JJJJJ = jump destination (sequence step number).

CCC = condition code. 000 = ! (waitcount ≥ threshold) -- See IWA = *00Ch, bits 9:0 for threshold details. 001 = waitcount ≥ threshold -- See IWA = *00Ch, bits 9:0 for threshold details. 010 = loop counter ≠ 0. 011 = loop counter = 0. 100 = ! (RSCO) (RSCO - resampler NCO carry output). 101 = RSCO. 110 = sync (if enabled) or μP controlled bit.

111 = always. Start = load parameters and start filter computation, set to zero for no-ops, loop counter loads. IncrRS = increment resampler during this filter.

DecrSel = selects between two decrement values for the wait counter. DecrEn = decrement wait count on starting this instruction. LdLp = load loop counter with the data in the I(20:9) bit field.

DecrLp = decrement loop counter on starting this instruction. EnU/C = enable U/C counter with this FIR.

14:9 FIR Type FIR Parameter Bit Fields

14:9 FIR type. 000000 NOP. 000001 Decimating FIR, Even Symmetric, Even # Taps. 000010 Decimating FIR, Even Symmetric, Odd # Taps. 000011 Decimating FIR, Odd Symmetric, Even # Taps. 000100 Decimating FIR, Odd Symmetric, Odd # Taps. 000101 Decimating FIR, Asymmetric. 001000 Resampling FIR, Asymmetric. 001001 Interpolating HBF. 100000 Decimating FIR, Complex (Asymmetric). NOTES:

14. Regular interpolation FIRs are successive runs of a FIR with no data address increment, but with coefficient start address increments.

15. Decimating HBFs are even symmetric, odd number of taps but with different data step sizes.

16. U/C FIR is a normal FIR with the U/C bit enabled.

17. Other codes may be added in the future.

17:15 Steps per FIR Specifies the number of steps per FIR instruction sequence (load with value minus 1)

(set to 0 for all FIR types except complex which is set to 1).

Increments on start or at each FIR output depending on μPcontrol bit.

The start bit should not be set when this bit is set.

This multiplies the data by 1, j, -1, -j. The multiplication factor changes each time the filter runs.

FN6013.3

July 13, 2007

ISL5216

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INSTRUCTION BIT FIELDS (Continued)

BIT

POSITIONS FUNCTION DESCRIPTION

28:18 Destination Destination Field Bit Mapping

31:29 Round Select 31:29 Round Select (Add rounding bit at specified location).

41:32 Data Memory

Block Start

44:42 Data Memory

Block Size

52:45 Data Memory

Block-to-Block Step

62:53 Coefficient Memory

Block Start

28 27 26 25 24 23 22 21 20 19 18 AGCLFGN AGCLF Path1 Path0 OS FB F4 F3 F2 F1 F0 AGCLFGN AGC loop gain select. Only applies to Path 1.

AGCLF AGC loop filter enable. Only applies to Path 1. The AGC loop is updated with the magnitude

Path(1:0) Back End Data Routing Path Selection. (see Back End Data Routing figure)

OS Enable output strobe. Setting this bit generates a data ready signal when the data reaches

FB Feedback data path. When set, the magnitude and dphi/dt from the cartesian-to-polar coor-

F(4:0) Filter select. For data recirculated to the input of the FIR processor by path 0 or from the

000 2 001 2 010 2 011 2 100 2 101 2 110 2

111 no rounding. Provided for use with the coefficient down-shift bits. Memory block base address, 0-1023, 0-383 are valid for the ISL5216.

44:42 Block Size. 0 8 1 16 2 32 364 4 128 5 256 6 512 7 1024 (modulo addressing is used). 0-255, usually equal to the decimation factor for the FIR in this instruction.

Memory base address of coefficients, 0-1023, 0-511 are valid on the ISL5216.

Loop gain 0 or 1 if AGCLF bit is set. Set to 0 (1 is a test mode for future chips).

of this sample (Path(1:0) = 01).

00 Route output back to filter compute engine input to another FIR in the filter chain. 01 Route output thru the FIFO and AGC to outputs I1 and Q1. 10 Route output to I2 and Q2, bypassing the FIFO and AGC. This path

also routes to next channel FIR input.

11 Route output thru the FIFO and AGC to outputs I2 and Q2.

the output section and starts the serial output sequence (paths 1, 2, 3). If OS is not set, there will be no output to the outside world from this channel, for that output calculation, but the data will be loaded into its output holding register (OS would not be set when routing the data to another back end when cascading channels).

dinate converter block are routed to the filter compute engine input (magnitude goes to the I input and dphi/dt goes to the Q input). Provided for discriminator filtering.

cartesian to polar coordinate converter output, these bits tell which filter sequencer step gets it as an input.

-24

, use this code when downshifting is not used.

-23

-22

-21

-20

-19

-18

FN6013.3

July 13, 2007

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