intersil ISL43L710, ISL43L711, ISL43L712 DATA SHEET

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ISL43L710, ISL43L711, ISL43L712

Data Sheet November 4, 2004

Ultra Low ON-Resistance, Single Supply,
Differential SPST Analog Switches

The Intersil ISL43L710, ISL43L711, ISL43L712 devices are
low ON-resistance, low voltage, bidirectional, precision,
differential single-pole/single-throw (SPST) analog switches
designed to operate from a single +1.65V to +3.6V supply.
Targeted applications include battery powered equipment
that benefit from low R
(0.12µW) and fast switching speeds (t
t

= 13ns).

OFF

Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This family of parts may be used to
switch in additional functionality while reducing ASIC design
risk. The ISL43L71X are offered in small form factor
packages, alleviating board space limitations.

The ISL43L710, ISL43L711, ISL43L712 are differential
single-pole/single-throw (SPST) devices. The ISL43L710
has two normally open (NO) switches; the ISL43L711 has
two normally closed (NC) switches; the ISL43L712 has one
normally open (NO) and one normally closed (NC) switch
and can be used as an SPDT. The ISL43L712 is equipped
with an inhibit pin to simultaneously open all signal paths.

(0.16Ω), low power consumption

ON

ON =

13ns,

FN6092.1

Features

• Pb-Free Available (RoHS Compliant) (See Ordering info)

• Low ON Resistance (R

ON

)

- V+ = 3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.16Ω

- V+ = 1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.26Ω

Matching Between Channels. . . . . . . . . . . . . . . 0.005Ω

•R

ON

Flatness Over Signal Range . . . . . . . . . . . . . . . 0.008Ω

•R

ON

• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +3.6V

• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . <0.12µW

• Fast Switching Action (V+ = 3.0V)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns

-t

ON

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns

-t

OFF

• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >8kV

• 1.8V Logic Compatible (+3V Supply)

• Available in 8-Ld thin DFN and 8-Ld MSOP Packages

Applications

• Battery Powered, Handheld, and Portable Equipment

- Cellular/Mobile Phones

- Pagers

- Laptops, Notebooks, Palmtops

Table 1 summarizes the performance of this family.

TABLE 1. FEATURES AT A GLANCE

ISL43L710 ISL43L711 ISL43L712

NUMBER OF

SWITCHES

SW 1/SW 2 NO/NO NC/NC NO/NC

1.8V R

ON

1.8V tON/t

3V t

PACKAGES 8 Ld 3x3 thin DFN, 8 Ld MSOP

3V R

ON/tOFF

OFF

ON

222

0.26Ω 0.26Ω 0.26Ω

30ns/25ns 30ns/25ns 30ns/25ns

0.16Ω 0.16Ω 0.16Ω

13ns/13ns 13ns/13ns 13ns/13ns

Related Literature

Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”.

Application Note AN557 “Recommended Test Procedures
for Analog Switches”.

• Portable Test and Measurement

• Medical Equipment

• Audio and Video Switching

Truth Table

ISL43L710 ISL43L711

LOGIC

0OFFON

1ONOFF

INH LOGIC

1X OFF OFF

00 OFF ON

0 1 ON OFF

NOTE: Logic “0” ≤ 0.5V. Logic “1” ≥ 1.4V with a 3V Supply.

SW 1, 2 SW 1, 2

ISL43L712

SW 1 SW 2

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2004. All Rights Reserved

Pinouts (Note 1)

ISL43L710 (MSOP, TDFN)

TOP VIEW

ISL43L710, ISL43L711, ISL43L712

ISL43L711 (MSOP, TDFN)

TOP VIEW

V+

1

NO

2

1

3

IN

4

NO

2

NOTE:

1. Switches Shown for Logic “0” Input.

Ordering Information

(Note 2)

PART NO.

(BRAND)

ISL43L710IU
(L710)

ISL43L710IR
(L70)

ISL43L711IU
(L711)

ISL43L711IR
(L71)

ISL43L712IU
(L712)

ISL43L712IR
(L72)

ISL43L710IUZ
(L710) (Note 3)

ISL43L710IRZ
(L70)
(Note 3)

ISL43L711IUZ
(L711)
(Note 3)

ISL43L711IRZ
(L71)
(Note 3)

TEMP.

RANGE (°C) PACKAGE

-40 to 85 8 Ld MSOP M8.118

-40 to 85 8 Ld 3x3 thin DFN L8.3x3A

-40 to 85 8 Ld MSOP M8.118

-40 to 85 8 Ld 3x3 thin DFN L8.3x3A

-40 to 85 8 Ld MSOP M8.118

-40 to 85 8 Ld 3x3 thin DFN L8.3x3A

-40 to 85 8 Ld MSOP
(Pb-free)

-40 to 85 8 Ld 3x3 thin DFN
(Pb-free)

-40 to 85 8 Ld MSOP
(Pb-free)

-40 to 85 8 Ld 3x3 thin DFN
(Pb-free)

COM

8

1

7

N.C.

6

COM

2

5

GND

NC

NC

V+

IN

1

2

1

3

4

2

8

COM

1

7

N.C.

6

COM

2

5

GND

ISL43L712 (MSOP, TDFN)

TOP VIEW

NO

NC

V+

IN

1

2

1

3

4

2

8

COM

1

7

INH

6

COM

2

5

GND

Ordering Information (Continued)

(Note 2)

PKG.

DWG. #

PART NO.

(BRAND)

ISL43L712IUZ *
(L712)

TEMP.

RANGE (°C) PACKAGE

-40 to 85 8 Ld MSOP
(Pb-free)

PKG.

DWG. #

M8.118

(Note 3)

ISL43L712IRZ *
(L72)

-40 to 85 8 Ld 3x3 thin DFN
(Pb-free)

L8.3x3A

(Note 3)

NOTES:

2. Most surface mount devices are available on tape and reel; add
“-T” to suffix.

3. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak

M8.118

reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020C.

L8.3x3A

Pin Descriptions

M8.118

L8.3x3A

PIN FUNCTION

V+ System Power Supply Input (+1.65V to +3.6V)

GND Ground Connection

IN Digital Control Input

COM Analog Switch Common Pin

NO Analog Switch Normally Open Pin

NC Analog Switch Normally Closed Pin

INH Digital Control Input. Connect to GND for Normal

Operation. Connect to V+ to turn all switches off.

N.C. No Connect

2

FN6092.1

November 4, 2004

ISL43L710, ISL43L711, ISL43L712

Absolute Maximum Ratings Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V

Input Voltages

IN (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)

NO, NC (Note 4) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)

Output Voltages

COM (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)

Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . 300mA

Peak Current, IN, NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . 500mA

ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . . >8kV

Operating Conditions

Temperature Range

ISL43L71XIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

4. Signals on NC , NO , COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

5. θ

JA

Thermal Resistance (Typical, Note 5) θ

(°C/W)

JA

8 Ld 3x3 thin DFN Package . . . . . . . . . . . . . . . . . . . 110

8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 190

Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(Lead Tips Only)

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

Unless Otherwise Specified

TEMP

PARAMETER TEST CONDITIONS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ON Resistance, R

R

Matching Between Channels,

ON

∆R

ON

Flatness, R

R

ON

NO or NC OFF Leakage Current,
I

NO(OFF)

or I

NC(OFF)

COM ON Leakage Current,
I

COM(ON)

ON

Flat(ON)

ANALOG

V+ = 2.7V, I
(See Figure 4)

V+ = 2.7V, I
Max R

V+ = 2.7V, I
(Note 11)

V+ = 3.3V, V

V+ = 3.3V, V

DYNAMIC CHARACTERISTICS

Turn-O N Time, t

Turn-O FF Time, t

ON

OFF

Charge Injection, Q C

OFF Isolation R

Crosstalk (Channel-to-Channel) R

NO or NC OFF Capacitance, C

V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
V

IN

V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
V

IN

L

L

(See Figure 3)

L

(See Figure 5)

f = 1MHz, VNO or VNC = V

OFF

= 100mA, VNO or VNC = 0V to V+

COM

COM

, (Note 10)

ON

COM

= 100mA, VNO or V

= 100mA, VNO or V

= 0.3, 3V, VNO or VNC = 3V, 0.3V 25 -3 - 3 nA

COM

= 0.3V, 3V, or VNO or VNC = 0.3V, 3V 25 -3 - 3 nA

COM

= Voltage at

NC

= 0V to V+,

NC

= 0 to 2.7V, (See Figure 1, Note 9)

= 0 to 2.7V, (See Figure 1, Note 9)

= 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -125 - pC

= 50Ω, CL = 5pF, f = 100kHz, V

= 50Ω, CL = 5pF, f = 100kHz, V

= 0V, (See Figure 6) 25 - 182 - pF

COM

COM

COM

= 1 V

= 1 V

RMS,

RMS

(°C)

Full 0 - V+ V

25 - 0.17 0.25 Ω

Full - - 0.3 Ω

25 - 0.005 0.02 Ω

Full - - 0.04 Ω

25 - 0.008 0.06 Ω

Full - - 0.07 Ω

Full -60 - 60 nA

Full -80 - 80 nA

25 - 15 25 ns

Full - - 30 ns

25 - 15 25 ns

Full - - 30 ns

25 - 62 - dB

,

25 - -94 - dB

= 1.4V, V

INH

INL

MIN

(NOTE 7) TYP

= 0.5V (Notes 6, 8),

MAX

(NOTE 7) UNITS

3

FN6092.1

November 4, 2004

ISL43L710, ISL43L711, ISL43L712

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

= 1.4V, V

INH

= 0.5V (Notes 6, 8),

INL

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS

COM OFF Capacitance,
C

COM(OFF)

COM ON Capacitance, C

COM(ON)

f = 1MHz, VNO or VNC = V

f = 1MHz, VNO or VNC = V

TEMP

(°C)

= 0V, (See Figure 6) 25 - 182 - pF

COM

= 0V, (See Figure 6) 25 - 290 - pF

COM

MIN

(NOTE 7) TYP

MAX

(NOTE 7) UNITS

POWER SUPPLY CHARACTERISTICS

Power Supply Range Full 1.65 - 3.6 V

Positive Supply Current, I+ V+ = 1.65V to 3.6V, V

off

= 0V or V+, all channels on or

IN

25 - - 30 nA

Full - - 750 nA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Input Voltage High, V

Input Current, I

INH

, I

INL

INH

INL

V+ = 3.3V, VIN = 0V or V+ (Note 9) Full -0.5 - 0.5 µA

Full - - 0.5 V

Full 1.4 - - V

NOTES:

= input voltage to perform proper function.

6. V

IN

7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

8. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.

9. Guaranteed but not tested.

10. R

matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max

ON

Ron value.

11. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.65V to +2.0V, GND = 0V, V

Unless Otherwise Specified

TEMP

PARAMETER TEST CONDITIONS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ON Resistance, R

R

Matching Between Channels,

ON

∆R

ON

Flatness, R

R

ON

NO or NC OFF Leakage Current,
I

NO(OFF)

or I

NC(OFF)

COM ON Leakage Current,
I

COM(ON)

ON

FLAT(ON)

ANALOG

V+ = 1.8V, I
(See Figure 4, Note 9)

V+ = 1.8V, I
Max R

V+ = 1.8V, I
(Note 11)

V+ = 2.0V, V

V+ = 2.0V, V

1.8V

DYNAMIC CHARACTERISTICS

Turn-O N Time, t

Turn-O FF Time, t

ON

OFF

Charge Injection, Q C

V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF,
V

IN

V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF,
V

IN

L

= 100mA, VNO or VNC = 0V to V+,

COM

= 100mA, VNO or VNC = Voltage at

COM

, (Note 10)

ON

= 100mA, VNO or VNC = 0V to V+,

COM

= 0.3V, 1.8V, VNO or VNC = 1.8V, 0.3V 25 -3 - 3 nA

COM

= 0.3V, 1.8V, or VNO or VNC = 0.3V,

COM

= 0 to 1.65V, (See Figure 1, Note 9)

= 0 to 1.65V, (See Figure 1, Note 9)

= 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -80 - pC

(°C)

(NOTE 7) TYP

Full 0 - V+ V

25 - 0.26 0.35 Ω

Full - - 0.4 Ω

25 - 0.005 - Ω

Full - 0.005 - Ω

25 - 0.074 - Ω

Full - 0.082 - Ω

Full -60 - 60 nA

25 -3 - 3 nA

Full -80 - 80 nA

25 - 30 40 ns

Full - - 45 ns

25 - 25 35 ns

Full - - 40 ns

INH

MIN

= 1.0V, V

= 0.4V (Notes 6, 8),

INL

MAX

(NOTE 7)UNITS

4

FN6092.1

November 4, 2004

ISL43L710, ISL43L711, ISL43L712

Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.65V to +2.0V, GND = 0V, V

= 1.0V, V

INH

= 0.4V (Notes 6, 8),

INL

Unless Otherwise Specified (Continued)

TEMP

PARAMETER TEST CONDITIONS

OFF Isolation RL = 50Ω, CL = 5pF, f = 100kHz, V

Crosstalk (Channel-to-Channel) 25 - -94 - dB

NO or NC OFF Capacitance, C

COM OFF Capacitance,
C

COM(OFF)

COM ON Capacitance, C

COM(ON)

Figure 3 and Figure 5)

f = 1MHz, VNO or VNC = V

OFF

f = 1MHz, VNO or VNC = V

f = 1MHz, VNO or VNC = V

COM

COM

COM

COM

= 1 V

RMS,

(See

= 0V, (See Figure 6) 25 - 182 - pF

= 0V, (See Figure 6) 25 - 182 - pF

= 0V, (See Figure 6) 25 - 290 - pF

(°C)

25 - 62 - dB

MIN

(NOTE 7) TYP

MAX

(NOTE 7)UNITS

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 1.65V to 3.6V, V

off

= 0V or V+, all channels on or

IN

25 - - 30 nA

Full - - 750 nA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Input Voltage High, V

Input Current, I

INH

, I

INL

INH

INL

V+ = 2.0V, VIN = 0V or V+ (Note 9) Full -0.5 - 0.5 µA

Full - - 0.4 V

Full 1.0 - - V

Test Circuits and Waveforms

tr < 5ns

< 5ns

t

f

90%

LOGIC
INPUT

SWITCH

INPUT

SWITCH

OUTPUT

V+

50%

0V

t

OFF

V

NO

0V

t

ON

90%

V

OUT

Logic input waveform is inverted for switches that have the opposite
logic sense.

SWITCH

LOGIC

INPUT

INPUT

NO or NC

IN

Repeat test for all switches. C
capacitance.

V

OUT

V+

C

GND

includes fixture and stray

L

V

=

(NO or NC)

COM

R

L

------------------------------

RLR

+

ON()

RL
50Ω

V

OUT

C

35pF

L

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

V+

C

R

SWITCH

OUTPUT

V

OUT

LOGIC

INPUT

ON

Q = ∆V

OUT

∆V

x C

OUT

L

OFF

ON

V+

0V

V

G

G

NO or NC

GND

FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

5

COM

IN

LOGIC
INPUT

V

OUT

C

L

FN6092.1

November 4, 2004

ISL43L710, ISL43L711, ISL43L712

Test Circuits and Waveforms (Continued)

SIGNAL
GENERATOR

ANALYZER

FIGURE 3. OFF ISOLATION TEST CIRCUIT FIGURE 4. RON TEST CIRCUIT

SIGNAL
GENERATOR

R

L

0V or V+

NO or NC

COM

NO1 or NC1

IN

1

GND

V+

IN

V+

COM1

IN

C

X

C

0V or V+

2

0V or V+

50Ω

RON = V1/100mA

V

NX

IMPEDANCE

ANALYZER

1mA

V

1

NO or NC

COM

NO or NC

GND

V+

C

0V or V+

IN

V+

C

IN

0V or V+

X

ANALYZER

COM2

R

L

NO2 or NC2

GND

NC

FIGURE 5. CROSSTALK TEST CIRCUIT FIGURE 6. CAPACITANCE TEST CIRCUIT

Detailed Description

The ISL43L71x family of devices are bidirectional, single
pole/single throw (SPST) analog switches that offer precise
switching capability from a single 1.65V to 3.6V supply with
low on-resistance (0.16Ω) and high speed operation
(t

= 13ns, t

ON

suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(2.7µW max), low leakage currents (80nA max), and the tiny
TDFN and MSOP packaging. The ultra low on-resistance and
R

flatness provide very low insertion loss and distortion to

ON

application that require signal reproduction.

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (See
Figure 7). To prevent forward biasing these diodes, V+ must

= 13ns). The device is especially well

OFF

COM

GND

be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.

Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (See Figure 7). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.

This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low R

switch, so two small signal

ON

diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (See Figure 7). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is

6

FN6092.1

November 4, 2004

ISL43L710, ISL43L711, ISL43L712

unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.

OPTIONAL PROTECTION
DIODE

OPTIONAL
PROTECTION
RESISTOR

IN

X

V

NO or NC

FIGURE 7. OVERVOLTAGE PROTECTION

V+

GND

OPTIONAL PROTECTION
DIODE

V

COM

Power-Supply Considerations

The ISL43L71x construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL43L71x 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.

The minimum recommended supply voltage is 1.65V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and on­resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.

V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.

This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2V to 3.6V (See Figure 14). At 3.6V
the V

level is about 1.27V. This is still below the 1.8V

IH

CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.

The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.

High-Frequency Performance

In 50Ω systems, signal response is reasonably flat even past
20MHz with a -3dB bandwidth of 175MHz (See Figure 15).
The frequency response is very consistent over a wide V+
range, and for varying analog signal levels.

An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 16 details the high Off Isolation and Crosstalk
rejection provided by this family. At 100kHz, Off Isolation is
about 62dB in 50Ω systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.

Leakage Considerations

Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.

Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog­signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.

7

FN6092.1

November 4, 2004

ISL43L710, ISL43L711, ISL43L712

Typical Performance Curves T

0.26

0.24

V+ = 1.8V

0.22

0.2

(Ω)

ON

R

0.18

0.16

0.14

0.12
01234

V+ = 2.7V

V+ = 3V

V

COM

(V)

= 25°C, Unless Otherwise Specified

A

I

= 100mA

COM

V+ = 3.6V

FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

0.3

0.25

85°C

V+ = 1.8V

I

COM

= 100mA

0.19

0.18

0.17

0.16

(Ω)

0.15

ON

R

0.14

0.13

0.12

0.11

00.511.522.53

85°C

25°C

-40°C

V

COM

(V)

I

COM

V+ = 3V

= 100mA

FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE

50

0

-50

V+ = 3V

(Ω)

0.2

ON

R

-40°C

0.15

0.1
0 0.5 1 1.5 2

V

(V)

COM

25°C

-100

Q (pC)

-150

-200

-250

00.511.522.53

V+ = 1.8V

V

COM

(V)

FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 11. CHARGE INJECTION vs SWITCH VOLTAGE

80

70

60

50

(ns)

40

ON

t

30

20

10

0

11.522.533.544.5

-40°C

85°C

25°C

V+ (V)

50

40

85°C

30

(ns)

OFF

t

-40°C

20

10

0

1.522.533.544.5

1

25°C

V+ (V)

FIGURE 12. TURN-ON TIME vs SUPPLY VOLTAGE FIGURE 13. TURN-OFF TIME vs SUPPLY VOLTAGE

8

FN6092.1

November 4, 2004

V

AND

V

(V)

ISL43L710, ISL43L711, ISL43L712

Typical Performance Curves T

1.8

1.6

1.4

1.2

INL

1

0.8

INH

0.6

0.4

0.2

11.522.533.544.5

V

INH

V+ (V)

= 25°C, Unless Otherwise Specified (Continued)

A

-20

NORMALIZED GAIN (dB)

V

INL

V+ = 3V

0

GAIN

PHASE

RL = 50Ω
VIN = 0.2V

1 10 100 600

P-P

to 2V

P-P

FREQUENCY (MHz)

FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE FIGURE 15. FREQUENCY RESPONSE

-10
V+ = 3V

-20

-30

-40

-50

-60

-70

CROSSTALK (dB)

-80

-90

ISOLATION

CROSSTALK

10

20

30

40

50

60

70

OFF ISOLATION (dB)

80

90

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

114

PROCESS:

Submicron CMOS

0

20

40

60

80

100

PHASE (DEGREES)

-100

-110
1k 100k 1M 100M 500M10k 10M

FREQUENCY (Hz)

FIGURE 16. CROSSTALK AND OFF ISOLATION

9

100

110

FN6092.1

November 4, 2004

ISL43L710, ISL43L711, ISL43L712

Thin Dual Flat No-Lead Plastic Package (TDFN)

(DATUM B)

6

INDEX
AREA

(DATUM A)

NX (b)

5

SECTION "C-C"

A

6

INDEX
AREA

SEATING

PLANE

NX L

8

C

12

N

(A1)

D

TOP VIEW

SIDE VIEW

D2

D2/2

N-1

e

(Nd-1)Xe

REF.

BOTTOM VIEW

TERMINAL TIP

FOR EVEN TERMINAL/SIDE

2X

2X

ABC0.15

0.15

CB

L8.3x3A

8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

NOTESMIN NOMINAL MAX

A 0.70 0.75 0.80 -

E

A1 - - 0.05 -

A3 0.20 REF -

b 0.25 0.30 0.35 5,8

D 3.00 BSC -

D2 2.20 2.30 2.40 7,8

E 3.00 BSC -

E2 1.40 1.50 1.60 7,8

e 0.65 BSC -

k0.25 - - -

L 0.20 0.30 0.40 8

A3

C

0.10

//

A

0.08

C

L1 - - 0.15 1

N82

87

Nd 4 3

Rev. 2 6/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

NX k

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

E2

E2/2

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

NX b

5

0.10

BAMC

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land

C

L

L1

e

L

10

Pattern Design efforts, see Intersil Technical Brief TB389.

9. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

10. COMPLIANT TO JEDEC MO-229-WEEC-1 except for
dimensions E2 & D2.

10

FN6092.1

November 4, 2004

ISL43L710, ISL43L711, ISL43L712

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only.

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 ­A1 0.002 0.006 0.05 0.15 ­A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9
c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3
E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - ­R1 0.003 - 0.07 - -

0 5

α

o

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 2 01/03

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

11

FN6092.1

November 4, 2004