Low-Voltage, Single and Dual Supply,
Dual 4 to 1 Multiplexer Analog Switch with
Enable
The Intersil ISL43840 device is a precision, bidirectional,
analog switches configured as a a dual 4 channel multiplexer/
demultiplexer designed to operate from a single +2V to +12V
supply or from a
±2V to ±6V supply. The device has two
enable bar pins to simultaneously open all signal paths of
bank A and B.
ON resistance of 39Ω with a
±5V supply and 125Ω with a
+3.3V supply. Each switch can handle rail to rail analog
signals. The off-leakage current is only .01nA at +25
2.5nA at +85
o
C.
o
C or
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring
TTL/CMOS logic compatibility when using a single 3.3V or
+5V supply or dual
±5V supplies.
The ISL43840 is a dual 4 to 1 multiplexer device. Table 1
summarizes the performance of this part.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on NO, COM, ADD, or EN
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θ
JA
exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
o
C to 85oC
(oC/W)
JA
o
C to 150oC
o
o
C
C
Electrical Specifications: ±5V SupplyTest Conditions: V
Unless Otherwise Specified
PARAMETERTEST CONDITIONS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ON Resistance, R
R
Matching Between Channels,
ON
∆R
ON
R
Flatness, R
ON
NO or NC OFF Leakage Current,
I
NO(OFF)
or I
NC(OFF)
COM OFF Leakage Current,
I
COM(OFF)
COM ON Leakage Current,
I
COM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Input Voltage Low, V
Input Current, I
I
ADDL
ENH
DYNAMIC CHARACTERISTICS
Enable Turn-ON Time, t
Enable Turn-OFF Time, t
ON
FLAT(ON)
ENH
ENL
, I
ENL
ANALOG
, V
ADDH
, V
ADDL
, I
ADDH
ON
OFF
VS = ±4.5V, I
VS = ±4.5V, I
VS = ±4.5V, I
VS = ±5.5V, V
VS = ±5.5V, V
VS = ±5.5V, V
,
VS = ±5.5V, V
= 2mA, VNO = 3V, (See Figure 5)25-4450Ω
COM
= 2mA, VNO = 3V, (Note 5)25-1.34Ω
COM
= 2mA, VNO = ±3V, 0V, (Note 6)25-7.59Ω
COM
= ±4.5V, VNO = +4.5V, (Note 7)25-0.10.0020.1nA
COM
= ±4.5V, VNO = +4.5V, (Note 7)25-0.10.0020.1nA
COM
= VNO = ±4.5V, (Note 7)25-0.10.0020.1nA
COM
, V
ENH
= 0V or V+Full-0.50.030.5µA
ADD
VS = ±4.5V, VNO = ±3V, RL = 300Ω, CL = 35pF,
V
= 0 to 3, (See Figure 1)
IN
VS = ±4.5V, VNO = ±3V, RL = 300Ω, CL = 35pF,
V
= 0 to 3, (See Figure 1)
IN
= ±4.5V to ±5.5V, GND = 0V, V
SUPPLY
TEMP
o
(
C)
INH
(NOTE 4)
MINTYP
= 2.4V, V
= 0.8V (Note 3),
INL
(NOTE 4)
MAXUNITS
FullV--V+V
Full--80Ω
Full--6Ω
Full--12Ω
Full-2.5-2.5nA
Full-2.5-2.5nA
Full-2.5-2.5nA
Full2.4--V
Full--0.8V
25-3550ns
Full--60ns
25-2235ns
Full--40ns
3
ISL43840
Electrical Specifications: ±5V SupplyTest Conditions: V
= ±4.5V to ±5.5V, GND = 0V, V
SUPPLY
= 2.4V, V
INH
= 0.8V (Note 3),
INL
Unless Otherwise Specified (Continued)
PARAMETERTEST CONDITIONS
Address Transition Time, t
Break-Before-Make Time, t
TRANSVS
BBM
V
VS = ±5.5V, VNO = 3V, RL = 300Ω, CL = 35pF,
V
= ±4.5V, VNO = ±3V, RL = 300Ω, CL = 35pF,
= 0 to 3, (See Figure 1)
IN
= 0 to 3V, (See Figure 3)
IN
TEMP
(NOTE 4)
o
(
C)
MINTYP
(NOTE 4)
MAXUNITS
25-4360ns
Full--70ns
Full27-ns
Charge Injection, QCL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 225-0.31pC
NO/NC OFF Capacitance, C
COM OFF Capacitance, C
COM ON Capacitance, C
OFF
OFF
COM(ON)
OFF IsolationR
Crosstalk, (Note 8)25-≤110-dB
f = 1MHz, VNO = V
f = 1MHz, VNO = V
f = 1MHz, VNO = V
= 50Ω, CL = 15pF, f = 100kHz, VNO = 1V
L
= 0V, (See Figure 7)25-3-pF
COM
= 0V, (See Figure 7)25-12-pF
COM
= 0V, (See Figure 7)25-18-pF
COM
(See Figures 4 and 6)
RMS
,
25-92-dB
All Hostile Crosstalk, (Note 8)25--105-dB
POWER SUPPLY CHARACTERISTICS
Power Supply RangeFull±2-±6V
Positive Supply Current, I+V
= ±5.5V, V
S
ENH
, V
= 0V or V+, Switch On or Off25-10.11µA
ADD
Full-1-1µA
Negative Supply Current, I-25-10.11µA
Full-1-1µA
NOTES:
3. V
= logic voltage to configure the device in a given state.
IN
4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. ∆R
= RON (MAX) - RON (MIN).
ON
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
o
7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25
C.
8. Between any two switches.
Electrical Specifications +12V SupplyTest Conditions: V+ = +10.8V to +13.2V, GND = 0V, V
Unless Otherwise Specified
PARAMETERTEST CONDITIONS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ON Resistance, R
R
Matching Between Channels,
ON
∆R
ON
R
Flatness, R
ON
NO or NC OFF Leakage Current,
I
NO(OFF)
or I
NC(OFF)
ON
FLAT(ON)
ANALOG
V+ = 10.8V, I
V+ = 10.8V, I
V+ = 10.8V, I
V+ = 13.2V, V
(Note 7)
4
TEMP
= 1.0mA, VNO = 9V, (See Figure 5)25-3745Ω
COM
= 1.0mA, VNO = 9V, (Note 5)25-1.22Ω
COM
= 1.0mA, VNO = 3V, 6V, 9V, (Note 6)25-57Ω
COM
= 1V, 12V, VNO = 12V, 1V,
COM
(NOTE 4)
o
(
C)
MIN TYP
Full0-V+V
Full-55Ω
Full--2Ω
Full--7Ω
25-0.10.0020.1nA
Full-2.5-2.5nA
INH
= 4V, V
= 0.8V (Note 3),
INL
(NOTE 4)
MAXUNITS
ISL43840
Electrical Specifications +12V SupplyTest Conditions: V+ = +10.8V to +13.2V, GND = 0V, V
Unless Otherwise Specified (Continued)
PARAMETERTEST CONDITIONS
COM OFF Leakage Current,
I
COM(OFF)
COM ON Leakage Current,
I
COM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Input Voltage Low, V
Input Current, I
I
ADDL
ENH
, I
ENH
ENL
ENL
, V
, V
, I
ADDH
ADDL
ADDH
,
DYNAMIC CHARACTERISTICS
Enable Turn-ON Time, t
Enable Turn-OFF Time, t
Address Transition Time, t
ON
OFF
TRANS
V+ = 13.2V, V
(Note 7)
V+ = 13.2V, V
floating, (Note 7)
V+ = 13.2V, V
= 12V, 1V, VNO = 1V, 12V,
COM
= 1V, 12V, VNO = 1V, 12V, or
COM
, V
ENH
= 0V or V+Full-0.50.030.5µA
ADD
V+ = 10.8V, VNO = 10V, RL = 300Ω, CL = 35pF,
V
= 0 to 4, (See Figure 1)
IN
V+ = 10.8V, VNO = 10V, RL = 300Ω, CL = 35pF,
V
= 0 to 4, (See Figure 1)
IN
V+ = 10.8V, VNO = 10V, RL = 300Ω, CL = 35pF,
V
= 0 to 4, (See Figure 1)
IN
TEMP
(NOTE 4)
o
(
C)
MIN TYP
25-0.10.0020.1nA
Full-2.5-2.5nA
25-0.10.0020.1nA
Full-2.5-2.5nA
Full3.73.3-V
Full-2.70.8V
25-2440ns
Full-45ns
25-1530ns
Full-35ns
25-2750ns
Full-55ns
INH
= 4V, V
= 0.8V (Note 3),
INL
(NOTE 4)
MAXUNITS
Break-Before-Make Time Delay, t
Charge Injection, QC
OFF IsolationR
Crosstalk, (Note 8)25-≤110-dB
Power Supply RangeFull2-12V
Positive Supply Current, I+V+ = 3.6V, V- = 0V, V
Switch On or Off
ENH
, V
ADD
= 0V or V+,
25-1-0.11µA
Full-1-1µA
Positive Supply Current, I-25-1-0.11µA
Full-1-1µA
7
Test Circuits and Waveforms
ISL43840
tr < 20ns
< 20ns
t
f
90%
LOGIC
INPUT
SWITCH
OUTPUT
VNO0
0V
3V
0V
t
OFF
50%
90%
t
ON
V
OUT
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. ENABLE t
3V
LOGIC
INPUT
0V
VNO0
SWITCH
OUTPUT
VNO
0V
X
ON
t
TRANS
/ t
MEASUREMENT POINTS
OFF
50%
t
TRANS
V
OUT
10%
tr < 20ns
t
< 20ns
f
90%
Logic input waveform is inverted for switches that have the opposite
logic sense.
V+
C
V+
LOGIC
INPUT
NO0
NO1-NO3
ENABLE
GND
Repeat test for other switches. C
capacitance.
V
OUT
V
(NO)
FIGURE 1B. ENABLE t
V+
NO0
NO3
NO1-NO2
GND
V-
LOGIC
INPUT
C
V+
C
ADD1, 2
Repeat test for other switches. C
capacitance.
V
OUT
V
(NO)
V-
C
ADD1, 2
includes fixture and stray
L
------------------------------=
RLR
/ t
ON
C
ENABLE
includes fixture and stray
L
------------------------------=
RLR
C
COM
R
L
+
ON()
TEST CIRCUIT
OFF
V-
COM
R
L
+
ON()
C
V
OUT
RL
300Ω
V
OUT
RL
300Ω
C
L
35pF
C
L
35pF
FIGURE 1C. ADDRESS t
OUT
OFF
Q = ∆V
OUT
LOGIC
INPUT
SWITCH
OUTPUT
V
FIGURE 2A. Q MEASUREMENT POINTS
MEASUREMENT POINTS
TRANS
ON
x C
L
8
FIGURE 1. SWITCHING TIMES
3V
0V
∆V
OFF
OUT
FIGURE 2. CHARGE INJECTION
FIGURE 1D. ADDRESS t
R
G
NOX
0Ω
ADDX
V
G
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
V+
GND
TRANS
C
COMX
ENABLE
TEST CIRCUIT
V-
C
LOGIC
INPUT
C
1nF
V
OUT
L
Test Circuits and Waveforms (Continued)
ISL43840
LOGIC
INPUT
SWITCH
OUTPUT
V
OUT
FIGURE 3A. t
SIGNAL
GENERATOR
ANALYZER
3V
0V
V-
C
COM
ENABLE
includes fixture and stray
L
C
V
OUT
R
L
300Ω
TEST CIRCUIT
C
35pF
L
0V
t
BBM
MEASUREMENT POINTS
BBM
tr < 20ns
< 20ns
t
f
80%
V+
C
V+
LOGIC
INPUT
NO0-NO3
ADD1. 2
GND
Repeat test for other switches. C
capacitance.
FIGURE 3B. t
BBM
FIGURE 3. BREAK-BEFORE-MAKE TIME
C
ADDX
ENABLE
V-
C
0V or V+
0V or V+
V
NX
RON = V1/1mA
1mA
C
ADDX
ENABLE
V-
C
0V or V+
V+
NOX
V
1
COMX
GND
V+
NOX
COMX
GND
R
L
FIGURE 4. OFF ISOLATION TEST CIRCUITFIGURE 5. R
SIGNAL
GENERATOR
ANALYZER
C
COM
NO
ENABLE
V-
A
B
0V or V+
R
L
NO
A
ADDX
COM
V+
B
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
9
TEST CIRCUIT
ON
C
50Ω
IMPEDANCE
ANALYZER
N.C.
NOX
COMX
V+
GND
C
ADDX
ENABLE
V-
0V or V+
C
FIGURE 7. CAPACITANCE TEST CIRCUIT
ISL43840
Detailed Description
The ISL43840 analog switch offers a precise switching
capability from a bipolar
supply with low on-resistance (39Ω) and high speed
operation (t
ON
=38ns, t
It has an enable bar pin to simultaneously open all signal
paths.
The device is especially well suited for applications using
±5V supplies. With ±5V supplies the performance (R
Leakage, Charge Injection, ect.) is best in class.
High frequency applications also benefit from the wide
bandwidth, and the very high off isolation and crosstalk
rejection.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V-(see
Figure 8). To prevent forward biasing these diodes, V+ and
V- must be applied before any input signals, and input signal
voltages must remain between V+ and V-. If these conditions
cannot be guaranteed, then one of the following two
protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low R
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS
1kΩ
±2V to ±6V or a single 2V to 12V
= 19ns) with dual 5V supplies.
OFF
switch, so two small signal
ON
OPTIONAL PROTECTION
DIODE
V+
LOGIC
V
NO
V-
OPTIONAL PROTECTION
DIODE
V
COM
ON
,
Power-Supply Considerations
The ISL43840 construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL43840 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (
±6V or 12V single supply),
as well as room for overshoot and noise spikes.
This switch device performs equally well when operated with
bipolar or single voltage supplies.The minimum
recommended supply voltage is 2V or
±2V. It is important to
note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical PerformanceCurves for details.
V+ and GND power the internal lo gic (thu s se tting the d igit al
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
compatible (0.8V and 2.4V) over a V+ supply range of 2.7V
to 10V. At 12V the V
level is about 3.3V. This is still below
IH
the CMOS guaranteed high output minimum level of 4V, but
noise margin is reduced. For best results with a 12V supply,
use a logic family that provides a V
greater than 4V.
OH
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
100MHz (see Figures 17 and 18). Figures 17 and 18 also
illustrates that the frequency response is very consistent
over varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off Isolation is the
resistance to this feed through, while Crosstalk indicates the
amount of feed through from one switch to another.
Figure 19 details the high Off Isolation and Crosstalk
rejection provided by this family. At 10MHz, Off Isolation is
about 55dB in 50Ω systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
FIGURE 8. INPUT OVERVOLTAGE PROTECTION
10
ISL43840
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.
they are reverse biased differently. Each is biased by either
Typical Performance Curves T
70
60
50
40
30
20
400
(Ω)
ON
R
300
200
100
85oC
25oC
-40oC
0
2
4681012357911
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGEFIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
V- = -5V
V- = 0V
V+ (V)
= 25oC, Unless Otherwise Specified
A
V
= (V+) - 1V
COM
I
= 1mA
COM
85oC
25oC
-40oC
120
110
I
= 2mA
COM
100
90
80
70
60
50
90
80
70
(Ω)
60
ON
50
R
40
30
60
50
40
30
20
-5-3-1135
85oC
25oC
-40oC
25oC
-40oC
-4-2024
85oC
V
COM
(V)
85oC
25oC
-40oC
VS = ±5V
VS = ±2V
VS = ±3V
225
200
175
150
125
100
75
160
140
(Ω)
120
ON
100
R
80
60
100
90
80
70
60
50
40
024
85oC
25oC
135
V+ = 5V
V
COM
85oC
25oC
-40oC
V- = 0V
(V)
85oC
25oC
-40oC
I
COM
V+ = 2.7V
V- = 0V
V+ = 3.3V
V- = 0V
-40oC
= 1mA
60
55
50
45
40
(Ω)
ON
R
35
30
25
20
024681012
25oC
V
COM
V+ = 12V
V- = 0V
85oC
(V)
I
COM
-40oC
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGEFIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
11
= 1mA
ISL43840
Typical Performance Curves T
500
400
-40oC
300
200
100
(ns)
ON
t
25oC
25oC
85oC
-40oC
0
250
200
85oC
150
100
50
-40oC
0
24681012357911
25oC
V- = -5V
V- = 0V
V+ (V)
= 25oC, Unless Otherwise Specified (Continued)
A
V
COM
= (V+) - 1V
200
-40oC
150
100
(ns)
100
OFF
t
25oC
25oC
50
-40oC
0
80
85oC
60
40
20
-40oC
0
24681012
357911
85oC
25oC
V- = -5V
V- = 0V
V+ (V)
V
COM
= (V+) - 1V
FIGURE 13. ENABLE TURN - ON TIME vs SUPPLY VOLTAGEFIGURE 14. ENABLE TURN - OFF TIME vs SUPPLY VOLTAGE
300
250
200
(ns)
150
RANS
t
100
50
0
35791113
24681012
25oC
85oC
-40oC
V+ (V)
V
COM
= (V+) - 1V
V- = 0V
FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY
VOLTAGE
250
200
150
(ns)
RANS
t
100
50
0
23456
25oC
85oC
-40oC
V± (V)
V
COM
= (V+) - 1V
FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY
VOLTAGE
VS = ±5V
3
GAIN
0
-3
NORMALIZED GAIN (dB)
PHASE
RL = 50Ω
110100600
FREQUENCY (MHz)
VIN = 0.2V
P-P
to 5V
FIGURE 17. FREQUENCY RESPONSEFIGURE 18. FREQUENCY RESPONSE
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE C)
MILLIMETERS
SYMBOL
A0.800.901.00A1--0.05A2--1.009
A30.20 REF9
b0.180.230.305, 8
D4.00 BSCD13.75 BSC9
D21.952.102.257, 8
E4.00 BSCE13.75 BSC9
E21.952.102.257, 8
e 0.50 BSC-
k0.25 -- -
L0.350.600.758
L1--0.1510
N202
Nd53
Ne553
P- -0.609
θ--129
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
NOTESMINNOMINALMAX
Rev. 1 10/02
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data she ets are current before placin g orders. Information furn ished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or othe rwise under any patent or patent rights of Intersil or its subsidia ries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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