Low-Voltage, Single and Dual Supply,
8 to 1 Multiplexer and Differential 4 to 1
Multiplexer
The Intersil ISL43681 and ISL43741 devices are precision,
bidirectional, analog switches configured as an 8 channel and
a differential 4 channel multiplexer/demultiplexer. They are
designed to operate from a single +2V to +12V supply or from
a
±2V to ±6V supplies. The devices have an inhibit and inhibit
bar pin to simultaneously open all signal paths. The devices
also have a latch bar pin to lock in the last switch address.
ON resistance of 39Ω with a
±5V supply and 125Ω with a
+3.3V supply. Each switch can handle rail to rail analog
signals. The off-leakage current is only 0.1nA at +25
2.5nA at +85
o
C.
o
C or
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring
TTL/CMOS logic compatibility when using a single 3.3V or
+5V supply or dual
±5V supplies.
The ISL43681 is a single 8 to 1 multiplexer device and the
ISL43741 is a diff 4 to 1 multiplexer device. Table 1
summarizes the performance of these parts.
TABLE 1. FEATURES AT A GLANCE
CONFIGURATION
±5V R
ON
±5V t
ON/tOFF
12V R
ON
12V t
ON/tOFF
5V R
ON
5V t
ON/tOFF
3.3V R
ON
3.3V t
ON/tOFF
Package20 Ld 4x4 QFN
SINGLE 8:1 MUX,
DIFF 4:1 MUX
39Ω
32ns/18ns
32Ω
23ns/15ns
65Ω
38ns/19ns
125Ω
70ns/32ns
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
• Application Note AN520 “CMOS Analog Multiplexers and
Switches; Specifications and Application Considerations.”
FN6053
Features
• Fully Specified at 3.3V, 5V, ±5V, and 12V Supplies for
10% Tolerances
• ON Resistance (R
• ON Resistance (R
•R
Matching Between Channels, VS = ±5V. . . . . . . . . <2Ω
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on NC, NO, COM, ADD, EN, EN
, or LE exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum
current ratings.
is measured with the component mounted on a high effective thermal conductivity test board with direct die attach. See Tech Brief TB379
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. ENABLE t
ON/tOFF
MEASUREMENT POINTS
EN, LE
V+
LOGIC
INPUT
V+
LOGIC
INPUT
C
NO0
NO1-NO7
EN
V+
EN, LE
NO0
x
-NO3
NO1
x
EN
GND
x
GND
Repeat test for other switches. C
capacitance.
V
OUT
V
=
(NO or NC)
FIGURE 1B. ENABLE t
ISL43681
COM
ADDA-C
V-
C
ISL43741
COM
x
ADDA-B
includes fixture and stray
L
------------------------------
RLR
ON/tOFF
V
OUT
RL
300Ω
C
V
OUT
RL
300Ω
R
L
+
ON()
TEST CIRCUIT
C
L
35pF
CL
35pF
9
ISL43681, ISL43741
Test Circuits and Waveforms (Continued)
LOGIC
INPUT
SWITCH
OUTPUT
3V
0V
VNO0
0V
VNO
50%
t
TRANS
V
OUT
X
t
TRANS
10%
tr < 20ns
< 20ns
t
f
90%
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1C. ADDRESS t
MEASUREMENT POINTS
TRANS
FIGURE 1. SWITCHING TIMES
EN, LE
NO0
NO7
NO1-NO6
EN, LE
x
x
V+
GND
V+
x
GND
V-
LOGIC
INPUT
V-
LOGIC
INPUT
C
V+
C
ADDA-C
C
V+
C
NO0
NO3
NO1x-NO2
ADDA-B
Repeat test for other switches. C
capacitance.
V
OUT
V
=
(NO or NC)
FIGURE 1D. ADDRESS t
V-
C
ISL43681
COM
EN
C
ISL43741
COM
EN
includes fixture and stray
L
------------------------------
RLR
TRANS
C
V
OUT
RL
300Ω
V-
C
V
x
R
+
OUT
RL
300Ω
L
ON()
TEST CIRCUIT
C
L
35pF
CL
35pF
OUT
OFF
Q = ∆V
OUT
x C
ON
L
LOGIC
INPUT
SWITCH
OUTPUT
V
FIGURE 2A. Q MEASUREMENT POINTS
10
3V
0V
∆V
OFF
OUT
FIGURE 2. CHARGE INJECTION
G
EN, LE
NO or NC
ADDX
R
0Ω
V
G
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
V+
GND
V-
EN
LOGIC
INPUT
C
V
OUT
C
L
1nF
C
COM
ISL43681, ISL43741
Test Circuits and Waveforms (Continued)
LOGIC
INPUT
SWITCH
OUTPUT
V
OUT
3V
0V
0V
t
BBM
tr < 20ns
t
< 20ns
f
80%
V+
LOGIC
INPUT
V+
LOGIC
INPUT
C
COM
ISL43681
EN
C
COM
EN
V-
C
V
OUT
R
L
300Ω
V-
C
V
x
OUT
R
300Ω
L
C
35pF
C
35pF
L
L
V+
C
EN, LE
NO0-NO7
ADDA-C
GND
V+
C
EN, LE
NO0
-NO3
x
x
ADDA-B
ISL43741
GND
FIGURE 3A. t
MEASUREMENT POINTS
BBM
Repeat test for other switches. C
capacitance.
FIGURE 3. BREAK-BEFORE-MAKE TIME
FIGURE 3B. t
includes fixture and stray
L
TEST CIRCUIT
BBM
11
ISL43681, ISL43741
Test Circuits and Waveforms (Continued)
tr < 20ns
< 20ns
t
f
50%50%
t
H
50%
tON, t
OFF
90%
LOGIC
INPUT
LE
LOGIC
INPUT
ADD
X
SWITCH
OUTPUT
VNO
3V
0V
3V
0V
0V
t
MPW
50%
t
H
X
50%
V
OUT
t
S
Logic input waveform is inverted for switches that have the opposite
logic sense.
V+
C
EN
ADDA-C
LOGIC
INPUT
LOGIC
INPUT
LOGIC
INPUT
LOGIC
INPUT
LE
V+
EN
ADDA-B
LE
GND
C
GND
Repeat test for other switches. C
capacitance.
V
OUT
V
=
(NO or NC)
V-
C
NO1-NO7
NO0
ISL43681
EN
V-
NO1
x
ISL43741
EN
includes fixture and stray
L
COM
C
-NO3
x
NO0
x
COM
R
------------------------------
RLR
+
V
OUT
V
OUT
L
ON()
RL
300Ω
RL
300Ω
C
V+
CL
35pF
C
V+
CL
35pF
FIGURE 4A. LATCH t
SIGNAL
GENERATOR
ANALYZER
R
L
FIGURE 5. OFF ISOLATION TEST CIRCUIT
S
, tH, t
MEASUREMENT POINTS
MPW
V+
C
EN, LE
NO or NC
ADDX
COM
GND
EN
FIGURE 4B. LATCH t
FIGURE 4. LATCH SETUP AND HOLD TIMES
V-
C
RON = V1/1mA
V
NX
0V or V+
0V or V+
1mA
V
1
FIGURE 6. R
, tH, t
S
MPW
V+
EN, LE
NO or NC
COM
GND
TEST CIRCUIT
ON
TEST CIRCUIT
V-
C
ADDX
EN
C
0V or V+
12
ISL43681, ISL43741
Test Circuits and Waveforms (Continued)
C
COM
EN
V-
C
50Ω
A
B
N.C.
SIGNAL
GENERATOR
ANALYZER
V+
EN, LE
NOA or NC
0V or V+
R
L
FIGURE 7. CROSSTALK TEST CIRCUIT
ADDX
COM
B
A
ISL43741
NOB or NC
GND
Detailed Description
The ISL43681 and ISL43741 multiplexers offer precise
switching capability from a bipolar
to 12V supply with low on-resistance (39Ω) and high speed
operation (t
=38ns, t
ON
OFF
They have an inhibit and inhibit bar pin to simultaneously
open all signal paths. They also have a latch bar pin to lock
in the last switch address.
The devices are especially well suited for applications using
±5V supplies. With ±5V supplies the performance (R
Leakage, Charge Injection, etc.) is best in class.
High frequency applications also benefit from the wide
bandwidth, and the very high off isolation and crosstalk
rejection.
±2V to ±6V or a single 2V
= 19ns) with dual 5V supplies.
,
ON
C
ADDX
EN
V-
0V or V+
C
EN, LE
NO or NC
IMPEDANCE
ANALYZER
COM
FIGURE 8. CAPACITANCE TEST CIRCUIT
V+
GND
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 9). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS
1kΩ
LOGIC
V
NO or NC
OPTIONAL PROTECTION
DIODE
V+
V
COM
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V- (see
Figure 9). To prevent forward biasing these diodes, V+ and
V- must be applied before any input signals, and input signal
voltages must remain between V+ and V-. If these conditions
cannot be guaranteed, then one of the following two
protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 9). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low R
switch, so two small signal
ON
13
V-
OPTIONAL PROTECTION
DIODE
FIGURE 9. INPUT OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL43681 and ISL43741 construction is typical of most
CMOS analog switches, in that they have three supply pins:
V+, V-, and GND. V+ and V- drive the internal CMOS
switches and set their analog voltage limits, so there are no
connections between the analog signal path and GND.
Unlike switches with a 13V maximum supply voltage, the
ISL43681 and ISL43741 15V maximum supply voltage
provides plenty of room for the 10% tolerance of 12V
supplies (
overshoot and noise spikes.
This family of switches performs equally well when operated
with bipolar or single voltage supplies.The minimum
±6V or 12V single supply), as well as room for
ISL43681, ISL43741
recommended supply voltage is 2V or ±2V. It is important to
note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
compatible (0.8V and 2.4V) over a V+ supply range of 2.7V
to 10V. At 12V the V
level is about 3.3V. This is still below
IH
the CMOS guaranteed high output minimum level of 4V, but
noise margin is reduced. For best results with a 12V supply,
use a logic family that provides a V
greater than 4V.
OH
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
100MHz (see Figures 18 and 19). Figures 18 and 19 also
illustrates that the frequency response is very consistent
over varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off Isolation is the
resistance to this feed through, while Crosstalk indicates the
amount of feed through from one switch to another. Figure
20 details the high Off Isolation and Crosstalk rejection
provided by this family. At 10MHz, Off Isolation is about
55dB in 50Ω systems, decreasing approximately 20dB per
decade as frequency increases. Higher load impedances
decrease Off Isolation and Crosstalk rejection due to the
voltage divider action of the switch OFF impedance and the
load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.
Typical Performance Curves T
70
60
50
40
30
20
400
(Ω)
ON
R
300
200
100
85oC
25oC
-40oC
0
2
4681012357911
V- = -5V
V- = 0V
V+ (V)
A
85oC
25oC
-40oC
FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE
= 25oC, Unless Otherwise Specified
V
COM
I
COM
= (V+) - 1V
= 1mA
120
110
100
90
80
70
60
50
90
80
70
(Ω)
60
ON
50
R
40
30
60
50
40
30
20
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
I
= 1mA
COM
85oC
25oC
-40oC
25oC
-40oC
-5-3-1135
-4-2024
85oC
V
COM
(V)
85oC
25oC
-40oC
VS = ±2V
VS = ±3V
VS = ±5V
14
ISL43681, ISL43741
Typical Performance Curves T
225
200
175
150
125
100
75
160
140
(Ω)
120
ON
100
R
80
60
100
90
80
70
60
50
40
024
85oC
25oC
135
V+ = 5V
V
COM
(V)
= 25oC, Unless Otherwise Specified (Continued)
A
I
= 1mA
COM
85oC
25oC
-40oC
V- = 0V
85oC
25oC
-40oC
V+ = 2.7V
V- = 0V
V+ = 3.3V
V- = 0V
-40oC
60
I
55
50
45
40
(Ω)
ON
R
35
30
25
20
024681012
V+ = 12V
V- = 0V
25oC
V
(V)
COM
85oC
COM
-40oC
= 1mA
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGEFIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE
500
400
-40oC
300
200
100
(ns)
ON
t
25oC
25oC
85oC
-40oC
0
250
200
85oC
150
100
50
-40oC
0
24681012357911
25oC
V- = -5V
V- = 0V
V+ (V)
V
COM
= (V+) - 1V
200
-40oC
150
100
(ns)
100
OFF
t
25oC
25oC
50
-40oC
0
80
60
40
20
0
24681012
85oC
85oC
25oC
-40oC
357911
V- = -5V
V- = 0V
V+ (V)
V
COM
= (V+) - 1V
FIGURE 14. ENABLE TURN - ON TIME vs SUPPLY VOLTAGEFIGURE 15. ENABLE TURN - OFF TIME vs SUPPLY VOLTAGE
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE C)
MILLIMETERS
SYMBOL
A0.800.901.00A1--0.05A2--1.009
A30.20 REF9
b0.180.230.305, 8
D4.00 BSCD13.75 BSC9
D21.952.102.257, 8
E4.00 BSCE13.75 BSC9
E21.952.102.257, 8
e 0.50 BSCk0.25 -- L0.350.600.758
L1--0.1510
N202
Nd53
Ne553
P- -0.609
θ--129
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
NOTESMINNOMINALMAX
Rev. 1 10/02
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data she ets are current before placin g orders. Information furn ished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or othe rwise under any patent or patent rights of Intersil or its subsidia ries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
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