intersil ISL3874 DATA SHEET

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ISL3874

PRELIMINARY

Data Sheet March 2001

Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI

The Intersil ISL3874 Wireless LAN Integrated Medium Access Controller with Integrated Baseband Processor

is part of the PRISM® 2.4GHz radio chip set. The ISL3874 directly interfaces with the Intersil’s IF QMODEM (HFA3783). Adding Intersil’s RF/IF Converter (ICW3685) and Intersil’s Power Amp (HFA3983/4/5) offers the designer a complete end-to-end WLAN Chip Set solution. Protocol and PHY support are implemented in firmware thus, supporting customization of the WLAN solution.

Firmware implements the full IEEE 802.11 Wireless LAN MAC protocol. It supports BSS and IBSS operation under DCF, and operation under the optional Point Coordination Function (PCF). Low level protocol functions such as RTS/CTS generation and acknowledgment, fragmentation and de-fragmentation, and automatic beacon monitoring are handed without host intervention. Active scanning is performed autonomously once initiated by host command. Host interface command and status handshakes allow concurrent operations from multi-threaded I/O drivers. Additional firmware functions specific to access point applications are also available.

The ISL3874 has on-board A/Ds and D/A for analog I and Q inputs and outputs, for which the HFA3783 IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with Complementary Code Keying to provide a variety of data rates. Both Receive and Transmit AGC functions with 7-bit AGC control obtain maximum performance in the analog portions of the transceiver.

Built-in flexibility allows the ISL3874 to be configured through a general purpose control bus, for a range of applications. The ISL3874 is housed in a thin plastic BGA package suitable for mini PCI board applications.

The ISL3874 is designed to provide maximum performance with minimum power consumption. External pin layout is organized to provide optimal PC board layout to all user interfaces including mini PCI.

File Number 8010

Features

• Start up modes allow the mini PCI Card Information Structure to be initialized from a serial EEPROM. This Allows Firmware to be Downloaded from the Host, Eliminating the Parallel Flash Memory Device

• Firmware Can Be Loaded from Serial Flash Memory

• Zero Glue Connection to 16-Bit Wide SRAM Devices

• Low Frequency Crystal Oscillator to Maintain Time and Allow Baseband Clock Source to Power Off During Sleep Mode

• High Performance Internal WEP Engine

• Debug Mode Support Tracing Execution from On-Chip Memory

• Programmable MBUS Cycle Extension Allows Accessing of Slow Memory Devices without Slowing the Clock

• Complete DSSS Baseband Processor

• RAKE Receiver with Decision Feedback Equalizer

• Processing Gain. . . . . . . . . . . . . . . . . . . . .FCC Compliant

• Programmable Data Rate . . . . . . . 1, 2, 5.5, and 11Mbps

• Ultra Small Package. . . . . . . . . . . . . . . . . . 14mm x 14mm

• Single Supply Operation . . . . . . . . . . . . . . . . 2.7V to 3.6V

• Modulation Methods. . . . . . . . DBPSK, DQPSK, and CCK

• Supports Full or Half Duplex Operations

• On-Chip A/D and D/A Converters for I/Q Data (6-Bit, 22MSPS), AGC, and Adaptive Power Control (7-Bit)

• Targeted for Multipath Delay Spreads 125ns at 11Mbps, 250ns at 5.5Mbps

• Supports Short Preamble and Antenna Diversity

Applications

• Enterprise WLAN Systems

• PCI Card Wireless LAN Adapters

• PCN / Wireless PBX / Wireless Local Loop

• High Data Rate Wireless LAN Systems Targeting IEEE

802.11b Standard

• Wireless LAN Access Points and Bridge Products

• Spread Spectrum WLAN RF Modems

• TDMA or CSMA Packet Protocol Radios

Ordering Information

PART

NUMBER

ISL3874IK -40 to 85 192 BGA V192.14x14 ISL3874IK96 -40 to 85 Tape and Reel 1000 Units/Reel

PRISM® is a registered trademark of Intersil Americas Inc. PRISM and design is a trademark of Intersil Americas Inc.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.

TEMP.

RANGE (oC) PACKAGE

PART

NUMBER

Simplified Block Diagram

HOST

COMPUTER

DATA ADDRESS

CONTROL

ISL3874

PCI/CARD BUS 32

ON-CHIP

ROM

ON-CHIP

RAM

HOST

INTERFACE

MICRO-

PROGRAMMED

MAC ENGINE

MEMORY

CONTROLLER

WEP

ENGINE

PHY

INTERFACE

(MDI)

SERIAL

CONTROL

(MMI)

ISL3874

DATA I/O

AGC

CTL

DEMOD

I/O

MOD

ALC

1 7

6 6

THRESH.

DETECT

DAC

I ADC

Q ADC

I DAC

Q DAC

DAC

ADC

ANT_SEL

RX_RF_AGC

RX_IF_DET

RX_IF_AGC

RX_I±

RX_Q±

REF

TX_I±

TX_Q±

TX_IF_AGC

TX_AGC_IN

PRISM RADIO

RF SECTION

ADDRESS

DATA

SELECT

EXTERNAL SRAM AND

FLASH

MEMORY

MEDIUM ACCESS

CONTROLLER

BASEBAND PROCESSOR

44MHz CLOCK

SOURCE †

RADIO AND SYNTH

SERIAL CONTROL

ISL3874

ISL3874 Signal Descriptions

TABLE 1.HOST INTERFACE PINS

PIN NAME

HAD31 A8 5V Tol, CMOS, BiDir PCI address/data bus bit 31. These signals make up the multiplexed PCI address and data bus on

HAD30 A9 5V Tol, CMOS, BiDir PCI address/data bus bit 30. HAD29 C8 5V Tol, CMOS, BiDir PCI address/data bus bit 29. HAD28 A10 5V Tol, CMOS, BiDir PCI address/data bus bit 28. HAD27 B9 5V Tol, CMOS, BiDir PCI address/data bus bit 27. HAD26 B10 5V Tol, CMOS, BiDir PCI address/data bus bit 26. HAD25 C9 5V Tol, CMOS, BiDir PCI address/data bus bit 25. HAD24 A11 5V Tol, CMOS, BiDir PCI address/data bus bit 24. HAD23 B11 5V Tol, CMOS, BiDir PCI address/data bus bit 23. HAD22 B12 5V Tol, CMOS, BiDir PCI address/data bus bit 22. HAD21 A12 5V Tol, CMOS, BiDir PCI address/data bus bit 21. HAD20 A13 5V Tol, CMOS, BiDir PCI address/data bus bit 20. HAD19 C12 5V Tol, CMOS, BiDir PCI address/data bus bit 19. HAD18 A14 5V Tol, CMOS, BiDir PCI address/data bus bit 18. HAD17 C13 5V Tol, CMOS, BiDir PCI address/data bus bit 17. HAD16 C14 5V Tol, CMOS, BiDir PCI address/data bus bit 16. HAD15 E14 5V Tol, CMOS, BiDir PCI address/data bus bit 15. HAD14 E15 5V Tol, CMOS, BiDir PCI address/data bus bit 14. HAD13 F16 5V Tol, CMOS, BiDir PCI address/data bus bit 13. HAD12 F15 5V Tol, CMOS, BiDir PCI address/data bus bit 12. HAD11 F14 5V Tol, CMOS, BiDir PCI address/data bus bit 11. HAD10 G16 5V Tol, CMOS, BiDir PCI address/data bus bit 10.

HAD9 G15 5V Tol, CMOS, BiDir PCI address/data bus bit 9. HAD8 G14 5V Tol, CMOS, BiDir PCI address/data bus bit 8. HAD7 H15 5V Tol, CMOS, BiDir PCI address/data bus bit 7. HAD6 G13 5V Tol, CMOS, BiDir PCI address/data bus bit 6. HAD5 J15 5V Tol, CMOS, BiDir PCI address/data bus bit 5. HAD4 J14 5V Tol, CMOS, BiDir PCI address/data bus bit 4. HAD3 K14 5V Tol, CMOS, BiDir PCI address/data bus bit 3. HAD2 K15 5V Tol, CMOS, BiDir PCI address/data bus bit 2. HAD1 L14 5V Tol, CMOS, BiDir PCI address/data bus bit 1. HAD0 L16 5V Tol, CMOS, BiDir PCI address/data bus bit 0. HBE3 C10 5V Tol, CMOS, BiDir PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals.

HBE2 B14 5V Tol, CMOS, BiDir PCI bus commands and byte enables. HBE2 applies to byte 2 (HAD23-HAD16). HBE1 E16 5V Tol, CMOS, BiDir PCI bus commands and byte enables. HBE1 applies to byte 1 (HAD15-HAD8).

NUMBER PIN I/O TYPE DESCRIPTION

the primary interface. During the address phase of a primary bus PCI cycle, HAD31-HAD0 contain a 32-bit address or other destination information. During the data phase, HAD31-HAD0 contain data.

During the address phase of a primary bus PCI cycle, HBE3-HBE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. HBE3 applies to byte 3 (HAD31-HAD24).

ISL3874

TABLE 1.HOST INTERFACE PINS (Continued)

PIN NAME

HBE0 H16 5V Tol, CMOS, BiDir PCI bus commands and byte enables. HBE0 applies to byte 0 (HAD7-HAD0).

HINTA C6 CMOS, Output PCI Bus Interrupt A HRESET D6 5V Tol, CMOS, Input PCI reset. HFRAME B15 5V Tol, BiDir PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate

HIRDY A15 5V Tol, CMOS, BiDir PCI initiator ready. HIRDY indicates the PCI bus initiators ability to complete the current data phase

HTRDY A16 5V Tol, CMOS, BiDir PCI target ready. HTRDY indicates the primary bus targets ability to complete the current data

HREQ B7 CMOS, Output PCI bus request. HREQ is asserted by the ISL3874 to request access to the PCI bus as an initiator.

HSERR B16 CMOS, Output PCI system error. HSERR is an output that is pulsed from the ISL3874 when enabled through the

HSTOP C16 5V Tol, CMOS, BiDir PCI cycle stop signal. HSTOP is driven by a PCI target to request the initiator to stop the current

HDEVSEL D15 5V Tol, CMOS, BiDir PCI device select. The ISL3874 asserts HDEVSEL to claim a PCI cycle as the target device. As a

HPERR D16 5V Tol, CMOS, BiDir PCI bus parity. In all PCI bus read and write cycles, the ISL3874 calculates even parity across the

HGNT C7 5V Tol, CMOS, ST

HPCLK A7 5V Tol, CMOS,

HPAR B13 5V Tol, CMOS, BiDir PCI bus parity.

HIDSEL C11 5V Tol, CMOS,

HPME B8 CMOS, Output Power Management Event Output. HPME provides output for PME signals.

NUMBER PIN I/O TYPE DESCRIPTION

that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase.

of the transaction. A data phase is completed on a rising edge of PCLK where both HIRDY and HTRDY are asserted. Until HIRDY and HTRDY are both sampled asserted, wait states are inserted.

phase of the transaction. A data phase is completed on a rising edge of PCLK when both HIRDY and HTRDY are asserted. Until both HIRDY and HTRDY are asserted, wait states are inserted.

command register indicating a system error has occurred. The ISL3874 need not be the target of the PCI cycle to assert this signal. When HSERR is enabled in the control register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface.

PCI bus transaction. HSTOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers.

PCI initiator on the bus, the ISL3874 monitors HDEVSEL until a target responds. If no target responds before timeout occurs, the ISL3874 terminates the cycle with an initiator abort.

HD31-HAD0 and BE3-BE0 buses. As an initiator during PCI cycles, the ISL3874 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator. A compare error results in the assertion of a parity error (PERR).

PCI bus grant. HGNT is driven by the PCI bus arbiter to grant the ISL3874 access to the PCI bus

Input

after the current data transaction has completed. HGNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm.

HPCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

Initialization device select. HIDSEL selects the ISL3874 during configuration space accesses. HIDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

ISL3874

TABLE 2.MEMORY INTERFACE PINS

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

PL4-MA19 A4 CMOS BiDir, 2mA MBUS Address Bit 19, needed to address between 512KB and 1MB

of data store MA18 A3 CMOS BiDir, 2mA MBUS Address Bit 18 MA17 B4 CMOS BiDir, 2mA MBUS Address Bit 17 MA16 C3 CMOS TS Output, 2mA MBUS Address Bit 16 MA15 B3 CMOS TS Output, 2mA MBUS Address Bit 15 MA14 A1 CMOS TS Output, 2mA MBUS Address Bit 14 MA13 C2 CMOS TS Output, 2mA MBUS Address Bit 13 MA12 E3 CMOS TS Output, 2mA MBUS Address Bit 12 MA11 B1 CMOS TS Output, 2mA MBUS Address Bit 11 MA10 D2 CMOS TS Output, 2mA MBUS Address Bit 10

MA9 D3 CMOS TS Output, 2mA MBUS Address Bit 9 MA8 C1 CMOS TS Output, 2mA MBUS Address Bit 8 MA7 F4 CMOS TS Output, 2mA MBUS Address Bit 7 MA6 E2 CMOS TS Output, 2mA MBUS Address Bit 6 MA5 D1 CMOS TS Output, 2mA MBUS Address Bit 5 MA4 F2 CMOS TS Output, 2mA MBUS Address Bit 4 MA3 E1 CMOS TS Output, 2mA MBUS Address Bit 3 MA2 F3 CMOS TS Output, 2mA MBUS Address Bit 2 MA1 F1 CMOS TS Output, 2mA MBUS Address Bit 1

MA0 / MWEH- G2 CMOS TS Output, 2mA, 50K Pull Up MBUS Write Enable, high byte. Asserted on writes to the high-order

byte of x16 memory devices that use the JEDEC 4-wire control

interface. Also asserted (as MA[0]) when accessing the odd (high-

order) byte of a word stored in a x8 memory device. During word

accesses of x8 memory, the odd byte is accessed first. MD15 H4 CMOS, BiDir, 2mA, 50K Pull Up MBUS Data Bit 15 MD14 G1 CMOS, BiDir, 2mA, 50K Pull Up MBUS Data Bit 14 MD13 H3 CMOS, BiDir, 2mA, 50K Pull Down MBUS Data Bit 13 MD12 H2 CMOS, BiDir, 2mA, 50K Pull Down MBUS Data Bit 12 MD11 H1 CMOS, BiDir, 2mA, 50K Pull Up MBUS Data Bit 11 MD10 J3 CMOS, BiDir, 2mA, 50K Pull Up MBUS Data Bit 10

MD9 M1 CMOS, BiDir, 2mA, 50K Pull Up MBUS Data Bit 9 MD8 M3 CMOS, BiDir, 2mA, 50K Pull Down MBUS Data Bit 8 MD7 M2 CMOS, BiDir, 2mA 50K Pull Down MBUS Data Bit 7 MD6 N1 CMOS, BiDir, 2mA, 50K Pull Down MBUS Data Bit 6 MD5 N3 CMOS, BiDir, 2mA, 50K Pull Down MBUS Data Bit 5 MD4 P1 CMOS, BiDir, 2mA, 50K Pull Down MBUS Data Bit 4 MD3 N2 CMOS, BiDir, 2mA, 50K Pull Down MBUS Data Bit 3 MD2 P3 CMOS, BiDir, 2mA, 50K Pull Down MBUS Data Bit 2 MD1 R1 CMOS, BiDir, 2mA, 50K Pull Down MBUS Data Bit 1 MD0 P2 CMOS, BiDir, 2mA, 50K Pull Down MBUS Data Bit 0

ISL3874

TABLE 2.MEMORY INTERFACE PINS (Continued)

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

MLBE L3 CMOS BiDir Output, 2mA, 50K Pull Up MBUS Lower Byte Enable. Asserted when accessing the low-order

byte of x16 memory devices that use the JEDEC 5-wire control

interface.

MOE L1 CMOS TS Output, 2mA, 50K Pull Up Memory Output Enable; asserted on memory reads

MWE/ MWEL L2 CMOS TS Output, 2mA, 50K Pull Up Low (or only) Byte Memory Write Enable. Asserted on writes to x8

RAMCS K2 CMOS TS Output, 2mA, 50K Pull Up RAM Select; asserted on MBUS cycles when the address is in the

NVCS K1 CMOS TS Output, 2mA, 50K Pull Up NV Memory Select; asserted on MBUS cycles when the address is in

TABLE 3.GENERAL PURPOSE PORT PINS

PIN NAME PIN NUMBER PIN I/O TYPE

PJ4 T2 CMOS BiDir, 2mA, 50K Pull Down PE1. PE1 and PE2 are bit-encoded functions that

PJ5 T4 CMOS BiDir, 2mA, 50K Pull Down LE_IF. LE_IF and LE_RF are the corresponding serial

PJ6 P4 CMOS BiDir, 2mA LED1.

memory devices, x16 memory devices that use the JEDEC 5-wire

control inteface, or writes to the low-order byte of x16 memory

devices that use the JEDEC 4-wire control interface.

area configured as RAM

the area configured as non-volitile memory.

DESCRIPTION OF FUNCTION

(IF OTHER THAN IO PORT)

control the RF and IF sections.

enables for the IF and RF chips. The trailing edge of the latch enables (LE) are required to latch the data in the input register. The last 20 bits of data before the trailing edge of enables are latched in.

PJ7 T3 CMOS BiDir, 2mA, 50K Pull Down RADIO_PE. This signal is the power enable to the RF

and IF components, but not the baseband.

PK0 R5 CMOS BiDir, 2mA, ST, 50K Pull Down LE_RF. LE_RF and LE_IF are the corresponding serial

PK1 R4 CMOS BiDir, 2mA, 50K Pull Down SYNTHCLK. Separate signals, SYNTHCLK and

PK2 N7 CMOS BiDir, 2mA, 50K Pull Down SYNTHDATA. Separate signals, SYNTHDATA and

PK3 R6 CMOS BiDir, 2mA, 50K Pull Down PA_PE. This signal, when asserted high, enables the

PK4 T5 CMOS BiDir, 2mA, 50K Pull Down PE2. PE2 and PE1 are bit-encoded functions that

PK7 P7 CMOS BiDir, 2mA, 50K Pull Down CAL_EN. Calibrates the Rx function to eliminate DC

PL3 P8 CMOS BiDir, 2mA, 50K Pull Up TR_SW_BAR. Antenna Diversity Control PL7 T6 CMOS BiDir, 2mA, 50K Pull Down TR_SW. Antenna Diversity Control

enables for the RF and IF chips. The trailing edge of the latch enables (LE) are required to latch the data in the input register. The last 20 bits of data before the trailing edge of enable are latched in.

SYNTHDATA, are used to program the synthesizer through bit manipulation in firmware.

SYNTHCLK, are used to program the synthesizer through bit manipulation in firmware.

Tx section of the Modulator/Demodulator and RF/IF up/down converter circuits.

control the RF and IF sictions.

offset in the Rx chain.

ISL3874

TABLE 4.SERIAL EEPROM PORT CONNECTIONS

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

PJ0 P5 CMOS BiDir, 2mA, 50K Pull Up SCLK, serial clock for serial EEPROM devices PJ1 T1 CMOS BiDir, 2mA, 50K Pull Down Serial Data Out (SD) used on serial EEPROM devices which require

three and four wire interfaces, example: AT45DB011

PJ2 R3 CMOS BiDir, 2mA, 50K Pull Down Serial Data In (MISO) used on serial EEPROM devices, Used in four wire

serial devices only. Not currently supported in software. Consult the factory for additional updates on this option.

TCLKIN(CS) L4 I/O, 50K Pull Down CS used for Chip Select Output for Serial Devices which have a 4 wire

interface like the AST45DB011 and also serial data on two wire devices like the 24C08.

TABLE 5.CLOCKS PORT PINS

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

XTALIN J2 Analog Input 32.768kHz Crystal Input

XTALOUT J1 CMOS Output, 2mA 32.768kHz Crystal Output

CLKOUT A2 CMOS, TS Output, 2mA Clock Output (Selectable as MCLK, TCLK, or TOUT0)

BBP_CLK J16 Input Baseband Processor Clock. The nominal frequency for this clock is 44 MHz.

TABLE 6.BASEBAND PROCESSOR RECEIVER PORT PINS

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

RX_IF_AGC T16 O Analog drive to the IF AGC control.

RX_RF_AGC P16 O Drive to the RF AGC stage attenuator. CMOS digital.

RX_IF_DET R10 I Analog input to the receive power A/D converter for AGC control.

RXI+ R7 I Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential.

RXI- T7 I Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential.

RXQ+ R9 I Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential.

RXQ- T9 I Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential.

TABLE 7.BASEBAND PROCESSOR TRANSMITTER PORT PINS

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

TX_AGC_IN T10 I Input to the transmit power A/D converter for transmit AGC control. TX_IF_AGC R16 O Analog drive to the transmit IF power control.

TXI+ R12 O TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential.

TXI− T12 O TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differentia. TXQ+ R14 O TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential. TXQ− T14 O TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential.

ISL3874

TABLE 8.MISCELLANEOUS CONTROL PORT PINS

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

GRESET L15 I Global Reset for MAC, Active LOW

TCLKIN(CS) L4 I/O, 50K Pull

Down

ANTSEL N15 O The antenna select signal changes state as the receiver switches from antenna to antenna during

ANTSEL N16 O The antenna select signal changes state as the receiver switches from antenna to antenna during

Test_Mode C4 I Must be tied to GND. CompCap1 R15 I Compensation Capacitor. CompCap2 R13 I Compensation Capacitor. CompRes1 T15 I Compensation Resistor. CompRes2 P13 I Compensation Resistor.

DBG4

(MPCIACT)

DBG3

(CLKRUN)

DBG2

(LED2)

DBG1 B5 I/O Manufacturing Debug Signals, Leave Unconnected. DBG0 A6 I/O Manufacturing Debug Signals, Leave Unconnected.

B6 I/O Manufacturing Debug Signals, Leave Unconnected.

A5 I/O Manufacturing Debug Signals, Leave Unconnected.

C5 I/O Manufacturing Debug Signals, Leave Unconnected.

CS used for Chip Select Output for Serial Devices which have a 4 wire interface like the AST45DB011 and also serial data on two wire devices like the 24C08.

the acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 40) for differential drive of antenna switches.

the acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 39) for differential drive of antenna switches.

Connected to MPCIACT Signal on Mini-PCI Connector.

Connected to CLKRUN Signal on Mini-PCI Connector.

Used as LED2 Output Signal.

TABLE 9.POWER PORT PINS

PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION

DDA

SSA

sub

GND B2, D5, D8, D10, D12, D13,

REF

NC P15, P14, N11, M14, C15, L13,

ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with “-” are active low.

M13, P12, R11, T8, R8, P9 Power Analog DC Power Supply 2.7 - 3.6V.

P6, D4, D7, D9, D11, D14, F13,

H13, K16, M15, N5, N4, K4,

G3, E4

N13, T13, T11, N9 GND Analog Ground.

N10, P10 GND Analog Ground.

E13, H14, J13, N14, N8, N6,

R2, M4, K3, J4, G4

P11 Input Voltage Reference for A/Ds and D/As. N12 Input Current Reference for internal ADC and DAC devices. Requires 12K resistor to

M16, K13

Power Digital DC Power Supply 2.7 - 3.6V.

GND Digital Ground.

ground.

NC No Connection.

ISL3874

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V

Input, Output or I/O Voltage. . . . . . . . . . . GND -0.5V to V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

+0.5V

Operating Conditions

Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

BGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .100oC

Maximum Soldering Temperature . . . . . . . . . See Tech Brief TB334

DC Electrical Specifications (Test conditions @ 25

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Power Supply Current I Standby Power Supply Current I

CCOP CCSB

Input Leakage Current I Output Leakage Current I Logical One Input Voltage V Logical Zero Input Voltage V Logical One Output Voltage V Logical Zero Output Voltage V Input Capacitance C

OH OL

VCC = 3.6V, CLK Frequency = 44MHz - 170 TBD mA VCC = Max, Outputs Not Loaded - 3 TBD mA VCC = Max, Input = 0V or V

VCC = Max, Input = 0V or V

VCC = Max, Min 0.7V

VCC = Min, Max - - VCC*0.3 V

CC CC

- 100 TBD nA

- 300 TBD nA

IOH = -1mA, VCC = Min VCC-0.2 2.6 - V IOL = 2mA, VCC = Min - 0.05 0.2 V CLK Frequency = 1MHz. All measurements

- 5 10 pF

referenced to GND. TA = 25oC

Output Capacitance C

OUT

CLK Frequency 1MHz. All measurements

- 5 10 pF

referenced to GND. TA = 25oC

NOTE:All values in this table have not been measured and are only estimates of the performance at this time.

AC Electrical Specifications

PARAMETER SYMBOL MIN TYP MAX UNITS

CLOCK SIGNAL TIMING

OSC Clock Period (Typ. 44MHz) t High Period t Low Period t Full Scale Input Voltage (V

) TBD TBD 4 V

P-P

EXTERNAL MEMORY READ INTERFACE

MOE-Setup Time from RAMCS_ t MOE_Setup Time from MA (17..0) t MA (17..1) Hold Time from MOE_ Rising Edge t RAMCS_ Hold from MOE_ Rising Edge t MD (15..0) Enable from MOE_ Falling t MO (15..0) Disable from MOE_ Rising Edge t

EXTERNAL MEMORY WRITE INTERFACE

MA (17..0) Setup to MWE_ Falling Edge t RAMCS_ Setup to MWE t MA (17..0) Hold from MWE_ Rising Edge t RAMCS _ Hold from MWE_ Rising Edge t MD (15..0) Setup to MWE_ Rising Edge t MD (15..0) Hold from MWE_ Rising Edge t

CYC

H1 L1

S1 S2 H1 H2 E1 D1

S3 S4 H3 H4 S5 H5

22.5 20.8 200 ns 10 10.4 - ns 10 10.4 - ns

0 - - ns

0 20 - - ns 20 - - ns

0 0 0 ns

0 - - ns 15 - - ns 15 - - ns 40 - - ns 15 - - ns

- - V

- ns

100 ns

ISL3874

AC Electrical Specifications (Continued)

PARAMETER SYMBOL MIN TYP MAX UNITS

SYNTHESIZER

SYNTHCLK(PK1) Period t SYNTHCLK(PK1) Width Hi t SYNTHCLK(PK1) Width Lo t SYNTHDATA(PK2) Hold Time from Falling Edge of SYNTHCLK(PK1) t SYNTHCLK(PK1) Falling Edge to SYNLE Inactive t

CYC

H1 L1 D2 D3

SYSTEM INTERFACE - PCI TIMING

Cycle Time, HPCLK t Pulse Duration, HPCLK High t Pulse Duration, HPCLK Low t Slew Rate, HPCLK t Propagation Delay Time, HPCLK to Signal Valid Delay Time t Propogation Delay Time, HPCLK to Signal Invalid Delay Time t Enable Time, High Impedance to Active Delay Time from HPCLK t Disable Time, Active to High Impedance Delay Time from HPCLK t Setup Time Before HPCLK Valid t Hold Time After HPCLK High t

CYC

L S V

INV

DIS

BASEBAND SIGNALS

Full Scale Input Voltage (V

) 0.25 0.50 1.0 V

P-P

Input Bandwidth (-0.5dB) - 20 - MHz Input Capacitance - 5 - pF Input Impedance (DC) 5 - - kΩ FS (Sampling Frequency) - - 22 MHz

90 - 4,000 ns

/2 - 10 - t

CYC

/2 - 10 - t

CYC

/2 + 10 ns

CYC

/2 + 10 ns

CYC

0 - - ns 35 - - ns

30 - - ns 11 - - ns 11 - - ns

1 - 4 V/ns

- - 11 ns 2 - - ns 2 - - ns

- - 28 ns 7 - - ns 0 - - ns

Waveforms

ADDRESS

MA(17..1)

RAMCS

MOE

MD(15..0)

FIGURE 1.MAC EXTERNAL MEMORY READ TIMING

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