intersil ISL3873A DATA SHEET

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ISL3873A

Data Sh eet Septemb er 2001

Wireless LAN Integrated Medium Access Controller with Baseband Processor

The Intersil ISL3873A Wireless LAN IntegratedMediumAccess Controller with Integrated Baseband Processor

is part of the PRISM® 2.4GHz radio chip set. The ISL3873A directly interfaces wi th t he Intersil’s IF QMODEM (HFA3783).AddingIntersil’sRF/IF Converter (ISL3685) and Intersil’s Power Amp (HFA3983) offers the designera completeend-to-endWLAN Chip Set solution. Protocoland PHY support are implemented in firmwarethus, supporting customization of the WLAN solution.

Firmware implements the full I EEE 802.11 Wireless LAN MAC protocol. It supports BSS and IBSS operation under DCF, and operation under the optional Point Coordination Function (PCF). Low level protocol functions such as RTS/CTS generation and acknowledgment,fragmentation and de-fragmentation, and automatic beacon monitoring are handled without host intervention. Active scanning is performed autonomously once initiated by host command. Host interface command and status handshakes allow concurrentoperations from multi-threaded I/O drivers. Additional firmware functions specific to access point applicationsare also available.

The ISL3873A has on-board A/Ds and D/A for analog I and Q inputsand outputs, for which the HFA3783IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability,are available along with Complementary Code Keying to provide a variety of data rates. Both Receive and Transmit AGC functions with 7-bit AGC control obtain maximum per formance in the analog portions of the transceiver.

Built-in flexibility allows the ISL3873A to be configured through a general purpose control bus, for a range of applications. The ISL3873A is housed in a thin plastic BGA package suitable for PCMCIA board applications.

The ISL3873A is designed to provide maximum performancewi th minimum power consumption.Externalpin layout is organized t o provide optimal PC board layout to all user interfaces including PCMCIA and USB.

Ordering Information

PART

NUMBER

ISL3873AIK -40 to 85 192 BGA V192.14x14 ISL3873AIK-TK -40 to 85 Tape and Reel 1000 Units/Reel

TEMP.

RANGE (

C) PACKAGE

PART

NUMBER

File Number 8015.2

Features

• PCMCIA Host Interface and compatibility with USB V1.1.

• New Start Up Modes Allow the PCMCIA Car d Information Structure to be Initialized From a Serial EEPROM. This Allows Firmware to be Downloaded from the Host, Eliminating the Parallel Flash Memory Device

• Firmware Can be Loaded from Serial Flash Memory

• Zero Glue Connection to 16-Bit Wide SRAM Devices

• Low Frequency Crystal Oscillator to Maintain Time and Allow Baseband Clock Source to Power off During Sleep Mode

• Improved Performance of I nternal WEP Engine

• Improvementsto Debug Mode Support Tracing Execution From on Chip Memory

• Programmable MBUS Cycle Extension Allows Accessing of Slow Memory Devices Without Slowing the Clock

• Complete DSSS Baseband Processor

• RAKE Receiver with Decision Feedback Equalizer

• ProcessingGain.....................FCCCompliant

• ProgrammableDataRate........1,2,5.5,and11Mbps

• UltraSmallPackage.....................14x14mm

• SingleSupplyOperation ................2.7Vto3.6V

• Modulation Methods. . . .....DBPSK, DQPSK, and CCK

• Supports Full or Half Duplex Operations

• On-Chip A/D and D/A Converters f or I/Q Data (6-Bit, 22MSPS), AGC, and Adaptive Power Control (7-Bit)

• Targetedfor MultipathDelay Spreads 125ns at 11Mbps, 250ns at 5.5Mbps

• Supports Short Preamble and Antenna Diversity

Applications

• PC Card Wireless LAN Adapters

• USB and PCMCIA Wireless LAN Adapters

• PCN / Wireless PBX / Wireless Local Loop

• High Data Rate Wireless LAN Systems Targeting IEEE

802.11b Standard

• Wireless LAN Access Points and Bridge Products

• Spread Spectrum WLAN RF Modems

• TDMA or CSMA Packet Protocol Radios

• PCI Wireless LAN Cards (Using Ext. Br idge Chip)

• ISA, ISA PNP WLAN Cards

Microsoft® and Windows® are registered trademarks of Microsoft Corporation.

PRISM® is a registered trademark of Intersil Americas Inc.

PRISM and design is a trademark of Intersil Americas Inc.

CAUTION: These devices aresensitiveto electrostatic discharge;followproperIC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil andDesign is a trademark of IntersilAmericasInc.

Simplified Block Diagram

HOST

COMPUTER

DATA ADDRESS CONTROL

ISL3873A

USB

ON-CHIP

ROM

ON-CHIP

RAM

PC CARD

HOST

INTERFACE

MICRO-

PROGRAMMED

MAC ENGINE

CONTROLLER

WEP

ENGINE

MEMORY

USB

HOST

INTERFACE

SERIAL

CONTROL

PHY

(MDI)

(MMI)

ISL3873A

DATA I/O

AGC CTL

DEMOD

I/O

MOD

ALC

PRISM RADIO

ANT_SEL

DETECT

DAC

I ADC

Q ADC

I DAC

6 6

Q DAC

DAC

ADC

RX_RF_AGC

RX_IF_DETTHRESH.

RX_IF_AGC

RXI±

RXQ±

REF

TXI±

TXQ±

TX_IF_AGC

TX_AGC_IN

RF SECTION

ADDRESS

DATA

SELECT

EXTERNAL SRAM AND

FLASH

MEMORY

MEDIUM ACCESS

CONTROLLER

BASEBAND PROCESSOR

44MHz CLOCK

SOURCE †

†

THE ISL3873A MUST BE SUPPLIED WITHA SEPARATE CLOCK WHEN USB IS USED.

RADIO AND SYNTH

SERIAL CONTROL

ISL3873A

ISL3873A Signal Descriptions

Host InterfaceP ins

PIN NAME PIN I/O TYPE DESCRIPTION

HA0-9 5V tol, CMOS, Input, 50K Pull Down Host PC Card Address Input,Bits 0 to 9 HCE1- 5V tol, CMOS, Input, 50K Pull Up Host PC Card Select, Low Byte HCE2- 5V tol, CMOS, Input, 50K Pull Up Host PC Card Select, High Byte HD0-15 5V tol, BiDir, 2mA, 50K Pull Down Host PC Card Data Bus, Bit 0 to 15 HINPACK- CMOS Output, 2mA Host PC Card I/O Decode Confirmation HIORD- 5V tol, CMOS, Input, 50K Pull Up Host PC Card I/O Space Read Strobe HIOWR- 5V tol, CMOS, Input, 50K Pull Up Host PC Card I/O Space Write Strobe HRDY/HIREQ- CMOS Output, 4mA Host PC Card interrupt Request (I/O Mode), also use d as PC Card

HOE- 5V tol, CMOS, Input, 50K Pull Up Host PC Card Memory Attribute Space Output Enable HREG- 5V tol, CMOS, Input, 50K Pull Up Host PC Card Attribute Space Select RESET 5V tol, CMOS, ST Input, 50 K Pull Up Hardware Reset. Self-asserted by internal pull-up at power-on. Clock

HSTSCHG- CMOS Output, 4mA Host PC Card Status Change HWAIT- CMOS Output, 4mA Host Wait, asserted to indicate data transfer not complete and to force

HWE- 5V tol, CMOS Input, 50K Pull Up Host PC Card Memory Attribute Space Write Enable

USB INTERFACE PINS

PIN NAME PIN I/O TYPE DESCRIPTION

USB+ CMOS BiDir, 2mA, (Also USB Transceiver) USB, MBUS Address Bit 20, or I/O as PL5 USB- CMOS BiDir, 2mA, (Also USB Transceiver) USB, MBUS Address Bit 21, or I/O as PL6 USB_DETECT Input, 5V tolerant, pull-down Sense USB VBUS to indicate cable attachment

Ready (Memory Mode) output which is asserted to indicate card initialization is complete

signal CLKIN or XTALIN must be available before negation of Reset. Value of MD[15..0] copied to MDIR[15..0] and various control register bits on the f irst MCLK following releaseof Reset

force host bus wait states

Memory Interface Pins

PIN NAME PIN I/O TYPE DESCRIPTION

MUBE- / MA0 / MWEH-

MA1-18 CMOS TS Output, 2mA MBUS Address Bits 1 to 18 PL4-MA19 CMOS B iDir, 2mA MBUS Address Bit 19 MLBE- CMOS TS Output, 2mA, 50K Pull Up MBUS Lower Byte Enable, or I/O as PM2 MOE- CMOS TS Output, 2mA MemoryOutputEnable MWE- / MWEL- CMOS TS Output, 2mA Low (or only) Byte Memory Write Enable RAMCS- CMOS TS Output, 2mA RAM Select NVCS- CMOS TS Output, 2mA NV Memory Select MD0-7 5Vtol, CMOS, BiDir,2mA, 100K Pull Up MBUS Low Data Byte,Bits 0 to 7 MD8-15 5Vt ol, CMOS, BiDir, 2mA

CMOS TS Output, 2mA MBUS Upper Byte Enable for x16 Memory; MBUS Address Bit 0 (byte)

50K Pull-Downs on MD15, MD14, MD13, MD11, MD10, MD09 50K Pull-Ups MD12, MD08

for x8 Memory; High Byte Write Enable for 2 x8 Memories

MBUS High Data Byte, Bits 8 to 15 Defaultpowerup states are defined by pull-upand pull-down internal resistors as shown. Device defaults to external EEPROM for boot up mode. Using external 10K resistors, configure these pins according to Table 4 to change power-upconfiguration

ISL3873A

MAC Radio Interface and General Purpose Port Pins

DESCRIPTION OF FUNCTION

PIN NAME PIN I/O TYPE

PJ4 CMOS BiDir, 2mA PE1 PJ5 CMOSBiDir,2mA,50KPullUp LE_IF PJ6 CMOS BiDir, 2mA LED1 PJ7 CMOS BiDir, 2mA, 50K Pull Up RADIO_PE PK0 CMOSBiDir,2mA,ST,50KPullDown LE_RF PK1 CMOS BiDir, 2mA, 50K Pull Down SYNTHCLK PK2 CMOS BiDir, 2mA, 50K Pull Down SYNTHDATA PK3 CMOS BiDir, 2mA PA_PE PK4 CMOS BiDir, 2mA PE2 PK7 CMOS BiDir, 2mA CAL_EN PL3 CMOS BiDir, 2mA TR_SW_BAR PL7 CMOSBiDir,2mA,PullDown TR_SW

SERIAL EEPROM PORT PINS

PIN NAME PIN I/O TYPE DESCRIPTION

PJ0 CMOS BiDir SCLK, Serial Clock PJ1 CMOS BiDir, 50K Pull Down SD, Serial Data Out PJ2 CMOS BiDir, 50K Pull Down MISO, Serial Data IN TCLKIN (CS_) CMOS BiDir CS_, Chip Select

Clocks Port Pins

PIN NAME PIN I/O TYPE DESCRIPTION

CLKIN CMOS Input, 50K Pull Down External Clock Input to MCLK prescaler (at >= 2X Desired MCLK

Frequency, Typically 44-48MHz) XTALIN Analog I nput 32.768kHz Crystal Input XTALOUT CMOS Output, 2mA 32.768kHz Crystal Output CLKOUT CMOS, TS Output, 2mA Internal Clock Output (Selectable as MCLK, TCLK, or TOUT0) BBP_CLK Input BasebandProcessor Clock.The nominal frequency for this clock is

44MHz.This is used internally to generate divideby 2 and 4 for the

transceiverclock

(IF OTHER THAN I/O PORT)

Baseband Processor Receiver Port Pins

PIN NAME PIN I/O TYPE DESCRIPTION

RX_IF_AGC O Analog drive to the IF AGC control RX_RF_AGC O Drive to the RF AGC stage attenuator.CMOS digital RX_IF_DET I Analog input to the receive power A/D converter for AGC control RXI, ± I Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11RXQ, ± I Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14-

Baseband Processor Transmitter Port Pins

PIN NAME PIN I/O TYPE DESCRIPTION

TX_AGC_IN I Input to the transmitpower A/D converter for transmitAGC control TX_IF_AGC O Analog drive to the transmit IF power control TXI ± O TX Spread baseband I digital output data. Data is output atthe chiprate. Balanced differential 23+/24TXQ ± O TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential

29+/30-

ISL3873A

Misc Control Port Pins

PIN NAME PIN I/O TYPE DESCRIPTION

ANTSEL

ANTSEL O The antenna select signalchangesstate as the receiver switches from antenna to

TestMode I/O Factoryleveltest pin. This pin must be pulled low with a 10K resistor. CompCap1 I Compensation Capacitor CompCap2 I Compensation Capacitor CompRes1 I Compensation Resistor CompRes2 I Compensation Resistor DBG(0-4) I/O Debug factory test signals. Do not connect

PIN NAME PIN I/O TYPE DESCRIPTION

DDA

SUPPLY5V Power 5V Tolerant DC Power Supply V

SSA

sub

GND Ground Digital Ground VREF Input Voltage Reference for A/D’s and D/A’s IREF Input CurrentReferencefor internalADC and DAC devices. Requires12K resistorto ground. ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with “-” are active low.

O The antenna select signalchangesstate as the receiver switches from antenna to

antennaduringthe acquisitionprocessin the antenna diversity mode. This is a complement for ANTSEL (pin 40) for differentialdrive of antennaswitches

antennaduringthe acquisitionprocessin the antenna diversity mode. This is a complement for ANTSEL

(pin 39) for differential drive of antenna switches

Power Port Pins

Power DC PowerSupply2.7 - 3.6V (Not HardwiredTogetheron Chip) Power DC PowerSupply2.7 - 3.6V

Ground Analog Ground Ground Analog Ground

ISL3873A Pin Number Assignments

PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PI N NUMBER SIGNAL NAME

A1 NC C7 HD4 F4 MA5 K16 V

A2 MA10 C8 HD6 F13 HD9 A3 MA13 C9 HD14 F14 HD10 L1 MD8 A4 MA16 C10 HD11 F15 HA2 L2 MD7 A5 GND C11 HD7 F16 HA1 L3 MD10 A6 PL4_MA19 C12 HA7 L4 MD9 A7 DBG2 C13 GND G1 MD12 L13 GND A8 V

A9 HD3 C15 NC G3 V

C14 DBG3 G2 MD14 L14 R X_RF_AGC

L15 ANT_SEL A10 HCE2 C16 RESET G4 MA2 L16 ANT_SEL A11 GND G13 GND A12 HD15 D1 MA3 G14 HSTSCHG M1 MD5 A13 HA9 D2 MA8 G15 HD0 M2 V A14 V

D3 MA7 G16 BBP_CLK M3 GND

A15 HA6 D4 MA14 M4 MD6 A16 NC D5 MA17 H1 V

M13 V

DDA

D6 DBG0 H2 MLBE M14 COMPCAP1

B1 V

D7 GND H3 MD11 M15 GND

ISL3873A

ISL3873A Pin Number Assignments (Continued)

PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PI N NUMBER SIGNAL NAME

B2 NC D8 HD5 H4 MD13 M16 V B3 MA9 D9 HIREQ H13 HD2 B4 MA12 D10 HIOWR H14 HD1 N1 MD4 B5 V

D11 HOE H15 HA0 N2 MD0 B6 MA18 D12 NC H16 HD8 N3 MD3 B7 DBG1 D13 HA5 N4 MD2 B8 HD12 D14 HWAIT J1 XTALIN N5 NC B9 HCE1 D15 SUPPLY5V J2 XTALOUT N6 PJ7

B10 V

D16 HREG J3 RAMCS N7 PK2

B11 HIORD J4 NVCS N8 VDDA B12 HA8 E1 GND J13 USB_DET N9 V B13 HWE E2 MA4 J14 V

N10 V B14 HA4 E3 GND J15 USB- N11 V B15 NC E4 NC J16 USB+ N12 IREF B16 DBG4 E13 HA3 N13 V

E14 V

K1 CLKIN N14 NC C1 MA6 E15 HINPACK K2 MOE N15 RX_IF_AGC C2 NC E1 6 GND K3 MWEL N16 TX_IF_AGC C3 MA11 K4 GND C4 MA15 F1 MD15 K13 TESTMODE C5 CLKOUT F2 MA1 K14 GND C6 HD13 F3 MWEH_MA0 K15 GND P1 MD1 R1 PJ1

(SDATA)

P2 PJ2

R2 NC T2 V

(MISO)

T1 PJ0

(SCLK)

P3 TCLKIN R3 NC T3 PJ6

(LED1)

P4 PJ5

(LE_IF)

P5 GND R5 PK0

P6 PL7

(TR_SW)

P7 PK7

R4 PJ4

(PE1)

T4 PK1

(SYNTHCLK)

T5 PK4

(LE_RF)

R6 PK3

(PA_PE)

T6 PL3

(PE2)

(TR_SW_BAR)

R7 RXI+ T7 RXI-

(CAL_EN)

P8 V

DDA

R8 V

DDA

T8 V

DDA

P9 GND R9 RXQ+ T9 RXQP10 V

SUB

P11 VREF R11 V P12 V

DDA

P13 COMPRES2 R13 COMCAP2 T13 V

R10 RX_IF_DET T10 TX_AGC_IN

DDA

T11 V

SSA

R12 TXI+ T12 TXI-

SSA

P14 N C R14 TXQ+ T14 TXQP15 NC R15 NC T15 COMPRES1 P16 NC R16 NC T16 NC

(RADIO_PE)

(SYNTHDATA)

SSA SUB

SSA

ISL3873A

Absolute M axi m um Rati ng s Thermal Information

Supply Voltage, VCC.................................3.6V

Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to V

+0.5V

ESDClassification.................................Class2

Operating Conditions

Voltage...........................................+3.3V

AmbientTemperatureRange...................-40

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mountedon a low effectivethermalconductivity test boardin free air. See Tech Brief TB379 for details.

1. θ

Cto85oC

DC El ectri cal Specifications

PARAMETER SYMBOL TE ST COND ITIONS MIN TYP MAX UNITS

Power Supply Current I

CCOP

Input Leakage Current I Output Leakage Current I Logical One Input Voltage V Logical Zero Input Voltage V Logical One Output Voltage V Logical Zero Output Voltage V Input Capacitance C

Output Capacitance C

OUT

NOTE: All values in this table have not been measured and are only estimates of the performance at this time.

VCC= 3.6V, CLK Frequency 44MHz - - 175 mA VCC= Max, Input = 0V or V

VCC= Max, Input = 0V or V

VCC= Max, Min 0.7V

VCC= Min, Max - - 0.3V V

IOH=-1mA,VCC=Min 0.9V

IOL=2mA,VCC=Min - 0.1 0.1V

CLK Frequency 1MHz. All measurements

referenced to GND. T CLK Frequency 1MHz. All measurements

referenced to GND. T

Thermal Resistance (Typical, Note 1) θ

BGAPackage.............................. 56

MaximumStorageTemperatureRange.......... -65

MaximumJunctionTemperature.......................100

MaximumLead Temperature(Soldering 10s) . . . . . . . . . . . . .300

(Lead Tips Only)

CC CC

-10 1 10 mA

--V

-510pF

=25oC

-510pF

=25oC

(oC/W)

Cto150oC

AC El ectri cal Specifications

PARAMETER SYMBOL MIN TYP MAX UNITS

CLOCK SIGNAL TIMING

OSC Clock Period (Typ. 44MHz) t High Period t Low Period t

EXTERNAL MEMORY READ INTERFACE

MOE-Setup Time from RAMCS_ t MOE_Setup Time from MA (17..0) t MA(17..1)HoldTimefromMOE_RisingEdge t RAMCS_ Hold from MOE_ Rising Edge t MD (15..0) Enablefrom MOE_ Falling t MO (15..0) Disable from MOE_ RisingEdge t

EXTERNAL MEMORY WRITE INTERFACE

MA ( 17..0) Setup t o MWE_ Falling Edge t RAMCS_ Setup to MWE t MA(17..0)HoldfromMWE_RisingEdge t RAMCS _ Hold from MWE_ Rising Edge t MD (15..0) Setup to MWE_ Rising Edge t MD(15..0)HoldfromMWE_RisingEdge t

SYNTHESIZER

SYNTHCLK(PK1) Period t

CYC

S1 S2 H1 H2 E1 D1

S3 S4 H3 H4 S5 H5

CYC

20 20.8 200 ns 10 10.4 - 10 10.4 - -

0--ns 0

-ns 20 - - ns 20 - - ns

-ns

100 ns

000ns

0--ns 15 - - ns 15 - - ns 40 - - ns 15 - - ns

83 - 4,000 ns

ISL3873A

AC El ectri cal Specifications (Continued)

PARAMETER SYMBOL MIN TYP MAX UNITS

SYNTHCLK(PK1) Width Hi t SYNTHCLK(PK1) Width Lo t

SERIAL PORT

SYNTHCLK(PK1) Clock Period t Low Width t Delay from Clock Falling Edge to SPCSx, SPAS, SPREAD,

SYNTHDATA(PK2) Outputs Setup Time of SYTHNDATA(PK2) Read to SYTHNCL K(PK1) F alling Edge t Hold Time of SYTHNDATA(PK2) Read from SYTHNCLK(PK1) Falling Edge t Hold Time of SYTHNDATA(PK2) Write from SYTHNCLK(PK1) Falling Edge t

CYC

H1,tL1

DRS DRH

DWH

SYSTEM INTERFACE - PC CARD IO READ 16

Data Delay After HIORD- t Data Hold Following HIORD- t HIORD- Width Time t Address Setup Before HIORD- t Address Hold Following HIORD- t HCE(1,2)- Setup Before HIORD- t HCE(1,2)- Hold After HIORD- t HREG- Setup Before HIORD- t HREG- Hold Following HIORD- t HINPACK- Delay Falling from HIORD- t HINPACK- Delay Rising from HIORDN d HWAIT- t Data Delay from HWAIT- Rising t HWAIT- Width Time t

DIORD HIORD WIORD

SUA

SUCE

HCE

SUREG

HREG

DFINPACK

DRINPACK

DFWT

DRWT

WWT

SYSTEM INTERFACE - PC CARD IO WRITE 16

Data Setup Before HIOWR- t Data Hold Following HIOWR- t HIOWRN- Width Time t Address Setup Before HIOWR- t Address Hold Following HIOWR- t HCE(1,2)- Setup Before HIOWR- t HCE(1,2)- Hold Following HIOWR- t HREG- Setup Before HIOWR- t HREG- Hold Following HIOWR- t HWAIT- Delay Falling from HIOWR- t HWAIT- Width Time t HIOWRN High from HWAIT- High t

SUIOWR

HIOWR WIOWR

SUA

SUCE

HCE

SUREG

HREG DFWT

WWT

DRIOWR

BASEBAND SIGNALS

Full Scale Input Voltage (V

) 0.25 0.50 1.0 V

P-P

Input Bandwidth (-0.5dB) -20-MHz Input Capacitance -5-pF Input Impedance (DC) 5--kΩ FS (Sampling Frequency) --22MHz

/2- 10 - t

CYC

/2- 10 - t

CYC

/2+ 10 ns

CYC

/2+ 10 ns

CYC

83ns - 4000 ns

/2 -10 - t

CYC

/2 + 10 ns

CYC

-10-ns

15 - - ns

0--

--100ns

0--ns

165 - - ns

70 - - ns 20 - - ns

5--ns 20 - - ns

5--ns

0--ns

0 - 45 ns 30 - 45 ns

- - 35 ns

--0ns

- - 12,000 ns

30 - 92 ns 20 - - ns

165 - - ns

70 - - ns 20 - - ns

5--ns 20 - - ns

5--ns

0--ns

- - 35 ns

- - 12,000 ns

0--ns

Waveforms

ADDRESS

MA(17..1)

RAMCS_

MOE_

MD(15..0)

ISL3873A

FIGURE 1. EXTERNAL M EM ORY READ TIMING

ADDRESS

MA(17..1)

RAMCS_

MWE_

MD(15..0)

SYNTHCLK

FIGURE 2. EXTERNAL MEM O RY WRITE TIMING

H1tL1

SYNLE

SPCSPWR

SYNTHDATA

CYC

D[n] D[n-1] D[n -2] D[2] D[1] D[0]

FIGURE 3. SYNTHESIZER

Waveforms (Continued)

HA[15:0]

HREG-

ISL3873A

SUREG

HREG

HCE(1, 2) -

HIORD-

HINPACK-

HWAIT-

HD[15:0]

HA[15:0]

SUA

SUCE

WIORD

DIORD

DFINPACK

DFWT

WWT

FIGURE 4. PC CARD IO READ 16

HCE

DRWT

DRINPACK

HIORD

SUREG

HREG

HREGN-

SUCE

HCE

HCE (1, 2) -

SUA

WIOWR

HIOWR-

DRINPACK

DRIOWR

HWAIT-

SUIOWR

DFWT

WWT

HIOWR

HD[15:0]

FIGURE 5. PC CARD IO WRITE 16

ISL3873A MAC System Overview

ISL3873A

MA0/MWEH_

RAMCS_

MD0..15

MA1..17

NVCS_

MOE_

SRAM

128Kx8

MD0..7 MA1..17

OE_

MWEL_

WE_

CS_

FIGURE 6. 8-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873A

FLASH

128Kx8

MD0..7

MA0..16

CS_

OE_

SRAM

128Kx8

MD8..15

MA1..17 OE_

WE_ CS_

ISL3873A

MA1..17

MD0..15

NVCS-

MA0/MWEH-

SRAM

128Kx16

ADDR(0..16) DATA(0..15) UB-

MLBE-

RAMCS-

MOE-

MWEL-

LBCE-

OE WE

FIGURE 7. 16-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873A

FLASH

128Kx16

ADDR(0..16)

DATA(0..15) CE-

OEWE

ISL3873A

LARGE SERIAL EEPROM

MISO (PJ2)

SD (PJ1)

ISL3873A

SCLK (PJ0)

CS# (TCLKIN)

PULLUP

SCK

PULLUP

RESET#

WP#

45DB011

FIGURE 8. SERIAL EEPROM INTERFACE

External Memory Interface

The ISL3873A provides separate external chip selects for code space and data storage space. Code space is accessibleas data space through an overlay mechanism, except for an internal ROM. Refer to Figures 6, 7 and 8 for ISL3873A memory configuration detail examples.

The maximum possible memory space size is 4Mbytes. If USB is the host i nterface, this is reduced to 1Mbyte.

Most of the data store space is reserved for storage of receivedand transmitted data,with some areas reserved f or use by firmware. However,a portion of the data store may be allocated as code store. This permits higher speed instruction execution, by using fast RAMs, than is possible from Flash memories. The maximum size of this overlay is the full code space address range, 128Kbytes, and is allocated in independent sections of 16KBytes each, on 16Kbyteboundaries,ranging from the highestaddress of the actual physical memory space and extending down.

Mapping code execution to RAM requires the RAM to have code written into it. Typically,this is done by placing code in a non-volatile memory such as a Flash in the code space. At initialization, the code in the non-volatile memory transfers itself to RAM, maps the appropriate blocks of the code space to the RAM, and then branches to begin execution from RAM. This allows low cost, slow Flash devices to hold an entire code image, which can be executed much faster from RAM. If code is not placed in an external non-volatile memory as described here, it must be transferred to the RAM via the Host Interface.

Slow memories are not dynamically sensed. Followingreset, the instructionclock operates with a slower cycle while the Flash is copied to RAM. Once code has been copied from Flash to RAM, execution transfers to RAM and the clock is raised t o the normal operating frequency.

As mentioned above, it is feasible to operate without a code image in a non-volatile memory. In such a system, the

SMALL SERIAL EEPROM

PULLUP

ISL3873A

NOTE: Must operate at 400kHz AT 3.3V

CS# (TCLKIN)

SCLK (PJ0)

SDA

SCL

24C08 (NOTE)

A1 A2

firmware must be downloaded to RAM through t he host interface before operation can commence.

The external SRAM memory must be organized in a 16-bit width t o provide adequate performanceto implement the

802.11 protocol at 11Mb/srates. Systems designed for lower performanceapplications may be able to use 8-bit wide memory.

The minimum external memory is 128Kbytes of SRAM, organized 8 or 16 bits wide. Typical applications, including

802.11 station designs, use 256Kbytes organized 128K x 16. An access point application could make use of the full address space of the device with 4Mbytes organized a 2M x 16.

The ISL3873A supports8 or 16-bitcode space, and 8 or 16bit data space. Code space is typically populated with the leastexpensive Flash memoryavailable, usuallyan 8-bit device. Data space is usually populated with high-speed RAMsconfigured as a 16-bit space.This mixing of 8/16 bit spaces is fully supported, and may be done in any combination desired for code and data space.

The ISL3873A supports direct control of single chip 16-bit wide SRAMs with high/low byte enables, as well as direct controlof a 16-bit space constructed from 8-bit wide SRAMs. The type of memory configuration is specified via the appropriate MD pin, sensed when the ISL3873A is reset.

ISL3873A pin MUBE-/MA0/MWEH- functions as Address 0 for 8-bit access, (such as Flash) as M WEH (High Byte Write Enable) when two x8 memories are configured as a single x16 space, and as the upper Byte Enable when a single x 16 memory is used. No external logic is required to generate the required signalsfor both types of memory configurations, even when both exist together; all that is required is for the ISL3873A code to configure the ISL3873A memory controller to generate the proper signals for t he particular address space being accessed.

ISL3873A

For 8-bit spaces, the ISL3873A dynamically configures pin MUBE-/MA0/MWEH- cycle-by-cycle as the address LSB. MWEL-/MWE-is the only write control,and MOE- is the read output enable.

For 16-bit spaces constructed from 8-bit memories, the ISL3873A dynamically configures pin MUBE-/MA0/MWEHcycle-by-cycle as the high byte write enable, MWEL- as the low write enable signal, and MOE- as the read output enable.

For 16-bit spaces constructedfrom single-chip x16 memories (such as SRAMs), the ISL3873A dynamically configures pin MUBE_/MA0/MWEH- cycle-by-cycle as the upper byte enable. Pin MLBE- is connected as the low byte enable, MWEL-/MWE- is the write control, and MOE- is the read output enable.

Thesememoryimplementationsrequireno externallogic.The memory spaces may each be constructed from any type of memory desired. The only restriction is that a single memory space must be constructed from the same type of memory; for example,data space may notuse bothx8 and x16 memories, it must be all x8, or all x16. This restrictiondoes not apply across memory spaces; e.g., code space may use a x8 memory and data space a single x16 memory, or code space two x8 memories and data space a single x8 memory.

Serial EEPROM Interface

The ISL3873A contains a small on-chip ROM firmware which was added to allow the CIS or CIS plus firmware image to be transferred from an off-chip serial non-volatile memory device to RAM after a system reset. This allows a system configuration without a parallel Flash device. The operating frequency of the serial port is 400kHz with a voltage of 3.3V .Refer to Figure 8 for additional details on configuring the serial memory to the ISL3873A. The Power On Reset Configuration section in this document provides additional details on memory selection and control after a Reset condition.

PC Card Interface

PC Card Physical Interface

The Host interface is compatible to the PC Card 95 Standard (PCMCIA v2.1). The ISL3873A Host Interface pins connect directly to the correspondingly named pins on the PC Card connector with no external components (other than resistors) required. The ISL3873A operates as an I/O card using less than64 octetlocations. Readsand writesto internal registers and buffer memory are performed by I/O accesses. Attribute memory (256 octets) is provided for the CIS table which is located in external memory. Common memory is not used.

The following describesspecific features of various pins:

HA[9:0]

Decoding of the system address space is performed by the HCEx-. During I/O accesses HA[5:0] decode the register. HA[9:6] are ignored when the internal HAMASK register is

set to the defaults used by the standard firmware. During attribute memory accesses HA[9:1] are used.

HD[15:0]

The host interface is primarily designed for word accesses, although all byte access modes are fully supported. See HCE1-, HCE2- for a further description. Note that attribute memory is specified for and operates with even bytes accesses only.

HCE1-, HCE2-

The PC Card cycle type and widthare controlled with the CE signals. Word and Byte wide accesses are supported, using the combinationsof HCE1-, HCE2-, and HA0 as specified in the PC Card standard.

HWE-, HOE-

HOE- and HWE- are only used to access attribute memory. Common Memory,as specified in the PC Card standard, is not used in the ISL3873A. HOE- is the strobe that enables an attribute memory read cycle. HWE- is the corresponding strobe f or the attribute memory wr ite cycle. The attribute space contains the Card Information Structure (CIS) as well as the Function Configuration Registers (FCR).

HIORD-, HIOWR-

HIORD- and HIOWR- are the enabling strobes for register access cycles to the ISL3873A. These cycles can only be performed once the initializationprocedure is complete and the ISL3873A has been put into IO mode.

HREG-

This signal must be asserted for I/O or attribute cycles. A cycle where HREG- is not asserted will be ignored as the ISL3873A does not support common memory.

HINPACK-

Thissignal isasserted by the ISL3873Awhenever a validI/O read cycle takes place.A valid cycle is when HCE1-, HCE2-, HREG-, and HIORD- are asserted, once t he initialization procedure is complete.

HWAIT-

Waitstates are inserted in accesses using HWAIT-. The host interface synchronizes all PC Card cycles to the internal ISL3873A clock. The following wait states should be expected:

Direct Read or Write to Hardware Register

• 1/2 to 1 MCLK assertion of HWAIT- for internal synchronization.

Write to Memory Mapped Register, Buffer Access Path, or Attribute Space (Post-Write)

• The data required for the write cycle will be latched and therefore only the synchronizing wait state will occur.

• Until the queued cycle has actually written to the memory, any subsequent access by the Host will result in a WAIT.

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