intersil ISL34340 DATA SHEET

®
www.BDTIC.com/Intersil
Data Sheet June 23, 2008
WSVGA 24-Bit Long-Reach Video SERDES with Bidirectional Side-Channel
The ISL34340 is a serializer/deserializer of LVCMOS parallel video data. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer. It also transports auxiliary data bidirectionally over the same link during the video vertical retrace interval.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
ISL34340INZ* ISL34340INZ -40 to +85 64 Ld EPTQFP Q64.10x10B *Add “-T13” suffix for tape and reel. Please refer to TB347 for details on
reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
FN6255.1
Features
• 24-bit RGB transport over single differential pair
• Bidirectional auxiliary data transport without extra bandwidth and over the same differential pair
• 40MHz PCLK transports
- SVGA 800x600 @ 70fps, 16% blanking
- WSVGA 1024x600 @ 60fps, 8% blanking
• Internal 100Ω termination on high-speed serial lines
• DC balanced 8b/10b line code allows AC-coupling
- Provides immunity against ground shifts
• Transmitter amplitude boost and pre-emphasis and receiver equalization allow for longer cable lengths and higher data rates
• Same device for serializer and deserializer simplifies inventory
2
C interface
•I
• High-speed serial lines meet 8kV ESD rating
• Pb-free (RoHS compliant)
Applications
• Navigation and display systems
VIDEO
SOURCE
• Video entertainment systems
• Industrial computing terminals
• Remote cameras
3.3V 1.8V VDD_IO 3.3V 1.8V VDD_IO
VDD_TX
RGBA/B/C VSYNC
HSYNC DATAEN PCLK_IN
GND_CR
GND_AN
VDD_AN
GND_P
GND_TX
24 24
VDD_CR
VDD_CDR
RSTB/PDB
SERIOP
ISL34340 ISL34340
REF_RES
GND_CDR
GND_IO
3.16 KΩ
I2CA0
SERION
VIDEO_TX
VDD_IO
10m DIFFERENTIAL CABLE
27nF
27nF
27nF
27nF
REF_CLK
VDD_TX
SERIOP
SERION
PCLK_IN
GND_CR
GND_AN
VDD_P
VDD_IO
VDD_AN
GND_P
GND_TX
VDD_P
VDD_IO
GND_CDR
GND_IO
VDD_CR
VDD_CDR
RSTB/PDB
RGBA/B/C
VSYNC HSYNC
DATAEN
PCLK_OUT
VIDEO_TX
I2CA0
REF_RES
VDD_IO
3.16 KΩ
VIDEO
SINK
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
Pinout
www.BDTIC.com/Intersil
VDD_CDR
GND_IO
VDD_CDR
ISL34340
ISL34340
(64 LD EPTQFP)
TOP VIEW
SERIOP
GND_TX
VDD_TX
GND_CDR
GND_CDR
GND_TX
SERION
REF_RES
GND_AN
VDD_AN
TEST
I2CA1
I2CA0
Block Diagram
SCL SDA
VIDEO_TX
VDD_IO
PCLK_OUT
GND_IO
I2C
RGBA0 RGBA1 RGBA2 RGBA3 RGBA4 RGBA5 RGBA6 RGBA7 RGBB0 RGBB1 RGBB2 RGBB3
484746454443424140393837363534
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
123456789101112131415
RGBC5
RGBC4
RGBC3
RGBC2
RGBC1
RGBC0
RGBB7
RGBB6
RGBB5
RGBB4
VDD_IO
RGBC7
RGBC6
16
STATUS
TEST_EN
RSTB/PDB
33
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
I2CA2 I2CA3 SDA SCL VDD_P GND_P PCLK_IN VSYNCPOL HSYNCPOL VSYNC HSYNC DATAEN VDD_CR VDD_CR GND_CR GND_CR
VCM
GENERATOR
RAM
EMPHASIS
CDR
V/H/DE
RGB
24
VIDEO_TX
(HI)
PCLK_IN
(REF_CLK WHEN
VIDEO_TX IS LO)
PCLK_OUT
3
TDM
8b/10b
x30
÷30
MUX
DEMUX
2
PRE-
RX
TX
EQ
SERIOP
SERION
FN6255.1
June 23, 2008
ISL34340
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
Supply Voltage
VDD_P to GND_P, VDD_TX to GND_TX,
VDD_IO to GND_IO . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V
VDD_CDR to GND_CDR, VDD_CR to GND_CR . . -0 .5V to 2.5V Between any pair of GND_P, GND_TX,
GND_IO, GND_CDR, GND_CR . . . . . . . . . . . . . -0.1V to 0.1V
3.3V Tolerant LVTTL/LVCMOS Input Voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V
Differential Input Voltage . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V
Differential Output Current . . . . . . . . . . . . . .Short Circuit Protected
LVTTL/LVCMOS Outputs. . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating
Human Body Model
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4kV
SERIOP/N (all VDD Connected, all GND Connected) . . . . .8kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES:
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
1. θ
JA
Tech Brief TB379.
2. For θ
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Thermal Resistance (Typical, Notes 1, 2) θ
EPTQFP. . . . . . . . . . . . . . . . . . . . . . . . 33 4.5
Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θJC (°C/W)
JA
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR
VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY VOLTAGE
VDD_CDR, VDD_CR 1.7 1.8 1.9 V VDD_TX, VDD_P, VDD_AN, VDD_IO 3.0 3.3 3.6 V
SERIALIZER POWER SUPPLY CURRENTS
Analog TX Supply Current I Analog CDR Supply Current I Digital I/O Supply Current I Digital Supply Current I PLL/VCO Supply Current I Analog Bias Supply Current I Total 1.8V Supply Current 77 90 mA Total 3.3V Supply Current 40 46 mA
DESERIALIZER POWER SUPPLY CURRENTS
Analog TX Supply Current I Analog CDR Supply Current I Digital I/O Supply Current I Digital Supply Current I PLL/VCO Supply Current I Analog Bias Supply Current I Total 1.8V Supply Current 77 90 mA Total 3.3V Supply Current 64 80 mA
DDTX
DDCDR
DDIO
DDCR
DDP
DDAN
DDTX
DDCDR
DDIO
DDCR
DDP
DDAN
VIDEO_TX = 1 PCLK_IN = 40MHz
VIDEO_TX = 0 REF_CLK = 40MHz
= VDD_CR = 1.8V, VDD_IO = 3.3V
17 mA 57 mA
12mA 20 mA 17 mA
5.5 mA
24 mA 45 mA 17 25 mA 32 mA 17 mA
5.4 mA
,
3
FN6255.1
June 23, 2008
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