®
www.BDTIC.com/Intersil
ISL3232E, ISL4221E, ISL4223E
Data Sheet February 13, 2008
QFN Packaged, ±15kV ESD Protected,
+2.7V to +5.5V, 150nA, 250kbps, RS-232
Transmitters/Receivers
The Intersil ISL3232E and ISL4221E, ISL4223E devices are
2.7V to 5.5V powered RS-232 transmitters/receivers which
meet ElA/TIA-232 and V.28/V.24 specifications, even at
V
= 3.0V. Additionally, they pro vide ±15kV ESD protection
CC
(IEC61000-4-2 Air Gap and Human Body Model) on
transmitter outputs and receiver input s (RS-232 pins).
Targeted applications are PDAs, Palmtops, and hand-he ld
products where the low operational, and even lower st andby,
power consumption is critical. Efficient on-chip charge pumps,
coupled with manual and automatic power-down functions,
reduce the standby supply current to a 150nA trickle. Tiny
5mmx5mm Quad Flat No-Lead (QFN) packaging and the
use of small, low value capacitors ensure board space
savings as well. Data rates greater than 250kbps are
guaranteed at worst case load conditions.
The ISL4221E is a 1 driver, 1 receiver device and the
ISL3232E and ISL4223E are 2 driver, 2 receiver devices
that, coupled with the 5mmx5mm QFN package, provide the
industry’s smallest, lowest power serial port suitable for
PDAs, and hand-held applications. The 5mmx5mm QFN
requires 40% less board area than a 20 Ld TSSOP, and is
nearly 20% thinner.
The ISL4221E, ISL4223E versions feature an automatic
power-down function that powers down the on-chip power
supply and driver circuits. This occurs when an attached
peripheral device is shut off or the RS-232 cable is removed,
conserving system power automatically without changes to
the hardware or operating system. It powers up again when
a valid RS-232 voltage is applied to any receiver input.
Table 1 summarizes the features of the IC’s, while
Application Note AN9863 summarizes the features of each
device comprising the 3V RS-232 family.
FN6045.3
Features
• Available in Near Chip Scale QFN (5mmx5mm) Package,
which is 40% Smaller than a 20 Ld TSSOP
• ESD Protection for RS-232 I/O Pins to
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• RS-232 Compatible wi th VCC = 2.7V
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Manual and Automatic Power-down Features (Except
ISL3232E)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Wide Power Supply Range . . . . . . Single +2.7V to +5.5V
• Low Supply Current in Power-down State . . . . . . . .150nA
• Pb-Free Available (RoHS Compliant)
±15kV (IEC61000)
Applications
• Any Space Constrained System Requiring RS-232 Ports
- Battery Powered, and Portable Equipment
- Hand-Held Products (GPS Receivers, Bar Code
Scanners, etc.)
- PDAs and Palmtops, Data Cables
- Cellular/Mobile Phones, Digital Cameras
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
• Technical Brief TB379 “Thermal Characterization of
Packages for ICs”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
TABLE 1. SUMMARY OF FEATURES
NO. OF
PART NUMBER
ISL4221E 1 1 YES 250 YES YES YES
ISL3232E 2 2 YES 250 NO NO NO
ISL4223E 2 2 YES 250 YES YES YES
Tx.
NO. OF
Rx.
1
QFN PKG.
AVAILABLE?
DATA RATE
(kbps)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
Rx. ENABLE
FUNCTION?
All other trademarks mentioned are the property of their respective owners.
POWER-DOWN?
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2007, 2008. All Rights Reserved
MANUAL
AUTOMATIC POWER-DOWN
FUNCTION?
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
Ordering Information
PART
NUMBER
ISL3232EIRZ* (Note) ISL3232 EIRZ -40 to +85 16 Ld QFN (Pb-free) L16.5x5B
ISL4221EIR* ISL 4221EIR -40 to +85 16 Ld QFN L16.5x5B
ISL4221EIRZ* (Note) ISL4221 EIRZ -40 to +85 16 Ld QFN (Pb-free) L16.5x5B
ISL4223EIR* ISL 4223EIR -40 to +85 20 Ld QFN L20.5x5
ISL4223EIRZ* (Note) ISL4223 EIRZ -40 to +85 20 Ld QFN (Pb-free) L20.5x5
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
PART
MARKING
TEMP.
RANGE (°C) PACKAGE
PKG .
DWG. #
Pinouts
C1-
C2+
C2-
ISL3232E
(16 LD QFN)
TOP VIEW
V+
C1+
VCC
GND
15
16 14 13
T2IN
12
11
10
9
T1OUT
R1IN
R1OUT
T1IN
V+
C1-
C2+
C2-
1
2
3
4
1
2
3
4
V-
6578
R2IN
T2OUT
R2OUT
ISL4221E
(16 LD QFN)
TOP VIEW
C1+
EN
FORCEOFF
15
16 14 13
6578
V-
R1IN
R1OUT
VCC
INVALID
GND
12
11
T1OUT
FORCEON
10
T1IN
9
V+
C1-
C2+
C2-
C1+
20 19 18 17 16
1
2
3
4
V-
5
T2OUT
ISL4223E
(20 LD QFN)
TOP VIEW
EN
FORCEOFF
789106
R2IN
R2OUT
VCC
GND
T1OUT
15
R1IN
14
R1OUT
13
FORCEON
12
T1IN
11
T2IN
INVALID
2
FN6045.3
February 13, 2008
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
Pin Descriptions
PIN FUNCTION
VCC System power supply input (2.7V to 5.5V).
V+ Internally generated positive transmitter supply (+5.5V).
V- Internally generated negative transmitter supply (-5.5V).
GND Ground connection.
C1+ External capacitor (voltage doubler) is connected to this lead.
C1- External capacitor (voltage doubler) is connected to this lead.
C2+ External capacitor (voltage inverter) is connected to this lead.
C2- External capacitor (voltage inverter) is connected to this lead.
TIN TTL/CMOS compatible transmitter Inputs.
TOUT ±15kV ESD Protected
RIN ±15kV ESD Protected
ROUT TTL/CMOS level receiver outputs.
INVALID
FORCEOFF
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see T able 2).
FORCEON Active high input to override automatic power-down circuitry thereby keeping transmitters active. (FORCEOFF
EN
Active low receiver enable control.
, RS-232 level (nominally ±5.5V) transmitter outputs.
, RS-232 compatible receiver inputs.
must be high).
Typical Operating Circuits
TTL/CMOS
LOGIC LEVELS
+3.3V
0.1µF
0.1µF
R1
R2
C
C
T1
T2
OUT
OUT
ISL3232E
+
0.1µF
15
1
2
IN
IN
C1+
+
1
C1-
2
C2+
+
3
C2-
9
8
10
V
CC
R
R
2
GND
14
16
C
V+
V-
T
1
T
2
5kΩ
1
5kΩ
13
3
+
0.1µF
4
C
4
0.1µF
+
12
T1
OUT
5
T2
OUT
11
R1
67
R2
RS-232
LEVELS
IN
IN
3
FN6045.3
February 13, 2008
Typical Operating Circuits
www.BDTIC.com/Intersil
TTL/CMOS
ISL3232E, ISL4221E, ISL4223E
ISL4221E
+3.3V
LOGIC
LEVELS
C
0.1µF
C
0.1µF
R1
1
2
T1
OUT
IN
+
0.1µF
16
+
2
3
+
4
9
15
10
C1+
C1-
C2+
C2-
EN
FORCEON
13
V
CC
T
1
R
1
FORCEOFF
GND
12
INVALID
V+
V-
5kΩ
1
C
3
+
0.1µF
5
C
4
0.1µF
+
11
T1
OUT
67
R1
IN
14
V
CC
8
TO POWER
CONTROL LOGIC
RS-232
LEVELS
TTL/CMOS
LOGIC LEVELS
+3.3V
0.1µF
0.1µF
R1
R2
C
C
T1
T2
OUT
OUT
ISL4223E
+
0.1µF
20
+
+
2
3
4
11
10
13
19
12
C1+
C1-
C2+
C2-
EN
FORCEON
1
2
IN
IN
17
V
CC
T
1
T
2
R
1
R
2
FORCEOFF
GND
16
V+
V-
5kΩ
5kΩ
INVALID
1
C
3
+
0.1µF
5
C
4
0.1µF
+
15
T1
OUT
6
T2
OUT
14
R1
78
R2
18
V
CC
9
TO POWER
CONTROL LOGIC
RS-232
LEVELS
IN
IN
4
FN6045.3
February 13, 2008
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
, FORCEOFF, FORCEON, EN . . . . . . . . . . . . . . . -0.3V to 6V
T
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
R
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
T
OUT
, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
R
OUT
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
1. θ
JA
Tech Brief TB379, and Tech Brief TB389.
2. For θ
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Thermal Resistance (Typical)
16 Ld QFN Package (Notes 1, 2). . . . . 35 4.3
20 Ld QFN Package (Notes 1, 2). . . . . 32 4.3
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
(°C/W) θJC (°C/W)
JA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Electrical Specifications Test Conditions: V
Typicals are at T
PARAMETER TEST CONDITIONS
DC CHARACTERISTICS
Supply Current, Automatic Power-down All R
Supply Current, Power-down FORCEOFF
Supply Current,
Automatic Power-down Disabled
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low T
Input Logic Threshold High T
Input Leakage Current T
Output Leakage Current EN
Output Voltage Low I
Output Voltage High I
AUTOMATIC POWER-DOWN (FORCEON = GND, FORCEOFF
Receiver Input Thresholds to Enable
Transmitters
Receiver Input Thresholds to Disable
Transmitters
INVALID
INVALID
Receiver Threshold to T r ansmi tters
Enabled Delay (t
Receiver Positive or Negative Threshold
to INVALID
Receiver Positive or Negative Threshold
to INVALID
Output Voltage Low I
Output Voltage High I
)
WU
High Delay (t
Low Delay (t
INVH
INVL
)
)
IN
(Except ISL3232E)
All Outputs Unloaded,
FORCEON = FORCEOFF
, FORCEON, FORCEOFF, EN Full - - 0.8 V
IN
, FORCEON, FORCEOFF, EN VCC = 3.3V Full 2.0 - - V
IN
, FORCEON, FORCEOFF, EN Full - ±0.01 ±1.0 µA
IN
= VCC (Except ISL3232E) Full - ±0.05 ±10 µA
= 1.6mA Full - - 0.4 V
OUT
= -1.0mA Full V
OUT
ISL4221E, ISL4223E Powers Up (See Figure 6) Full -2.7 - 2.7 V
ISL4221E, ISL4223E Powers Down (See Figure 6) Full -0.3 - 0.3 V
= 1.6mA Full - - 0.4 V
OUT
= -1.0mA Full V
OUT
= 3V to 5.5V, C1 through C4 = 0.1µF; Unless Otherwise Specified.
CC
= +25°C
A
Open, FORCEON = GND, FORCEOFF = VCC
= GND (Except ISL3232E) 25 - 0.15 1 µA
VCC = 3.15V 25 - 0.3 1.0 mA
= V
CC
= 5.0V Full 2.4 - - V
V
CC
= VCC, Except ISL3232E)
TEMP
(°C)
25 - 0.15 1 µA
25 - 100 - µs
25 - 1 - µs
25 - 30 - µs
MIN
(Note 4) TYP
- 0.6 V
CC
- 0.6 - - V
CC
- 0.1 - V
CC
MAX
(Note 4) UNITS
5
FN6045.3
February 13, 2008
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
Electrical Specifications Test Conditions: V
Typicals are at T
PARAMETER TEST CONDITIONS
RECEIVER INPUTS
Input Voltage Range 25 -25 - 25 V
Input Threshold Low V
Input Threshold High V
Input Hysteresis 25 - 0.5 - V
Input Resistance 25 3 5 7 kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
Output Resistance V
Output Short-Circuit Current Full - ±35 ±60 mA
Output Leakage Current V
TIMING CHARACTERISTICS
Maximum Data Rate R
Receiver Propagation Delay Receiver Input to Receiver
Receiver Output Enable Time Normal Operation (Except ISL3232E) 25 - 200 - ns
Receiver Output Disable Time Normal Operation (Except ISL3232E) 25 - 200 - ns
Transmitter Skew t
Receiver Skew t
Transition Region Slew Rate V
ESD PERFORMANCE
RS-232 Pins (TOUT, RIN) Human Body Model 25 - ±15 - kV
All Other Pins Human Body Model 25 - ±2 - kV
NOTES:
3. Transmitter skew is measured at the transmitter zero crossing points.
4. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
= 3.3V 25 0.6 1.2 - V
CC
= 5.0V 25 0.8 1.5 - V
V
CC
= 3.3V 25 - 1.5 2.4 V
CC
= 5.0V 25 - 1.8 2.4 V
V
CC
= V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω
CC
= ±12V, VCC = 0V, or VCC = 3V to 5.5V,
OUT
with Automatic Power-down or FORCEOFF
= 3kΩ, CL = 1000pF, One Transmitter Switching Full 250 500 - kbps
L
Output, C
- t
PHL
- t
PHL
= 3.3V, RL = 3kΩ to 7kΩ,
CC
Measured From 3V to -3V
or -3V to 3V
IEC61000-4-2 Contact Discharge 25 - ±8 - kV
IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV
= 3V to 5.5V, C1 through C4 = 0.1µF; Unless Otherwise Specified.
CC
= +25°C (Continued)
A
TEMP
(°C)
Full - - ±25 µA
= GND
t
= 150pF
L
(Note 3) 25 - 100 - ns
PLH
PLH
PHL
t
PLH
= 150pF to
C
L
2500pF
C
= 150pF to
L
1000pF
25 - 0.15 - µs
25 - 0.15 - µs
25 - 50 - ns
25 4 - 30 V/µs
25 6 - 30 V/µs
MIN
(Note 4) TYP
MAX
(Note 4) UNITS
6
FN6045.3
February 13, 2008
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
Detailed Description
The ISL4221E, ISL4223E and ISL3232E operate from a
single +2.7V to +5.5V supply, guarantee a 250kbps minimum
data rate, require only four small external 0.1µF capaci tors,
feature low power consumption, and meet all ElA RS-232C
and V.28 specifications even with V
divided into three sections: The charge pump, the transmitters
and the receivers.
Charge-Pump
Intersil’s new RS-232 devices utilize regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a V
low as 3.0V . This allows them to maint ain R S-232 compliant
output levels over the ±10% tolerance range of 3.3V
powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inverter functions. The charge pumps
operate discontinuously (i.e., they turn off as soon as the V+
and V- supplies are pumped up to the no mi nal values),
resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting drivers
that translate TTL/CMOS inputs to EIA/TIA-232 output levels.
Coupled with the on-chip ±5.5V supplies, these transmitters
deliver true RS-232 levels over a wide range of single supply
system voltages.
All ISL4221E, ISL4223E transmitter outputs disable and
assume a high impedance state when the device enters the
power-down mode (see T able 2). These outputs may be driven
to ±12V when disabled.
= 3.0V. The circuit is
CC
supply as
CC
input high whenever the UART powers down. Figure 3 also
shows that the INV ALID
output can be used to determine
when the UART should be powered down. When the RS-232
cable is disconnected, INVALID
switches low indicating that
the UART is no longer needed. Reconnectin g the cable drives
INV ALID
back high, indicating that the UART should be
powered up.
V
CC
R
XIN
V
CC
5kΩ
V
OUT = VCC
SHDN
= GND
-25V ≤ V
FIGURE 1. INVERTING RECEIVER CONNECTIONS
POWERED
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
RIN
GND
V
CC
DOWN
UART
GND
PERIPHERAL
≤ +25V
Rx
Tx
R
XOUT
GND ≤ V
ROUT
V
CC
CURRENT
FLOW
OLD
RS-232 CHIP
≤ V
CC
The devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), V
≥ 3.0V, with one
CC
transmitter operating at full speed. Under more typical
conditions of V
≥ 3.3V, RL = 3kΩ, an d CL = 250pF, one
CC
transmitter easily operates at 900kbps.
Transmitter inputs float i f lef t unco nnected, and may ca use
I
increases. Connect unused inputs to GND for the best
CC
performance.
Receivers
All these RS-232 devices contain standard inverting receivers,
and the ISL4221E, ISL4223E receivers three-state via the EN
control line. All the receivers convert RS-232 signals to CMOS
output levels and accept inputs up to ±25V while presenting
the required 3kΩ to 7kΩ input impedance (see Figure 1) e ven
if the power is off (V
input stage uses hysteresis to increase noise immunity and
decrease errors due to slow input signal transitions.
Receivers driving a powered down UART must be disabled to
prevent current flow through, and possible damage to, the
UART’s protection diodes (see Figures 2 and 3). This can be
accomplished on the ISL4221E, ISL4223E by driving the EN
= 0V). The receivers’ Schmitt trigger
CC
V
CC
TRANSITION
DETECTOR
TO
WAKE-UP
LOGIC
V
CC
R
V
X
POWERED
DOWN
UART
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
T
OUT =
X
EN
R
= V
HI-Z
OUT
T
INVALID
IN
CC
ISL4221E, ISL4223E
R
T
IN
OUT
7
FN6045.3
February 13, 2008
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
TABLE 2. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE (EXCLUDING ISL3232E)
RS-232 SIGNAL
PRESENT AT
RECEIVER INPUT?
NO H H L Active Active L Normal Operation
NO H H H A ctive High-Z L
YES H L L Active Active H Normal Operation
YES H L H Active High-Z H
NO H L L High-Z Active L Power-down Due to Auto Power-down
NO H L H High-Z High-Z L
YES L X L High-Z Active H Manual Power-down
YES L X H High-Z High-Z H Manual Power-down w/Rcvr. Disabled
NO L X L High-Z Active L Manual Power-down
NO L X H High-Z High-Z L Manual Power-down w/Rcvr. Disabled
FORCEOFF
INPUT
FORCEON
INPUTENINPUT
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
INVALID
OUTPUT MODE OF OPERATION
(Auto Power-down Disabled)
(Auto Power-down Enabled)
Logic
Low Power Operation
These 3V devices require a nominal supply current of
0.3mA, even at V
= 5.5V, during normal operation (not in
CC
power-down mode). This is considerably less than the 5mA
to 11mA current required by comparable 5V RS-232 devices,
allowing users to reduce system power simply by switching to
this new family .
Power-down Functionality (Excluding
ISL3232E)
The already low current requirement drops significantly when
the device enters power-down mode. In power-down, supply
current drops to 150nA because the on-chip charge pump
turns off (V+ collapses to V
transmitter outputs three-state. Receiver outputs are
unaffected by power-down; refer to Table 2 for details. This
micro-power mode makes the ISL4221E, ISL4223E ideal for
battery-powered and portable applications.
Software Controlled (Manual) Power-down
The ISL4221E, ISL4223E family provides pins that allow the
user to force the IC into the low power , sta ndby st a te.
The ISL4221E, ISL4223E utilize a two pin approach where
the FORCEON and FORCEOFF
mode. For always enabled operation, FORCEON and
FORCEOFF
and power-down modes, under logic or software control, only
the FORCEOFF
isn’t critical, as FORCEOFF
Nevertheless, if strictly manual control over power-down is
desired, the user must strap FORCEON high to disable the
automatic power-down circu it ry.
are both strapped high. To switch between active
input need be driven. The FORCEON state
, V- collapses to GND) and the
CC
inputs determine the IC’s
dominates over FORCEON.
The time to recover from automatic power-down mod e is
typically 100µs.
FORCEOFF
PWR
MGT
LOGIC
CPU
FIGURE 4. CONNECTIONS FOR MANUAL POWER-DOWN
MANAGEMENT
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
POWER
UNIT
FORCEON
INVALID
ISL4221E, ISL4223E
I/O
UART
MASTER POWER-DOWN LINE
0.1µF
FORCEOFF
ISL4221E, ISL4223E
FORCEON
1MΩ
Connecting FORCEOFF
and FORCEON together disables
FIGURE 5. CIRCUIT TO PREVENT AUTO POWER-DOWN
the automatic power-down feature, enabling them to function
as a manual SHUTDOWN
input (see Figure 4).
8
FOR 100ms AFTER FORCED POWER-UP
February 13, 2008
FN6045.3
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
VALID RS-232 LEVEL - ISL4221E, ISL4223E IS ACTIVE
2.7V
INDETERMINATE - POWER-DOWN MAY OR
0.3V
INVALID LEVEL - POWER-DOWN OCCURS AFTER 30µs
-0.3V
INDETERMINATE - POWER-DOWN MAY OR
-2.7V
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
TRANSMITTER
INVALID
OUTPUT
VALID RS-232 LEVEL - ISL4221E, ISL4223E IS ACTIVE
RECEIVER
INPUTS
OUTPUTS
V
CC
0
V+
V
CC
0
V-
MAY NOT OCCUR
MAY NOT OCCUR
t
INVL
AUTOPWDN
t
INVH
INVALID
}
REGION
PWR UP
Some applications may need more time to wake up from
shutdown. If automatic power-down is being utilized, the
RS-232 device will re-enter power-down if valid receiver
levels aren’t reestablished within 30µs of the ISL4221E,
ISL4223E powering up. Figure 5 illustrates a circuit that
keeps the ISL4221E, ISL4223E from initiating automatic
power-down for 100ms after powering up. This gives the
slow-to-wake peripheral circuit time to re-establish valid
RS-232 output levels.
The time to recover from automatic power-down mode is
typically 100µs.
INV ALID Output (Excluding ISL3232E)
The INVALID output always indicates whether or not a valid
RS-232 signal (see Figure 6) is present at any of the
receiver inputs (see Table 2), giving the user an easy way to
determine when the interface block should power down.
Invalid receiver levels occur whenever the driving
peripheral’s outputs are shut off (powered down) or when the
RS-232 interface cable is disconnected. In the case of a
disconnected interface cable where all the receiver inputs
are floating (but pulled to GND by the internal receiver pull
down resistors), the INVALID
and drives the output low. The power management logic
then uses this indicator to power-down the interface block.
Reconnecting the cable restores valid levels at the receiver
inputs, INVALID
switches high, and the power management
logic wakes up the interface block. INVALID
used to indicate the DTR or RING INDICATOR signal, as
long as the other receiver inputs are floating, or driven to
GND (as in the case of a powered down driver).
logic detects the invalid levels
can also be
FIGURE 7. AUTOMA TIC POWER-DOWN AND INV ALID
TIMING DIAGRAMS
Automatic Power-down (Excluding ISL3232E)
Even greater power savings is available by using the
automatic power-down function. When no valid RS-232
voltages (see Figure 6) are sensed on any receiver input for
30µs, the charge pump and transmitters power-down,
thereby reducing supply current to 150nA. Invalid receiver
levels occur whenever the driving peripheral’s outputs are
shut off (powered down) or when the RS-232 interface cable
is disconnected. The ISL4221E, ISL4223E powers back up
whenever it detects a valid RS-232 voltage level on any
receiver input. This automatic power-down feature provides
additional system power savings without changes to the
existing operating system.
Automatic power-down operates when the FORCEON input is
low, and the FORCEOFF
disables automatic power-down, but manual power-down is
always available via the overriding FORCEOFF
summarizes the automatic power-down functionality.
input is high. Tying FORC EON high
input. Table 2
INV ALID
switches low after invalid levels have persiste d on all
of the receiver inputs for more than 30µs (see Figure 7).
INV ALID
RS-232 level on a receiver input. INVALID
switches back high 1µs after detectin g a val id
operates in all
modes (forced or automatic power-down, or forced on), so it is
also useful for systems employing manual power-down
circuitry . When automatic power-down is utilized, INVALID
= 0
indicates that the ISL4221E, ISL4223E is in power-down
mode.
Capacitor Selection
The charge pumps require 0.1µF, or greater, capacitors for
proper operation. Increasing the capacitor values (by a
factor of 2) reduces ripple on the transmitter outputs and
slightly reduces power consumption.
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-
.
9
FN6045.3
February 13, 2008
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple V
to ground with a
CC
capacitor of the same value as the charge-pump capacitor C
Connect the bypass capacitor as close as possible to the IC.
Transmitter Outputs when Exiting
Power-down
Figure 8 shows the response of two transmitter outputs
when exiting power-down mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF.
Note that the transmitters enable only when the magnitude
of the supplies exceed approximately 3V.
Operation Down to 2.7V
ISL4221E, ISL4223E and ISL3232E transmitter outputs
meet RS-562 levels (±3.7V), at the full data rate, with V
as low as 2.7V. RS-562 levels typically ensure inter
operability with RS-232 devices.
CC
V
CC
.
1
+
C
1
+
C
2
V
CC
+
0.1µF
C1+
C1-
ISL4221E, ISL4223E
C2+
C2-
T
IN
R
OUT
FORCEON
FORCEOFF
V
CC
T
OUT
5k
V+
V-
R
IN
+
C
3
C
4
+
1000pF
FIGURE 9. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV
T1
IN
High Data Rates
The ISL4221E, ISL4223E and ISL3232E maintain the RS232 ±5V minimum transmitter output voltages even at high
data rates. Figure 9 details a transmitter loopback test
circuit, and Figure 10 illustrates the loopback test result at
120kbps. For this test, all transmitters were simultaneously
driving RS-232 loads in parallel with 1000pF, at 120kbps.
Figure 11 shows the loopback results for a single transmitter
driving 1000pF and an RS-232 load at 250kbps. The static
transmitters were also loaded with an RS-232 receiver.
5V/DIV
2V/DIV
FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING
FORCEOFF
T1
T2
VCC = +3.3V
C1 - C4 = 0.1µF
TIME (20µs/DIV)
POWER-DOWN
T1
OUT
R1
OUT
5V/DIV
T1
T1
OUT
R1
OUT
VCC = +3.3V
C1 - C4 = 0.1µF
TIME (5µs/DIV)
FIGURE 10. LOOPBACK TEST AT 120kbps
IN
VCC = +3.3V
C1 - C4 = 0.1µF
TIME (2µs/DIV)
FIGURE 11. LOOPBACK TEST AT 250kbps
10
FN6045.3
February 13, 2008
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
Interconnection with 3V and 5V Logic
The ISL4221E, ISL4223E and ISL3232E directly interface
with 5V CMOS and TTL logic families. Nevertheless, with the
ISL4221E, ISL4223E and ISL3232E at 3.3V, and the logic
supply at 5V, AC, HC, and CD4000 outputs can properly
drive ISL4221E, ISL4223E and ISL3232E inputs, but
ISL4221E, ISL4223E and ISL3232E outputs do not reach
the minimum V
more information.
TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
3.3 3.3 Compatible with all CMOS
5 5 Compatible with all TTL and
5 3.3 Compatible with ACT and HCT
for these logic families. See Table 3 for
IH
SUPPLY VOLTAGES
V
CC
SUPPLY
VOLTAGE
(V) COMPATIBILITY
families.
CMOS logic families.
CMOS, and with TTL. ISL4221E,
ISL4223E and ISL3232E outputs
are incompatible with AC, HC,
and CD4000 CMOS inputs.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
IEC61000-4-2 Testing
The IEC61000-4-2 test method applies to finished
equipment, rather than to an individual IC. Therefore, the
pins most likely to suffer an ESD event are those that are
exposed to the outside world (the RS-232 pins in this case),
and the IC is tested in its typical application configuration
(power applied) rather than testing each pin-to-pin
combination. The lower current limiting resistor coupled with
the larger charge storage capacitor yields a test that is much
more severe than the HBM test. The extra ESD protection
built into this device’s RS-232 pins allows the design of
equipment meeting level 4 criteria without the need for
additional board level protection on the RS-232 port.
±15kV ESD Protection
All pins on ISL4221E, ISL4223E and ISL3232E devices
include ESD protection structures, but the RS-232 pins
(transmitter outputs and receiver inputs) incorporate
advanced structures, which allow them to survive ESD
events up to ±15kV. The RS-232 pins are particularly
vulnerable to ESD damage because they typically connect to
an exposed port on the exterior of the finished product.
Simply touching the port pins, or connecting a cable, can
cause an ESD event that might destroy unprotected ICs.
These new ESD structures protect the device whether or not
it is powered-up, protect without allowing any latchup
mechanism to activate, and don’t interfere with RS-232
signals as large as ±25V.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
11
FN6045.3
February 13, 2008
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
Typical Performance Curves V
6
4
2
1 TRANSMITTER AT 250kbps
OTHER TRANSMITTERS AT 30kbps
0
-2
-4
TRANSMITTER OUTPUT VOLTAGE (V)
-6
1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
= 3.3V, TA = +25°C
CC
V
OUT
V
OUT
FIGURE 12. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
45
ISL4221E
40
35
30
25
20
15
SUPPLY CURRENT (mA)
10
5
0
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
250kbps
120kbps
20kbps
FIGURE 14. SUPPL Y CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
3.5
3.0
2.5
2.0
1.5
1.0
SUPPLY CURRENT (mA)
0.5
NO LOAD
ALL OUTPUTS STATIC
25
+
20
15
-SLEW
SLEW RATE (V/µs)
-
10
5
0 1000 2000 3000 4000 5000
+SLEW
LOAD CAPACITANCE (pF)
FIGURE 13. SLEW RATE vs LOAD CAPACITANCE
45
ISL4223E/ISL3232E
40
35
30
25
20
15
SUPPLY CURRENT (mA)
10
5
0
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
250kbps
120kbps
20kbps
FIGURE 15. SUPPL Y CURRENT vs LOAD CAP ACIT ANCE
WHEN TRANSMITTING DATA
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ISL3232E: 296
ISL4221E: 286
ISL4223E: 357
PROCESS:
Si Gate CMOS
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE
12
FN6045.3
February 13, 2008
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.28 0.33 0.40 5, 8
D 5.00 BSC -
D1 4.75 BSC 9
D2 2.95 3.10 3.25 7, 8
E 5.00 BSC -
E1 4.75 BSC 9
E2 2.95 3.10 3.25 7, 8
e 0.80 BSC -
k0.25---
L 0.35 0.60 0.75 8
L1 - - 0.15 10
N162
Nd 4 3
Ne 4 3
P--0.609
θ --129
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to a ssist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
NOTESMIN NOMINAL MAX
Rev. 1 10/02
13
FN6045.3
February 13, 2008
ISL3232E, ISL4221E, ISL4223E
www.BDTIC.com/Intersil
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L20.5x5
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
A 0.80 0.90 1.00 -
A1 - 0.02 0.05 -
A2 - 0.65 1.00 9
A3 0.20 REF 9
b 0.23 0.30 0.38 5, 8
D 5.00 BSC -
D1 4.75 BSC 9
D2 2.95 3.10 3.25 7, 8
E 5.00 BSC -
E1 4.75 BSC 9
E2 2.95 3.10 3.25 7, 8
e 0.65 BSC -
k0.20 - - -
L 0.35 0.60 0.75 8
N202
Nd 5 3
Ne 5 3
P- -0.609
θ --129
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to a ssist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VHHC Issue I except for the "b"
dimension.
NOTESMIN NOMINAL MAX
Rev. 4 11/04
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6045.3
February 13, 2008
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