®
ISL28276, ISL28476
Data Sheet April 20, 2007
Dual and Quad Precision Micropower
Single Supply Rail-to-Rail Input and
Output Precision Op Amps
The ISL28276 and ISL28476 are Dual and Quad channel
micropower precision operational amplifier optimized for
single supply operation at 5V and can operate down to 2.4V.
For equivalent performance in a single channel op-amp
reference EL8176.
The ISL28276 and ISL28476 feature an Input Range
Enhancement Circuit (IREC) which enables both parts to
maintain CMRR performance for input voltages equal to the
positive and negative supply rails. The input signal is
capable of swinging 0.5V above a 5.0V supply (0.25V for a
2.4V supply) and to within 10mV from ground. The output
operation is rail to rail.
The both parts draw minimal supply current while meeting
excellent DC-accuracy, AC-performance, noise and output
drive specifications. Offset current, voltage and current
noise, slew rate, and gain-bandwidth product are all two to
ten times better than other micropower op-amps with
equivalent supply current ratings.
The ISL28276 and ISL28476 can be operated from one
lithium cell or two Ni-Cd batteries. The input range includes
both positive and negative rail.
Ordering Information
FN6301.1
Features
• 60µA supply current per channel
• 100µV max offset voltage
• 500pA input bias current
• 400kHz gain-bandwidth product
• 115dB PSRR and CMRR
• Single supply operation down to 2.4V
• Input is capable of swinging above V+ and within 10mV of
Ground
• Rail-to-rail output
• Output sources 31mA load current
• Pb-free plus anneal available (RoHS compliant)
Applications
• Battery- or solar-powered systems
• 4mA to 25mA current loops
• Handheld consumer products
• Medical devices
• Thermocouple amplifiers
• Photodiode pre-amps
• pH probe amplifiers
PART NUMBER
(Note)
ISL28276IAZ 28276 IAZ 97/Tube 16 Ld QSOP MDP0040
ISL28276IAZ-T7 28276 IAZ 7”
Coming Soon
ISL28476FAZ
Coming Soon
ISL28476FAZ-T7
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
PART
MARKING
28476 FAZ 97/Tube 16 Ld QSOP MDP0040
28476 FAZ 7”
TAPE &
REEL
(1k pcs)
(1k pcs)
1
PACKAGE
(Pb-Free)
16 Ld QSOP MDP0040
16 Ld QSOP MDP0040
PKG.
DWG. #
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Pinouts
ISL28276
(16 LD QSOP)
TOP VIEW
ISL28276, ISL28476
ISL28476
(16 LD QSOP)
TOP VIEW
NC
1
NC
2
OUT_A
3
IN-_A
4
IN+_A IN+_B
5
EN
_A
6
V-
7
NC NC
8 9
+
-
+
NC
16
V+
15
OUT_B
14
IN-_B
13
12
EN_B
11
NC
10
OUT_A
1
IN-_A
2
IN+_A
3
V+
4
IN+_B IN+_C
5
IN-_B
OUT_B
NC NC
-
6
7
8 9
+
-
+
-
+
+
OUT_D
16
IN-_D
15
IN+_D
14
V-
13
12
IN-_C
11
OUT_C
10
2
FN6301.1
April 20, 2007
ISL28276, ISL28476
Absolute Maximum Ratings (T
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V, 1V/μs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V
ESD tolerance, Human Body Model . . . . . . . . . . . . . . . . . . . . . .3kV
ESD tolerance, Machine Model . . . . . . . . . . . . . . . . . . . . . . . . .300V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = T
Operating Junction
Electrical Specifications V
= +25°C) Thermal Information
A
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite
Ambient Operating Temperature Range . . . . . . . . .- 40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
- 0.5V to V+ + 0.5V
-
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
A
= 5V, 0V, VCM = 0.1V, VO = 1.4V, TA = +25°C unless otherwise specified.
+
Boldface limits apply over the operating temperature range, -40°C to +125°C
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
V
OS
ΔV
OS
------------------
ΔTi me
ΔV
OS
--------------- -
ΔT
I
OS
Input Offset Voltage -100
-150
20 100
150
µV
Long Term Input Offset Voltage Stability 1.2 µV/Mo
Input Offset Drift vs Temperature 0.3 µV/°C
Input Offset Current 0.25 1.3
nA
2.0
I
B
e
N
Input Bias Current -2
-2.5
0.5 2
2.5
Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 1 µV
nA
P-P
Input Noise Voltage Density fO = 1kHz 25 nV/√Hz
i
N
Input Noise Current Density fO = 1kHz 0.1 pA/√Hz
CMIR Input Voltage Range Guaranteed by CMRR test 05V
CMRR Common-Mode Rejection Ratio V
PSRR Power Supply Rejection Ratio V
= 0V to 5V 90
CM
= 2.4V to 5V 90
+
80
115 dB
115 dB
80
A
V
VOL
OUT
Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ 350
350
V
= 0.5V to 4.5V, RL = 1kΩ 25 V/mV
O
Maximum Output Voltage Swing Output low, RL = 100kΩ 3630mV
550 V/mV
Output low, R
= 1kΩ 130 175
L
mV
225
Output high, R
= 100kΩ 4.990
L
4.996 V
4.97
Output high, R
SR+ Positive Slew Rate 0.13
SR- Negative Slew Rate 0.10
= 1kΩ 4.800
L
4.750
0.10
0.09
4.880 V
0.17 0.20
V/µs
0.25
0.13 0.17
V/µs
0.19
GBW Gain Bandwidth Product 400 kHz
3
FN6301.1
April 20, 2007
ISL28276, ISL28476
Electrical Specifications V
= 5V, 0V, VCM = 0.1V, VO = 1.4V, TA = +25°C unless otherwise specified.
+
Boldface limits apply over the operating temperature range, -40°C to +125°C (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
I
S,ON
I
S,OFF
I
S,ON
I
S,OFF
I
+ Short Circuit Sourcing Capability RL = 10Ω 29
SC
Supply Current, Enabled ISL28276 all channels enabled. 120 156
175
Supply Current, Disabled 479µA
Supply Current, Enabled ISL28476 all channels enabled. 240 312
350
Supply Current, Disabled 81418µA
31 mA
23
I
- Short Circuit Sinking Capability RL = 10Ω 24
SC
V
V
V
I
ENH
I
ENL
S
INH
INL
Minimum Supply Voltage 2.4 V
Enable Pin High Level 2 V
Enable Pin Low Level 0.8 V
Enable Pin Input Current VEN = 5V 0.7 1.3
Enable Pin Input Current VEN = 0V -0.1 0 +0.1 µA
19
26 mA
1.5
µA
µA
µA
Typical Performance Curves
8
4
0
GAIN (dB)
AV = 1
R
= 10kΩ
-4
L
= 2.7pF
C
L
= 100Ω
R
F
= OPEN
R
G
-8
100 10k 100k 10M
1k 1M
VS = ±1.25V
VS = ±2.5V
FREQUENCY (Hz)
VS = ±1.0V
FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
45
40
35
30
25
20
AV = 100
GAIN (dB)
15
R
= 10kΩ
L
= 2.7pF
C
L
10
5
0
100 10k 100k 1M
R
F/RG
R
F
R
G
= 99.02
= 221kΩ
= 2.23kΩ
VS = ±1.25V
1k
FREQUENCY (Hz)
VS = ±2.5V
VS = ±1.0V
4
FN6301.1
April 20, 2007
ISL28276, ISL28476
Typical Performance Curves (Continued)
200
V
= VDD/2
CM
= -1
A
150
V
100
50
V
= 5V
DD
0
V
-50
-100
-150
INPUT OFFSET VOLTAGE (µV)
-200
05
= 2.5V
DD
1324
OUTPUT VOLTAGE (V)
0
-20
-40
-60
-80
INPUT OFFSET VOLTAGE (µV)
-100
VOS, µV
05
1324
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 3. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE FIGURE 4. INPUT OFFSET VOLTAGE vs COMMON-MODE
INPUT VOLTAGE
120
80
40
GAIN (dB)
0
-40
-80
11k100k10M
10
FREQUENCY (Hz)
FIGURE 5. A
vs FREQUENCY @ 100kΩ LOAD
VOL
10k 1M100
80
40
0
-40
-80
-120
100
80
60
PHASE (°)
40
GAIN (dB)
20
0
-20
10 10k 1M
100
FREQUENCY (Hz)
FIGURE 6. A
VOL
PHASE
GAIN
100k1k
vs FREQUENCY @ 1kΩ LOAD
200
150
100
50
0
-50
-100
-150
PHASE (°)
120
110
100
90
80
70
60
50
PSRR (dB)
40
30
20
10
0
PSRR -
VS = 5VDC
V
RL = 100k
AV = +1
10 10k 1M
SOURCE
100 100k1k
= 1V
P-P
Ω
FREQUENCY (Hz)
PSRR +
FIGURE 7. PSRR vs FREQUENCY
5
90
80
70
60
CMRR (dB)
50
40
30
10 10k 1M
100 100k1k
FREQUENCY (Hz)
VS = 5VDC
V
SOURCE
RL = 100k
AV = +1
FIGURE 8. CMRR vs FREQUENCY
= 1V
Ω
P-P
FN6301.1
April 20, 2007
ISL28276, ISL28476
Typical Performance Curves (Continued)
2.56
V
2.54
2.52
2.50
2.48
2.46
2.44
2.42
FIGURE 9. SMALL SIGNAL TRANSIENT RESPONSE
IN
V
OUT
= 5VDC
V
S
V
= 0.1V
OUT
P-P
RL = 500Ω
A
= +1
V
0 2 4 6 8 101214161820
V
IN
= 5VDC
V
S
V
= 0.1V
OUT
P-P
RL = 500Ω
= -2
A
V
V
OUT
0 100 200 300 400 500
FIGURE 10. LARGE SIGNAL TRANSIENT RESPONSE
10.00
1.00
0.10
CURRENT NOISE (pA/√Hz)
0.01
1 10 100 1k 10k
FREQUENCY (Hz)
FIGURE 11. CURRENT NOISE vs FREQUENCY
100k
1k
100
10
VOLTAGE NOISE (nV/√Hz)
1
10 100 1k 10k 100k
FREQUENCY (Hz)
FIGURE 12. VOLTAGE NOISE vs FREQUENCY
VOLTS (V)
6
V
IN
5
4
3
2
100K
100K
100K
VS +
VS +
100K
100K
100K
-
-
-
DUT
DUT
DUT
+
+
+
1K
1K
1K
VS -
VS -
Function
Function
Function
Generator
Generator
Generator
33140A
33140A
33140A
V+ = 5V
V
OUT
VOLTAGE NOISE (200nV/DIV)
1µV
P-P
TIME (1s/DIV)
FIGURE 13. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
6
1
0
0 50 100 150 200
TIME (ms)
FIGURE 14. INPUT VOLTAGE SWING ABOVE THE V+ SUPPLY
FN6301.1
April 20, 2007
ISL28276, ISL28476
Typical Performance Curves (Continued)
10k
1k
100
10
INPUT BIAS, OFFSET CURRENTS (pA)
1
IB+
I
OS
05
1324
COMMON-MODE INPUT VOLTAGE (V)
IB-
FIGURE 15. INPUT BIAS + OFFSET CURRENTS vs
COMMON-MODE INPUT VOLTAGE
120
n = 7
110
100
90
CURRENT (µA)
80
155
135
115
95
75
SUPPLY CURRENT (µA)
55
35
2.0 3.5 4.0 5.5
2.5 5.04.53.0
SUPPLY VOLTAGE (V)
FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE
150
n = 6
140
130
120
110
CURRENT (µA)
100
70
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 17. SUPPLY CURRENT vs TEMPERA TURE V
ENABLED. R
1200
n = 7
1000
800
600
400
CURRENT (pA)
200
0
-40 -20 0 20 40 60 80 100 120
FIGURE 19. I
BIAS
= INF
L
TEMPERATURE (°C)
+ vs TEMPERATURE VS = ±2.5V FIGURE 20. I
= ±1.2V
S
90
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 18. SUPPLY CURRENT vs TEMPERA TURE V
ENABLED. R
1400
n = 7
1200
1000
800
600
CURRENT (pA)
400
200
0
-40 -20 0 20 40 60 80 100 120
BIAS
= INF
L
TEMPERATURE (°C)
+ vs TEMPERATURE VS = ±1.2V
= ±2.5V
S
7
FN6301.1
April 20, 2007
ISL28276, ISL28476
Typical Performance Curves (Continued)
1400
n = 7
1200
1000
800
600
CURRENT (pA)
400
200
0
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 21. I
1200
n = 7
1000
800
600
400
CURRENT (pA)
200
vs TEMPERATURE VS = ±2.5V
BIAS-
1700
n = 7
1500
1300
1100
900
CURRENT (pA)
700
500
300
-40-200 20406080100120
TEMPERATURE (°C)
FIGURE 22. I
1300
n = 7
1100
900
700
500
CURRENT (pA)
300
100
vs TEMPERATURE VS = ±1.2V
BIAS-
0
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 23. INPUT OFFSET CURRENT vs TEMPERATURE
= ±2.5V
V
S
200
n = 5
150
100
50
(µV)
OS
0
V
-50
-100
-150
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 25. INPUT OFFSET VOLT AGE vs TEMPERA TURE
V
= ±2.5V
S
-100
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 24. INPUT OFFSET CURRENT vs TEMPERATURE
V
= ±1.2V
S
200
n = 6
150
100
50
(µV)
0
OS
V
-50
-100
-150
-200
-40-200 20406080100120
TEMPERATURE (°C)
FIGURE 26. INPUT OFFSET VOLTAGE vs TEMPERATURE
V
= ±1.2V
S
8
FN6301.1
April 20, 2007
OU
ISL28276, ISL28476
Typical Performance Curves (Continued)
130
n = 7
120
110
CMRR (dB)
100
90
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 27. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V
2.40
2.39
2.38
(V)
2.37
OUT
V
2.36
2.35
2.34
FIGURE 29. POSITIVE V
n = 5
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
vs TEMPERA TURE RL = 1k
V
S
OUT
= ±2.5V
114
n = 6
112
110
108
PSRR (dB)
106
104
102
-40-200 20406080100120
TEMPERATURE (°C)
FIGURE 28. PSRR vs TEMPERATURE V
-2.32
n = 5
-2.33
-2.34
-2.35
(V)
-2.36
OUT
V
-2.37
-2.38
-2.39
-2.4
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 30. NEGATIVE V
V
= ±2.5V
S
vs TEMPERATURE RL = 1k
OUT
= ±1.2V TO ±2.5V
S
2.4992
2.499
2.4988
2.4986
2.4984
(V)
2.4982
OUT
V
2.498
2.4978
2.4976
2.4974
n = 7
-40 -20 0 20 40 60 80 100 120
FIGURE 31. POSITIVE V
V
= ±2.5V
S
TEMPERATURE (°C)
vs TEMPERA TURE RL = 100k
OUT
9
-2.4956
-2.4958
-2.496
-2.4962
(V)
-2.4964
OUT
V
-2.4966
-2.4968
-2.497
-2.4972
n = 7
-40 -20 0 20 40 60 80 100 120
FIGURE 32. NEGATIVE V
V
= ±2.5V
S
TEMPERATURE (°C)
vs TEMPERATURE RL = 100k
OUT
FN6301.1
April 20, 2007
ISL28276, ISL28476
Typical Performance Curves (Continued)
14
n = 7
12
10
8
6
(nA)
4
IL
I
2
0
-2
-4
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
0.9
n = 5
0.8
0.7
(µA)
IH
I
0.6
0.5
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 33. IIL (EN) vs TEMPERATURE VS = ±2.5V FIGURE 34. IIH (EN) vs TEMPERATURE VS = ±2.5V
0.18
n = 5
0.16
0.14
0.12
SLEW RATE (V/µs)
0.1
0.16
n = 7
0.15
0.14
0.13
0.12
SLEW RATE (V/µs)
0.11
0.08
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 35. + SLEW RA TE vs TEMPERATURE V
INPUT = ±0.75V A
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.2
893mW
1
0.8
0.6
0.4
POWER DISSIPATION (W)
0.2
0
0 255075100 150
θ
J
A
=
AMBIENT TEMPERATURE (°C)
= 2
V
Q
S
O
P
1
6
1
1
2
°
C
/
W
S
12585
= ±2.5V
FIGURE 37. PACKAGE POWER DISSIPA TION vs AMBIENT
TEMPERATURE
0.1
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 36. - SLEW RATE vs TEMPERATURE V
INPUT = ±0.75V A
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1
0.8
633mW
0.6
θ
J
A
0.4
POWER DISSIPATION (W)
0.2
0
0 25 50 75 100 150
=
AMBIENT TEMPERATURE (°C)
= 2
V
Q
S
O
P
1
6
1
5
8
°
C
/
W
S
12585
= ±2.5V
FIGURE 38. PACKAGE POWER DISSIPA TION vs AMBIENT
TEMPERATURE
10
FN6301.1
April 20, 2007
Pin Descriptions
ISL28276, ISL28476
ISL28276
(16 LD QSOP)
3 1 OUT_A Circuit 3 Amplifier A output
4 2 IN-_A Circuit 1 Amplifier A inverting input
5 3 IN+_A Circuit 1 Amplifier A non-inverting input
15 4 V+ Circuit 4 Positive power supply
12 5 IN+_B Circuit 1 Amplifier B non-inverting input
13 6 IN-_B Circuit 1 Amplifier B inverting input
14 7 OUT_B Circuit 3 Amplifier B output
1, 2, 8, 9, 10, 16 8, 9 NC No internal connection
7 13 V- Circuit 4 Negative power supply
6EN
11 EN
ISL28476
(16 LD QSOP) PIN NAME
10 OUT_C Circuit 3 Amplifier C output
11 IN-_C Circuit 1 Amplifier C inverting input
12 IN+_C Circuit 1 Amplifier B non-inverting input
14 IN+_D Circuit 1 Amplifier D non-inverting input
15 IN-_D Circuit 1 Amplifier D inverting input
16 OUT_D Circuit 3 Amplifier D output
EQUIVALENT
CIRCUIT DESCRIPTION
_A Circuit 2 Amplifier A enable pin internal pull-down; Logic “1” selects the disabled state;
Logic “0” selects the enabled state.
_B Circuit 2 Amplifier B enable pin with internal pull-down; Logic “1” selects the disabled
state; Logic “0” selects the enabled state.
V+
IN-
IN+
V-
CIRCUIT 1
LOGIC
PIN
CIRCUIT 2
Applications Information
Introduction
The ISL28276 and ISL28476 are Dual and Quad channel
CMOS rail-to-rail input, output (RRIO) micropower precision
operational amplifier with an enable feature. The parts are
designed to operate from single supply (2.4V to 5.0V) or dual
supply (±1.2V to ±2.5V) while drawing only 120μA of supply
current. The device has an input common mode range that
extends 10% above the positive rail and up to 100mV below
the negative supply rail. The output operation can swing
within about 4mV of the supply rails with a 100kΩ load
(reference Figures 29 through 32). This combination of low
power and precision performance makes them suitable for
solar and battery power applications.
Rail-to-Rail Input
The input common-mode voltage range of the ISL28276 and
ISL28476 is from the negative supply to 10% greater than
V+
V-
V+
OUT
V-
CIRCUIT 3
V+
V-
CIRCUIT 4
CAPACITIVELY
COUPLED
ESD CLAMP
the positive supply without introducing additional offset
errors or degrading performance associated with a
conventional rail-to-rail input operational amplifier. Many
rail-to-rail input stages use two differential input pairs, a longtail PNP (or PFET) and an NPN (or NFET). Severe penalties
have to be paid for this circuit topology. As the input signal
moves from one supply rail to another, the operational
amplifier switches from one input pair to the other causing
drastic changes in input offset voltage and an undesired
change in magnitude and polarity of input offset current.
The ISL28276 and ISL28476 achieve input rail-to-rail
operation without sacrificing important precision
specifications and degrading distortion performance. The
devices’ input offset voltage exhibits a smooth behavior
throughout the entire common-mode input range. The input
bias current versus the common-mode voltage range gives
us an undistorted behavior from typically 100mV below the
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FN6301.1
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ISL28276, ISL28476
negative rail and 10% higher than the V+ rail (0.5V higher
than V+ when V+ equals 5V).
Input Protection
All input terminals have internal ESD protection diodes to
both positive and negative supply rails, limiting the input
voltage to within one diode beyond the supply rails. They
have additional back-to-back diodes across the input
terminals. For applications where the input differential
voltage is expected to exceed 0.5V , external series resistors
must be used to ensure the input currents never exceed
5mA.
Input Bias Current Compensation
The input bias currents are decimated down to a typical of
500pA while maintaining an excellent bandwidth for a micropower operational amplifier. Inside the ISL28276 and
ISL28476 is an input bias canceling circuit. The input stage
transistors are still biased with an adequate current for
speed but the canceling circuit sinks most of the base
current, leaving a small fraction as input bias current.
Rail-to-Rail Output
A pair of complementary MOSFET devices are used to
achieve the rail-to-rail output swing. The NMOS sinks
current to swing the output in the negative direction. The
PMOS sources current to swing the output in the positive
direction. The output with a 100kΩ load will swing to within
3mV of the supply rails.
Enable/Disable Feature
The ISL28276 offers an EN pin that disables the device
when pulled up to at least 2.2V. In the disabled state (output
in a high impedance state), the part consumes typically 4µA.
By disabling the part, multiple ISL28276 parts can be
connected together as a MUX. The outputs are tied together
in parallel and a channel can be selected by the EN
EN
pin also has an internal pull down. If left open, the EN pin
will pull to the negative rail and the device will be enabled by
default.
pin. The
components can be mounted to the PC board using PTFE
standoff insulators.
HIGH IMPEDANCE INPUT
IN
FIGURE 39. GUARD RING EXAMPLE FOR UNITY GAIN
AMPLIFIER
V+
Example Application
Thermocouples are the most popular temperature-sensing
device because of their low cost, interchangeability, and
ability to measure a wide range of temperatures. The
ISL28276 (Figure 40) is used to convert the differential
thermocouple voltage into single-ended signal with 10X gain.
The ISL28276's rail-to-rail input characteristic allows the
thermocouple to be biased at ground and the converter to
run from a single 5V supply.
R
4
100kΩ
10kΩR
K TYPE
THERMOCOUPLE
FIGURE 40. THERMOCOUPLE AMPLIFIER
3
10kΩR
2
V+
+
ISL28276
V-
R
1
100kΩ
+
410µV/°C
5V
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input
impedance and low offset voltage, care should be taken in
the circuit board layout. The PC board surface must remain
clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
will reduce surface moisture and provide a humidity barrier,
reducing parasitic resistance on the board. When input
leakage current is a concern, the use of guard rings around
the amplifier inputs will further reduce leakage currents.
Figure 39 shows a guard ring example for a unity gain
amplifier that uses the low impedance amplifier output at the
same voltage as the high impedance input to eliminate
surface leakage. The guard ring does not need to be a
specific width, but it should form a continuous loop around
both inputs. For further reduction of leakage currents,
12
FN6301.1
April 20, 2007
ISL28276, ISL28476
Quarter Size Outline Plastic Packages Family (QSOP)
E E1
0.010 C A B
C
SEATING
PLANE
0.004 C
A
N
1
B
L1
c
SEE DETAI L "X"
D
PIN #1
I.D. MARK
e
0.007 C A B
(N/2)+1
A
(N/2)
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
INCHES
SYMBOL
A 0.068 0.068 0.068 Max. A1 0.006 0.006 0.006 ±0.002 A2 0.056 0.056 0.056 ±0.004 -
b 0.010 0.010 0.010 ±0.002 -
c 0.008 0.008 0.008 ±0.001 D 0.193 0.341 0.390 ±0.004 1, 3
E 0.236 0.236 0.236 ±0.008 -
H
E1 0.154 0.154 0.154 ±0.004 2, 3
e 0.025 0.025 0.025 Basic -
L 0.025 0.025 0.025 ±0.009 -
b
L1 0.041 0.041 0.041 Basic -
N 16 24 28 Reference -
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
TOLERANCE NOTESQSOP16 QSOP24 QSOP28
Rev. F 2/07
GAUGE
PLANE
L
0.010
4°±4°
A2
A1
DETAIL X
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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13
FN6301.1
April 20, 2007
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