intersil ISL28270, ISL28273, ISL28470 DATA SHEET

ISL28270, ISL28273, ISL28470

Data Sheet April 13, 2007

Micropower, Single Supply, Rail-to-Rail Input and Output (RRIO) Instrumentation Amplifier

The ISL28270 and ISL28273 are dual channel micropower instrumentation amplifiers (in-amps) and the ISL28470 is a Quad-channel in-amp optimized for low 2.4V to 5V single supplies.

All three devices feature an Input Range Enhancement Circuit (IREC) which maintains CMRR performance for input voltages equal to the positive supply and down to 50mV above the negative supply rail. The input signal is capable of swinging above the positive supply rail and to 10mV above the negative supply with only a slight degradation of the CMRR performance. The output operation is rail to rail.

The ISL28273 is compensated for a minimum gain of 10 or more. For higher gain applications, the ISL28270 and ISL28470 are compensated for a minimum gain of 100. The in-amps have bipolar input devices for best offset and excellent 1/f noise performance. The amplifiers can be operated from one lithium cell or two Ni-Cd batteries.

FN6260.2

Features

• 60µA supply current per channel ISL28270

• 150µV max offset voltage

• 2nA max input bias current ISL28270

• 110dB CMRR, PSRR

• 0.7µV/°C offset voltage temperature coefficient

• 240kHz -3dB bandwidth (G = 100) ISL28270, ISL28470

• 230kHz -3dB bandwidth (G = 10) ISL28273

• 0.5V/µs slew rate

• Single supply operation

• Rail-to-rail input and output (RRIO)

• Input is capable of swinging above V+ and below V(ground sensing)

• Output sources and sinks ±29mA load current

• 0.5% gain error

• Pb-free plus anneal available (RoHS compliant)

Ordering Information

PART NUMBER

(Note)

ISL28270IAZ (Note)

ISL28270IAZ-T13 (Note)

Coming Soon ISL28273FAZ (Note)

Coming Soon ISL28273FAZ-T7 (Note)

ISL28470FAZ (Note)

ISL28470FAZ-T7 (Note)

ISL28270INEVAL1Z (Note)

ISL28273INEVAL1Z Evaluation Platform

Coming Soon

ISL28470EVAL1Z

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

28270 IAZ 97/Tube 16 Ld QSOP

28270 IAZ 13”

28273 FAZ 97/Tube 16 Ld QSOP

28273 FAZ 7”

ISL28470FAZ 48/Tube 28 Ld QSOP

ISL28470FAZ 7”

Evaluation Platform

TAPE &

REEL

(1k pcs)

PACKAGE

(Pb-Free)

(Pb-free) 16 Ld QSOP

(Pb-free)

16 Ld QSOP (Pb-free)

(Pb-free) 28 Ld QSOP

(Pb-free)

PKG.

DWG. #

MDP0040

M28.15

Applications

• Battery or solar-powered systems

• Strain gauge

• Sensor signal conditioning

• Medical devices

• Industrial instrumentations

Related Literature

• AN1290, ISL2827xINEVAL1Z Evaluation Board User’s Guide

• AN1298, Instrumentation Amplifier Application Note

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Pinouts

OUT_A

FB+_A

FB-_A

IN-_A

IN+_A

ISL28270, ISL28273

(16 LD QSOP)

TOP VIEW

V-

ISL28270, ISL28273, ISL28470

ISL28470

(28 LD QSOP)

TOP VIEW

V+

OUT_B

FB+_B

FB-_B

IN-_B

IN+_B

OUT_A

FB+_A

FB-_A

IN-_A

IN+_A

IN+_B

IN-_B

FB-_B

FB+_B

OUT_B

V-

-+ -+

OUT_D

FB+_D

FB-_D

IN-_D

IN+_D

V-

IN+_C

IN-_C

FB-_C

FB+_C

OUT_C

FN6260.2

April 13, 2007

ISL28270, ISL28273, ISL28470

Absolute Maximum Ratings (T

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V

Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/μs

Input Current (IN, FB) ISL28270, ISL28470 . . . . . . . . . . . . . . . 5mA

Differential Input Voltage (IN, FB) ISL28270, ISL28470 . . . . . . 0.5V

Input Current (IN, FB) ISL28273 . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Differential Input (IN, FB) Voltage ISL28273 . . . . . . . . . . . . . . . 1.0V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V-

ESD Tolerance

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV

= +25°C) Thermal Information

Thermal Resistance θ

16 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . . 112

28 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . . 79

Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite

Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

- 0.5V to V+ + 0.5V

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . .+125°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

(°C/W)

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = T

Electrical Specifications V

= +5V, VM = GND, V

operating temperature range, -40°C to +125°C.

= 1/2V+, TA = +25°C, unless otherwise specified. Boldface limits apply over the

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

Input Offset Voltage ISL28270, ISL28470 -150

-225

±35 150

225

µV

ISL28273 TBD µV

TCV

Input Offset Voltage Temperature Coefficient

Input Offset Current between IN+ and IN-, and between FB+ and FB-

Temperature = -40°C to +125°C 0.7 µV/°C

ISL28270 -1

-1.5

±0.25 1

1.5

ISL28470 -1.5

-2.0

±0.25 1.5

ISL28273 TBD nA

Input Bias Current (IN+, IN-, FB+, and FB- terminals)

ISL28270 -2.0

-2.5

ISL28470 -2.5

-3.0

±0.5 2.0

2.5

±0.5 2.5

3.0

ISL28273 TBD nA

Input Noise Voltage ISL28270, ISL28470 f = 0.1Hz to 10Hz 3.5 µV

ISL28273 3.5 µV

P-P P-P

Input Noise Voltage Density ISL28270, ISL28470 fo = 1kHz 60 nV/√Hz

ISL28273 210 nV/√Hz

Input Noise Current Density ISL28270, ISL28470 fo = 1kHz 0.48 pA/√Hz

ISL28273 0.65 pA/√Hz

Input Resistance ISL28270, ISL28470 3 MΩ

ISL28273 15 MΩ

Input Voltage Range V+ = 2.4V to 5.0V 0 V

FN6260.2

April 13, 2007

ISL28270, ISL28273, ISL28470

Electrical Specifications V

= +5V, VM = GND, V

operating temperature range, -40°C to +125°C. (Continued)

= 1/2V+, TA = +25°C, unless otherwise specified. Boldface limits apply over the

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

CMRR Common Mode Rejection Ratio ISL28270 VCM = 0.05V to 5V 90

110 dB

TBD

ISL28273 TBD dB ISL28470 90

110 dB

PSRR Power Supply Rejection Ratio ISL28270 V

= 2.4V to 5V 90

110 dB

TBD

ISL28273 TBD dB ISL28470 90

110 dB

Gain Error ISL28270, ISL28470 RL = 100kΩ to 2.5V +0.5 %

ISL28273 TBD %

OUT

Maximum Voltage Swing Output low, 100kΩ to 2.5V 4 10 mV

Output low, 1kΩ to 2.5V 130 250

300

Output high, 100kΩ to 2.5V 4.990 4.996 V Output high, 1kΩ to GND 4.75

4.88 V

4.70

SR Slew Rate R

= 1kΩ to GND 0.3

0.25

0.5 0.7

0.75

-3dB BW -3dB Bandwidth ISL28270, ISL28470 Gain = 100 240 kHz Gain = 200 84 kHz Gain = 500 30 kHz Gain = 1000 13 kHz

ISL28273 Gain = 10 265 kHz

Gain = 20 100 kHz Gain = 50 25 kHz Gain = 100 13 kHz

S,EN

S,DIS

ENH

ENL

ENH

ENL

Supply Current, Enabled ISL28270 - Both A and B channels enabled,

=V-

ISL28470 - A, B, C and D channels enabled, EN

= V-

Supply Current, Disabled ISL28270 - Both A and B channels disabled,

=V+

ISL28470 - A, B, C and D channels disabled,

= V+

120 156

195

260 335 µA

479µA

10 12

EN Pin for Shut-down 2 V EN Pin for Power-On 0.8 V EN Input Current High EN = V+ 0.8 1

1.3

EN Input Current Low EN = V- 26 50

100

Minimum Supply Voltage 2.4 V

V/µs

µA

FN6260.2

April 13, 2007

ISL28270, ISL28273, ISL28470

Electrical Specifications V

= +5V, VM = GND, V

operating temperature range, -40°C to +125°C. (Continued)

= 1/2V+, TA = +25°C, unless otherwise specified. Boldface limits apply over the

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

Short Circuit Output Current V+ = 5V, R

= 2.4V, R

= 10Ω ±20

LOAD

= 10Ω ±8 mA

LOAD

±18

±29 mA

Typical Performance Curves

GAIN (dB)

GAIN = 2,000V/V GAIN = 1,000V/V

GAIN = 500V/V

GAIN = 200V/V GAIN = 100V/V

1 10 100 1k 10k 100k 1M

COMMON-MODE INPUT = VS+

GAIN = 10,000V/V

GAIN = 5,000V/V

FREQUENCY (Hz)

FIGURE 1. ISL28270, ISL28470 FREQUENCY RESPONSE vs

CLOSED LOOP GAIN (V+ = V

= 5V)

GAIN (dB)

1E+00 1E+01 1E+02 1E+03 1E+04 1E+05 1E+06

GAIN = 1000 GAIN = 500

GAIN = 200 GAIN = 100 GAIN = 50

GAIN = 20 GAIN = 10

COMMON-MODE INPUT = V+

FREQUENCY (Hz)

FIGURE 2. ISL28273 FREQUENCY RESPONSE vs CLOSED

LOOP GAIN (V

= V+)

GAIN (dB)

GAIN = 2,000V/V GAIN = 1,000V/V

GAIN = 500V/V

GAIN = 200V/V GAIN = 100V/V

1 10 100 1k 10k 100k 1M

COMMON-MODE INPUT = 1/2V

GAIN = 10,000V/V

GAIN = 5,000V/V

FREQUENCY (Hz)

FIGURE 3. ISL28270, ISL28470 FREQUENCY RESPONSE vs

CLOSED LOOP GAIN (V+ = 5V, V

= 1/2V+)

GAIN (dB)

1E+00 1E+01 1E+02 1E+03 1E+04 1E+05 1E+06

GAIN = 1000 GAIN = 500

GAIN = 200 GAIN = 100 GAIN = 50

GAIN = 20 GAIN = 10

COMMON-MODE INPUT = 1/2V

FREQUENCY (Hz)

FIGURE 4. ISL28273 FREQUENCY RESPONSE vs CLOSED

LOOP GAIN (V

= 1/2V+)

FN6260.2

April 13, 2007

ISL28270, ISL28273, ISL28470

Typical Performance Curves (Continued)

GAIN (dB)

GAIN = 500V/V

GAIN = 200V/V GAIN = 100V/V

1 10 100 1k 10k 100k

COMMON-MODE INPUT = VM +10mV

GAIN = 10,000V/V

GAIN = 5,000V/V

GAIN = 2,000V/V

GAIN = 1,000V/V

FREQUENCY (Hz)

FIGURE 5. ISL28270, ISL28470 FREQUENCY RESPONSE vs

CLOSED LOOP GAIN (V+ = 5V, V

45 40 35 30 25 20

GAIN (dB)

AV = 100

= 10kΩ

= 10pF

5 0

100 10k1k 100k 1M

R R R

F/RG F G

= 99.02

= 221kΩ

= 2.23kΩ

VS = 3.3V

VS = 2.4V

FREQUENCY (Hz)

= 10mV)

VS = 5V

FIGURE 7. ISL28270, ISL28470 FREQUENCY RESPONSE vs

SUPPLY VOLTAGE

GAIN (dB)

1E+00 1E+01 1E+02 1E+03 1E+04 1E+05 1E+06

GAIN = 1000 GAIN = 500

GAIN = 200 GAIN = 100 GAIN = 50

GAIN = 20 GAIN = 10

COMMON-MODE INPUT = VM +10mV

FREQUENCY (Hz)

FIGURE 6. ISL28273 FREQUENCY RESPONSE vs CLOSED

LOOP GAIN (VCM = V-)

GAIN (dB)

AV = 10 R

= 10kΩ

= 10pF

100 10k1k 100k

F/RG

= 9.08Ω

= 178kΩ

= 19.6kΩ

FREQUENCY (Hz)

V+ = 5V

V+ = 3.3V

V+ = 2.4V

FIGURE 8. ISL28273 FREQUENCY RESPONSE vs SUPPLY

VOLTAGE

CL = 820pF

CL = 56pF

GAIN (dB)

AV = 100

= ±2.5V

= 10kΩ

100 10k1k 100k

F/RG

= 99.02

= 221kΩ

= 2.23kΩ

FREQUENCY (Hz)

CL = 470pF

CL = 220pF

FIGURE 9. ISL28270, ISL28470 FREQUENCY RESPONSE vs

LOAD

GAIN (dB)

AV = 10

= 5V

= 10kΩ

= 9.08Ω

F/RG

= 178kΩ

= 19.6kΩ

100 10k1k 100k

FREQUENCY (Hz)

CL = 47pF

CL = 27pF

CL = 100pF

CL = 2.7pF

FIGURE 10. ISL28273 FREQUENCY RESPONSE vs C

LOAD

FN6260.2

April 13, 2007

ISL28270, ISL28273, ISL28470

Typical Performance Curves (Continued)

120

100

CMRR (dB)

10 100 1k 10k 100k 1M

CMRR

FREQUENCY (Hz)

FIGURE 11. ISL28270, ISL28470 CMRR vs FREQUENCY

140

120

100

PSRR (dB)

10 100 1k 10k 100k 1M

PSRR+

PSRR-

FREQUENCY (Hz)

FIGURE 13. ISL28270, ISL28470 PSRR vs FREQUENCY

90 80 70 60 50 40 30

CMRR (dB)

20 10

-10 10 100 1k 10k 100k

CMRR

FREQUENCY (Hz)

FIGURE 12. ISL28273 CMRR vs FREQUENCY

PSRR (dB)

10 100 1k 10k 100k 1M

PSRR-

FREQUENCY (Hz)

PSRR+

FIGURE 14. ISL28273 PSRR vs FREQUENCY

250

200

150

100

INPUT VOLTAGE NOISE (nV/√Hz)

1 10 100 1k 10k 100k

FREQUENCY (Hz)

FIGURE 15. ISL28270, ISL28470 INPUT VOLT AGE NOISE

SPECTRAL DENSITY (GAIN = 100)

2.5

2.0

1.5

1.0

0.5

INPUT VOLTAGE NOISE (μV/√Hz)

0.0 1 10 100 1k 10k 100k

FREQUENCY (Hz)

FIGURE 16. ISL28273 INPUT VOLT AGE NOISE SPECTRAL

DENSITY (GAIN = 10)

FN6260.2

April 13, 2007

ISL28270, ISL28273, ISL28470

Typical Performance Curves (Continued)

1.0

0.9

0.8

0.7

0.6

0.5

CURRENT NOISE (pA/√Hz)

0.4

0.3 1 10 100 1k 10k 100k

FREQUENCY (Hz)

FIGURE 17. ISL28270, ISL28470 INPUT CURRENT NOISE

SPECTRAL DENSITY (GAIN = 100)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

CURRENT NOISE (pA/√Hz)

0.5

0.0 1 10 100 1k 10k 100k

FREQUENCY (Hz)

FIGURE 18. ISL28273 INPUT CURRENT NOISE SPECTRAL

DENSITY (GAIN = 10)

VOLTAGE NOISE (0.5µV/DIV)

TIME (1s/DIV)

FIGURE 19. ISL28270, ISL28470 0.1 Hz TO 10Hz INPUT

VOLTAGE NOISE (GAIN = 100)

400

n = 930

350

300

250

200

CURRENT (µA)

150

100

-40 -20 0 20 40 60 80 100 120

MEDIAN

FIGURE 21. SUPPLY CURRENT vs TEMPERA TURE V

ENABLED (R

MAX

MIN

TEMPERATURE (°C)

= INF)

= ±2.5V

VOLTAGE NOISE (0.5µV/DIV)

TIME (1s/DIV)

FIGURE 20. ISL28273 0.1 Hz TO 10Hz INPUT VOLT AGE NOISE

(GAIN = 10)

140 135

n = 930

130 125 120 115 110

CMRR (dB)

105 100

95 90

MEDIAN

-40-200 20406080100120

FIGURE 22. CMRR vs TEMPERATURE (V

MAX

MIN

TEMPERATURE (°C)

= +2.5V TO -2.5V)

FN6260.2

April 13, 2007

ISL28270, ISL28273, ISL28470

Typical Performance Curves (Continued)

165 155

n = 930

145 135 125 115

PSRR (dB)

105

95 85 75 65

MEDIAN

-40 -20 0 20 40 60 80 100 120

MAX

MIN

TEMPERATURE (°C)

FIGURE 23. PSRR vs TEMPERATURE (VS = ±2.5V)

170

n = 930

160

150

140

(mV)

130

OUT

120

110

100

-40 -20 0 20 40 60 80 100 120

MEDIAN

FIGURE 25. NEGATIVE V

= ±2.5V)

MAX

MIN

TEMPERATURE (°C)

vs TEMPERATURE (RL = 1k,

OUT

4.90

4.89

4.88

(V)

OUT

4.87

4.86

4.85

MEDIAN

-40-200 20406080100120

FIGURE 24. POSITIVE V

(V)

OUT

4.9964

4.9962

4.9960

4.9958

4.9956

4.9954

4.9952

4.9950

4.9948

4.9946

4.9944

n = 930

-40 -20 0 20 40 60 80 100 120

FIGURE 26. POSITIVE V

= ±2.5V)

MEDIAN

= ±2.5V)

n = 930

TEMPERATURE (°C)

vs TEMPERATURE (RL = 1k,

OUT

TEMPERATURE (°C)

vs TEMPERATURE (RL = 100k,

OUT

MAX

MIN

MAX

MIN

4.502 n = 930

4.002

3.502

(mV)

OUT

3.002

2.502

2.002

-40 -20 0 20 40 60 80 100 120

FIGURE 27. NEGATIVE V

MAX

MEDIAN

MIN

TEMPERATURE (°C)

vs TEMPERATURE (RL = 100k, VS= ±2.5V)

OUT

FN6260.2

April 13, 2007

Pin Descriptions

ISL28270, ISL28273, ISL28470

ISL28270

16 Ld QSOP

2, 15 2, 15 1, 13

ISL28273

16 Ld QSOP

ISL28470

28 Ld QSOP PIN NAME

OUT_A,B

16, 28

C_D

EQUIVALENT

CIRCUIT PIN FUNCTION

Circuit 3 Output Voltage. A complementary Class AB common-source output

stage drives the output of each channel. When disabled, the outputs are in a high impedance state

3, 14 3, 14 2, 12

17, 27

FB+_A,B

C_D

Circuit 1A,

Circuit 1B

Positive Feedback high impedance terminals. ISL28270 and ISL28470 input circuit is shown in Circuit 1A, and the ISL28273 input circuit is shown in Circuit 1B.

ISL28273: to avoid offset drift, it is recommended that the terminals of the ISL28273 are not overdriven beyond 1V and the input current must never exceed 5mA.

4, 13 4, 13 3, 11

18, 26

FB-_A,B

C_D

Circuit 1A,

Circuit 1B

Negative Feedback high impedance terminals. The FB- pins connect to an external resistor divider to individually set the desired gain of the inamp. ISL28270 and ISL28470 input circuit is shown in Circuit 1A, and the ISL28273 input circuit is shown in Circuit 1B.

ISL28273: to avoid offset drift, it is recommended that the terminals of the ISL28273 are not overdriven beyond 1V and the input current must never exceed 5mA.

5, 12 5, 12 4, 10

19, 25

IN-_A,B

C_D

Circuit 1A,

Circuit 1B

High impedance Inverting input terminals. Connect to the low side of the input source signal. ISL28270 and ISL28470 input circuit is shown in Circuit 1A, and the ISL28273 input circuit is shown in Circuit 1B.

ISL28273: to avoid offset drift, it is recommended that the terminals of the ISL28273 are not overdriven beyond 1V and the input current must never exceed 5mA.

6, 11 6, 11 5, 9

20, 24

IN+_A,B

C_D

Circuit 1A,

Circuit 1B

High impedance Non-inverting input terminals. Connect to the high side of the input source signal. ISL28270 and ISL28470 input circuit is shown in Circuit 1A, and the ISL28273 input circuit is shown in Circuit 1B.

ISL28273: to avoid offset drift, it is recommended that the terminals of the ISL28273 are not overdriven beyond 1V and the input current must never exceed 5mA.

7, 10 7, 10 6, 8

21, 23

_A,B

C_D

Circuit 2 Active LOW logic pins. When pulled above 2V, the corresponding

channel turns off and OUT is high impedance. A channel is enabled when pulled below 0.8V. Built-in pull downs define each EN when left floating.

16 16 7 V

Circuit 4 Positive Supply terminal shared by all channels.

8 8 22 V- Circuit 4 Negative Supply terminal shared by all channels. Grounded for single

supply operation.

1, 9 1, 9 14,15 NC No Connect, pins can be left floating or grounded

pin LOW

IN-

FB-

IN-

FB-

CIRCUIT 1A

CIRCUIT 1B

V+

IN+ FB+

V-

V+

IN+ FB+

V-

LOGIC

CIRCUIT 2

V+

V-

CIRCUIT 3

V+

OUT

V-

V+

V-

CIRCUIT 4

CAPACITIVELY COUPLED ESD CLAMP

FN6260.2

April 13, 2007

ISL28270, ISL28273, ISL28470

Application Information

Product Description

The ISL28270 and ISL28273 are dual channel micropower instrumentation amplifiers (in-amps) and the ISL28470 is a Quad-channel which delivers rail-to-rail input amplification and rail-to-rail output swing. The in-amps also deliver excellent DC and AC specifications while consuming only about 60µA per channel. Because the independent pair of feedback terminals set the gain and adjust the output 0 level, the ISL28270, ISL28273 and ISL28470 achieve high CMRR regardless of the tolerance of the gain setting resistors. The ISL28270 and ISL28470 are internally compensated for a minimum gain of 100. The ISL28273 is internally compensated for a minimum gain of 10.

pins are available to independently enable or disable a channel. When all channels are off, current consumption is down to typically 4µA.

Input Protection

All input terminals and feedback terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. Input signals originating from low impedance sources should have current limiting resistors in series with the IN+ and IN- pins to prevent damaging currents during power supply sequencing and other transient conditions. The ISL28270 and ISL28470 have additional back-to-back diodes across the input terminals and also across the feedback terminals. If overdriving the inputs is necessary, the external input current must never exceed 5mA. External series resistors may be used as an external protection to limit excessive external voltage and current from damaging the inputs. On the other hand, the ISL28273 has no clamps to limit the differential voltage on the input terminals allowing higher differential input voltages at lower gain applications. It is recommended, however, that the terminals of the ISL28273 are not overdriven beyond 1V to avoid offset drift.

Input Stage and Input Voltage Range

The input terminals (IN+ and IN-) of the in-amps are a single differential pair of bipolar PNP devices aided by an Input Range Enhancement Circuit (IREC), to increase the headroom of operation of the common-mode input voltage. The feedback terminals (FB+ and FB-) also have a similar topology. As a result, the input common-mode voltage range is rail-to-rail regardless of the feedback terminal settings and regardless of the gain settings. They are able to handle input voltages that are at or slightly beyond the supply and close to ground making these in-amps well suited for single 5V down to 2.4V supply systems. There is no need to bias the common-mode input to achieve symmetrical input voltage. It is recommended, however, that the common-mode input be biased at least 10mV above the negative supply rail to achieve top performance. See “Input Bias Cancellation/Compensation” on page 11.

The IREC enables rail-to-rail input amplificat ion without the problems usually associated with the dual differential stage topology. The IREC ensures that there are no drastic changes in offset voltage over the entire range of the input. See Input Offset Voltage vs Common-Mode Input Voltage in performance charts. IREC also cures the abrupt change and even reverse polarity of the input bias current over the whole range of input.

Input Bias Cancellation/Compensation

All three parts have an Input Bias Cancellation/Compensation Circuit for both the input and feedback terminals (IN+, IN-, FB+ and FB-), achieving a low input bias current throughout the input common-mode range and the operating temperature range. While the PNP bipolar input stages are biased with an adequate amount of biasing current for speed and increased noise performance, the Input Bias Cancellation/Compensation Circuit sinks most of the base current of the input transistors leaving a small portion as input bias current, typically 500pA. In addition, the Input Bias Cancellation/Compensation Circuit maintains a smooth and flat behavior of input bias current over the common mode range and over the operating temperature range. The Input Bias Cancellation/Compensation Circuit operates from input voltages of 10mV above the negative supply to input voltages slightly above the positive supply.

Output Stage and Output Voltage Range

A Class AB common-source output stage drives the output. The pair of complementary MOSFET devices drive the output VOUT to within a few millivolts of the supply rails. At a 100kΩ load, the PMOS sources current and pulls the output up to 4mV below the positive supply. The NMOS sinks current and pulls the output down to 4mV above the negative supply, or ground in the case of a single supply operation. The current sinking and sourcing capability are internally limited to 29mA. When disabled, the outputs are in a high impedance state.

Gain Setting

VIN (the potential difference across IN+ and IN-), is replicated (less the input offset voltage) across FB+ and FB-. The function of the in-amp is to maintain the differential voltage across FB- and FB+ equal to IN+ and IN-; (FB- FB+) = (IN+ - IN-). Consequently, the transfer function can be derived. The in-amp gain is set by two external resistors, the feedback resistor RF, and the gain resistor RG.

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April 13, 2007

ISL28270, ISL28273, ISL28470

VCM

IN+

IN-

2.4V TO 5V

V+

ISL28270

V-

IN+

IN-

FB+

FB-

VOUT

FIGURE 28. GAIN IS SET BY TWO EXTERNAL RESISTORS,

AND R

OUT

IN+ IN-–=

⎛⎞

--------

⎜⎟

⎝⎠

(EQ. 1)

In Figure 28, the FB+ pin and one end of resistor RG are connected to GND. With this configuration, the gain equation (Equation 1) is only true for a positive swing in VIN; negative input swings will be ignored because the output will be at ground.

Reference Connection

Unlike a three op-amp in-amp realization, a finite series resistance seen at the REF terminal does not degrade the high CMRR performance, eliminating the need for an additional external buffer amplifier. Figure 29 uses the FB+ pin to provide a high impedance REF terminal.

2.4V to 5V

VCM

IN+

IN-

2.9V to 5V

REF

IN+ INFB+ FB-

V+

ISL28270

V-

FIGURE 29. GAIN SETTING AND REFERENCE CONNECTION

IN+ IN-–=

OUT

⎛⎞

--------

()1

⎜⎟ ⎝⎠

⎛⎞

--------

()+=

⎜⎟ ⎝⎠

REF

The FB+ pin is used as a REF terminal to center or to adjust the output. Because the FB+ pin is a high impedance input,

VOUT

(EQ. 2)

an economical resistor divider can be used to set the voltage at the REF terminal without degrading or affecting the CMRR performance. Any voltage applied to the REF terminal will shift V by resistors R

OUT

by V

times the closed loop gain, which is set

REF

and RG. See Figure 29.

The FB+ pin can also be connected to the other end of resistor, R

. See Figure 30. Keeping the basic concept that

the in-amp maintains constant diff erenti al volt age across the input terminals and feedback terminals (FB- - FB+) = (IN+ - IN-), the transfer function of Figure 30 can be derived.

2.4V TO 5V

VCM

VREF

IN+

IN-

IN+ INFB+ FB-

V+

ISL28270

V-

FIGURE 30. REFERENCE CONNECTION WITH AN

AVAILABLE VREF

IN+ IN-–=

SRF

--------------------- -

OUT

+ V

⎛⎞

--------

⎜⎟

⎝⎠

()V

REF

()+=

REF

A finite resistance RS in series with the V an output offset of V

*(RS/RG). As the series resistance RS

source, adds

REF

VOUT

(EQ. 3)

(EQ. 4)

approaches zero, Equation 3 is simplified to Equation 4 for Figure 30. V

is simply shifted by an amount V

OUT

REF

External Resistor Mismatches

Because of the independent pair of feedback terminals provided by the in-amps, the CMRR is not degraded by any resistor mismatches. Hence, unlike a three op-amp and especially a two op-amp in-amp realization, the ISL28270, ISL28273 and ISL28470 reduce the cost of external components by allowing the use of 1% or more tolerance resistors without sacrificing CMRR performance. The CMRR will be typically 110dB regardless of the tolerance of the resistors used. Instead, a resistor mismatch results in a higher deviation from the theoretical gain - gain Error.

Gain Error and Accuracy

The gain error indicated in the “Electrical Specifications” Table on page 3 is the inherent gain error alone. The gain error specification listed does not include the gain error contributed by the resistors. There is an additional gain error

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April 13, 2007

ISL28270, ISL28273, ISL28470

due to the tolerance of the resistors used. The resulting non-ideal transfer function effectively becomes Equation 5:

⎛⎞

OUT

--------

⎜⎟ ⎝⎠

++()±[]VIN××=

RGERFEG

(EQ. 5)

Where:

ERG= Tolerance of RG

= Tolerance of RF

= Gain Error of the ISL28270

The term [1 - (ERG +ERF +EG)] is the deviation from the theoretical gain. Thus, (E

+ERF +EG) is the total gain

error. For example, if 1% resistors are used, the total gain error would be as follows in Equation 6:

TotalGainError E TotalGainError 0.01 0.01 0.005++()2.5%±=±=

RGERFEG

typical()++()±=

(EQ. 6)

Disable/Power-Down

The ISL28270, ISL28273 and ISL28470 have an enable/disable pin for each channel. They can be powered down to reduce the supply current to typically 4µA when all channels are off. When disabled, the corresponding output is in a high impedance state. The active low internal pull down and hence can be left floating and the in-amp enabled by default. When the external logic, the in-amp will shutdown when the

EN pin has an

EN is connected to an

EN pin is

pulled above 2V, and will power up when the

EN bar is pulled

below 0.8V.

Unused Channels

The ISL28270, ISL28273 and ISL28470 are Dual-channel and Quad-channel op-amps. If the application only requires one channel when using the ISL28270, ISL28273 or less than 4-channels when using the ISL28470, the user must configure the unused channel(s) to prevent them from oscillating. The unused channel(s) will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (as shown in Figure 31).

IN+

IN-

FB+

FB-

FIGURE 31. PREVENTING OSCILLATIONS IN UNUSED

CHANNELS

1/2 ISL28270, ISL28273 1/4 ISL28470

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ISL28270, ISL28273, ISL28470

Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)

INDEX AREA

123

-A-

-B-

SEATING PLANE

-C-

0.25(0.010) BM M

GAUGE

PLANE

0.25

0.010 h x 45°

0.17(0.007) C AM BS

0.10(0.004)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition.

10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.

M28.15

28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150” WIDE BODY)

INCHES MILLIMETERS

SYMBOL

A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 A2 - 0.061 - 1.54 -

B 0.008 0.012 0.20 0.30 9

C 0.007 0.010 0.18 0.25 -

D 0.386 0.394 9.81 10.00 3

E 0.150 0.157 3.81 3.98 4

e 0.025 BSC 0.635 BSC -

H 0.228 0.244 5.80 6.19 -

h 0.0099 0.0196 0.26 0.49 5

L 0.016 0.050 0.41 1.27 6

N28 287

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/04

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April 13, 2007

ISL28270, ISL28273, ISL28470

Quarter Size Outline Plastic Packages Family (QSOP)

E E1

0.010 C A B

SEATING PLANE

0.004 C

SEE DETAI L "X"

PIN #1 I.D. MARK

0.007 C A B

(N/2)+1

(N/2)

MDP0040

QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY

INCHES

SYMBOL

A 0.068 0.068 0.068 Max. A1 0.006 0.006 0.006 ±0.002 A2 0.056 0.056 0.056 ±0.004 -

b 0.010 0.010 0.010 ±0.002 -

c 0.008 0.008 0.008 ±0.001 D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 -

E1 0.154 0.154 0.154 ±0.004 2, 3

e 0.025 0.025 0.025 Basic -

L 0.025 0.025 0.025 ±0.009 -

L1 0.041 0.041 0.041 Basic -

N 16 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

TOLERANCE NOTESQSOP16 QSOP24 QSOP28

Rev. F 2/07

GAUGE PLANE

0.010

4°±4°

DETAIL X

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6260.2

April 13, 2007

intersil ISL28270, ISL28273, ISL28470 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual