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ISL28148
Datasheet (intersil)
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Datasheet ISL28148, ISL28248, ISL28448 Datasheet (intersil)

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查询ISL28148FIZ-T7供应商
®
Data Sheet March 13, 2008
4.5MHz, Single Dual and Quad Precision Rail-to-Rail Input-Output (RRIO) Op Amps with Very Low Input Bias Current
The ISL28148, ISL28248 and ISL28448 are 4.5MHz low-power single, dual and quad operational amplifiers. The parts are optimized for single supply operation from 2.4V to
5.5V, allowing operation from one lithium cell or two Ni-Cd batteries.
The single, dual and quad feature an Input Range Enhancement Circuit (IREC) which enables them to maintain CMRR performance for input voltages greater than the positive supply. The input signal is capable of swinging
0.25V above the positive supply and to 100mV below the negative supply with only a slight degradation of the CMRR performance. The output operation is rail-to-rail.
The parts draw minimal supply current (900µA per amplifier) while meeting excellent DC accuracy, AC performance, noise and output drive specifications. The ISL28148 features an enable pin that can be used to turn the device off and reduce the supply current to a maximum of 16µA. Operation is guaranteed over -40°C to +125°C temperature range.
FN6337.2
Features
• 4.5MHz gain bandwidth product
• 900µA supply current (per amplifier)
• 1.8mV maximum offset voltage
• 1pA typical input bias current
• Down to 2.4V single supply operation
• Rail-to-rail input and output
• Enable pin (ISL28148 SOT-23 package only)
• -40°C to +125°C operation
• Pb-free (RoHS compliant)
Applications
• Low-end audio
• 4mA to 20mA current loops
• Medical devices
• Sensor amplifiers
• ADC buffers
• DAC output amplifiers
Ordering Information
PART NUMBER PART MARKING
ISL28148FHZ-T7* (Note 1) GABT 6 Ld SOT-23 (Tape and Reel) MDP0038 ISL28148FHZ-T7A* (Note 1) GABT 6 Ld SOT-23 (Tape and Reel) MDP0038
Coming Soon, ISL28148FI Z-T7 (Not e 2) 178Z 6 Ld WLCSP (1.5mmx1.0mm) W3x2.6C Coming Soon, ISL28248FBZ (Note 1) 28248BZ 8 Ld SOIC MDP0027 Coming Soon, ISL28248FBZ-T7* (Note 1) 28248BZ 8 Ld SO I C (Tape an d R e el ) MDP0027 Coming Soon, IS L 28248F UZ (Note 1) 8248Z 8 Ld M S OP MDP0043 Coming Soon, IS L 28248F UZ-T7* (Note 1) 8248Z 8 Ld M S O P (Tape and R e e l ) MDP0043 Coming Soon, ISL28448 FVZ (Note 1) MXZ 14 Ld TSSOP MDP0044 Coming Soon, ISL28448 FVZ-T7* (Note 1) MXZ 14 Ld TSSOP (Tape and Reel) MDP0044
*Please refer to TB347 for details on reel specifications. NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. These Intersil Pb-free WLCSP and BGA packaged products products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PACKAGE
(Pb-free) PKG. DWG. #
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007, 2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
Pinouts
ISL28148, ISL28248, ISL28448
ISL28148
(6 LD SOT-23)
TOP VIEW
A
B
C
OUT
V-
IN+
1
2
+-
3
ISL28148
(6 LD WLCSP)
TOP VIEW
NC
V +
IN -
6
5
4
21
OUT
IN +
V+
EN
IN-
V -
ISL28248
(8 LD SOIC)
TOP VIEW
1
OUT_A
IN-_A
2
+-
IN+_A
3
V- IN+_B
4
+-
8
7
6
5
V+
OUT_B
IN-_B
OUT_A
IN-_A
IN+_A
V+
IN+_B
IN-_B
OUT_B
ISL28448
(14 LD TSSOP)
TOP VIEW
1 2
+-
+-
3 4 5
+-
6 7
+-
14 13 12 11 10
9 8
OUT_D IN-_D IN+_D V­IN+_C IN-_C OUT_C
ISL28248
(8 LD MSOP)
TOP VIEW
1
OUT_A
IN-_A
2
+-
IN+_A
3
V- IN+_B
4
+-
8
7
6
5
V+
OUT_B
IN-_B
2
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Absolute Maximum Ratings (T
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/μs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V-
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
= +25°C) Thermal Information
A
Thermal Resistance (Typical, Note 3) θ
6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230
6 Ld WLCSP Package . . . . . . . . . . . . . . . . . . . . . . . 130
- 0.5V to V+ + 0.5V
8 Ld SO Package. . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 175
14 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 115
Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
(°C/W)
JA
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . .+125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE:
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. θ
JA
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T
Electrical Specifications V+ = 5V, V- = 0V,V
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
= TC = T
J
= 2.5V, RL = Open, TA = +25°C unless otherwise specified.
CM
A
established by characterization.
PARAMETER DESCRIPTION CONDITIONS
V
OS
Input Offset Voltage -1.8
CSP package -1.0
ΔV
OS
----------------
ΔT
I
OS
I
B
Input Offset Voltage vs Temperature 0.03 µV/°C
Input Offset Current
T
= -40°C to +85°C
A
Input Bias Current
T
= -40°C to +85°C
A
CSP package -40
MIN
(Note 4) TYP
-2
-0.1
-1.2
-35
±535
-80
-30
±130
-80
±130
-90
(Note 4) UNIT
0
MAX
1.8
2
1.0
1.2
80
80
80
mV
pA
pA
CMIR Common-Mode Voltage Range Guaranteed by CMRR 05V CMRR Common-Mode Rejection Ratio V
= 0V to 5V 75
CM
98 dB
70
PSRR Power Supply Rejection Ratio V
A
V
VOL
OUT
Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ to V
Maximum Output Voltage Swing Output low, RL = 100kΩ to V
= 2.4V to 5.5V 80
+
CM
V
= 0.5V to 4.5V, RL = 1kΩ to V
O
CM
CM
75
200
150
98 dB
580 V/mV
50 V/mV
368mV
Output low, R
= 1kΩ to V
L
CM
50 70
mV
110
Output high, R
Output high, R
3
= 100kΩ to V
L
= 1kΩ to V
L
CM
CM
4.994
4.99
4.93
4.89
4.998 V
4.95 V
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Electrical Specifications V+ = 5V, V- = 0V,V
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
= 2.5V, RL = Open, TA = +25°C unless otherwise specified.
CM
established by characterization. (Continued)
MIN
PARAMETER DESCRIPTION CONDITIONS
I
S,ON
Quiescent Supply Current, Enabled 0.7
(Note 4) TYP
0.4
I
S,OFF
+ Short-Circuit Output Source Current RL = 10Ω to V
I
O
I
- Short-Circuit Output Sink Current RL = 10Ω to V
O
Quiescent Supply Current, Disabled ISL28148 SOT-23 package only 10 14
CM
CM
48
45
50
45
V
SUPPLY
V
ENH
V
ENL
I
ENH
I
ENL
Supply Operating Range V+ to V- 2.4 5.5 V EN Pin High Level ISL28148 SOT-23 package only 2 V EN Pin Low Level ISL28148 SOT-23 package only 0.8 V EN Pin Input High Current V EN = V+,ISL28148 SOT-23 package
only
EN Pin Input Low Current V EN = V-, ISL28148 SOT -23 package only 12 25
AC SPECIFICATIONS
GBW Gain Bandwidth Product A
Unity Gain
-3dB Bandwidth A
Bandwidth e
N
Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 2 µV
= 100, RF = 100kΩ, RG = 1kΩ,
V
R
= 10kΩ to V
L
=1, RF = 0Ω, V
V
R
= 10kΩ to V
L
CM
CM
OUT
= 10mV
P-P
,
Input Noise Voltage Density fO = 1kHz 28 nV/√Hz
i
N
CMRR @ 60Hz Input Common Mode Rejection Ratio V PSRR- @
120Hz PSRR+ @
120Hz
Input Noise Current Density fO = 1kHz 0.016 pA/√Hz
= 1V
CM
Power Supply Rejection Ratio (V-)V
Power Supply Rejection Ratio (V
)V
+
, V- = ±1.2V and ±2.5V,
+
V
SOURCE
, V- = ±1.2V and ±2.5V
+
V
SOURCE
, RL = 10kΩ to V
P-P
= 1V
= 1V
, RL = 10kΩ to V
P-P
, RL = 10kΩ to V
P-P
CM
CM
CM
TRANSIENT RESPONSE
SR Slew Rate tr, tf, Large
Signal
t
, tf, Small
r
Signal
t
EN
Rise Time, 10% to 90%, V
Fall Time, 90% to 10%, V
Rise Time, 10% to 90%, V
Fall Time, 90% to 10%, V
OUT
OUT
OUT
OUT
Enable to Output Turn-on Delay Time, 10% EN
to 10% V
, (ISL28148)
OUT
Enable to Output Turn-off Delay T ime, 10% EN
to 10% V
, (ISL28148)
OUT
AV = +2,
V
= 3V
R AV = +2,
R AV = +2,
R AV = +2,
R
EN
RG = RF = RL = 1 V
OUT
=
10kΩ to V
L
=
10kΩ to V
L
= RF = RL =
G
= RF = RL =
G
V
V
V
OUT
OUT
OUT
CM
= 3V
CM
= 10mV
10kΩ to V
= 10mV
10kΩ to V
= 5V to 0V, AV = +2,
= 0V to 5V, AV = +2,
EN
RG = RF = RL = 1k
, RG = RF = 10kΩ
P-P
, RG = RF = 10kΩ
P-P
,
P-P
CM
,
P-P
CM
k to V
CM
to V
CM
NOTE:
4. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
MAX
(Note 4) UNIT
0.9 1.1
mA
1.4
µA
16
75 mA
68 mA
11.5
µA
1.6
nA
30
4.5 MHz
13 MHz
PP
85 dB
-82 dB
-100 dB
±4V/µs
530 ns
530 ns
50 ns
50 ns
5µs
0.2 µs
4
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V
15
10
5
0
V+ = 5V
-5
= 1k
R
L
CL = 16.3pF
NORMALIZED GAIN (dB)
-10
A
= +2
V
= 10mV
V
OUT
-15 100 1k 10k 100k 1M 10M 100M
FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR
VALUES R
1 0
-1
-2
-3
-4
-5
-6
V+ = 5V
= 10k
R
-7
L
NORMALIZED GAIN (dB)
= 16.3pF
C
L
-8 A
= +1
V
-9
1k 10k 100k 1M 10M 100M
FIGURE 3. GAIN vs FREQUENCY vs V
1 0
-1
-2
-3
-4
-5
-6
V+ = 5V
= 10mV
V
-7
OUT
NORMALIZED GAIN (dB)
= 16.3pF
C
L
-8 AV = +1
-9
1k 10k 100k 1M 10M 100M
FIGURE 5. GAIN vs FREQUENCY vs R
Rf = Rg = 100k
P-P
FREQUENCY (Hz)
f/Rg
V
OUT
V
OUT
V
OUT
V
OUT
FREQUENCY (Hz)
P-P
FREQUENCY (Hz)
Rf = Rg = 1k
= 100mV
= 50mV = 10mV
= 1V
RL = 1k
RL = 10k
RL = 100k
Rf = Rg = 10k
, RL = 10k
OUT
L
= 2.5V, RL = Open
CM
FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
1 0
V
= 100mV
-1
-2
-3
-4
OUT
V V
V
OUT OUT
OUT
= 50mV = 10mV
= 1V
-5
-6
V+ = 5V
= 1k
R
-7
L
NORMALIZED GAIN (dB)
= 16.3pF
C
L
-8 A
= +1
V
-9
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 2. GAIN vs FREQUENCY vs V
OUT, RL
1 0
V
-1
-2
-3
-4
OUT
V
V
V
OUT OUT
OUT
= 100mV
= 50mV = 10mV
= 1V
-5
-6
V+ = 5V
= 100k
R
L
-7
NORMALIZED GAIN (dB)
= 16.3pF
C
L
-8 = +1
A
V
-9
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 4. GAIN vs FREQUENCY vs V
GAIN (dB)
70 60 50 40 30 20 10
0
-10
AV = 1001
A
A
AV = 1
100
= 101
V
= 10
V
1k 10k 100k 1M 10M 100M
AV = 1, Rg = INF, Rf = 0
= 10, Rg = 1k, Rf = 9.09k
A
V
= 101, Rg = 1k, Rf = 100k
A
V
A
= 1001, Rg = 1k, Rf = 1M
V
, RL = 100k
OUT
V+ = 5V CL = 16.3pF
= 10k
R
L
= 10mV
V
OUT
FREQUENCY (Hz)
= 1k
P-P
5
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V
1 0
-1
-2
-3
-4
-5 RL = 10k
-6 CL = 16.3pF
-7
NORMALIZED GAIN (dB)
A
= +1
V
-8
-9
= 10mV
V
OUT
10k 100k 1M 10M 100M
V+ = 2.4V
P-P
FREQUENCY (Hz)
FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
10
0
-10
-20
-30
-40
-50
CMRR (dB)
-60
-70
-80
-90 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
FIGURE 9. CMRR vs FREQUENCY; V+ = 2.4V AND 5V
20
0
-20
-40
-60
PSRR (dB)
-80
-100
-120 100 1k 10k 100k 1M 10M
PSRR-
PSRR+
FREQUENCY (Hz)
FIGURE 11. PSRR vs FREQUENCY V
V+ = 5V
V+ = 2.4V, 5V
= 1k
R
L
CL = 16.3pF A
= +1
V
V
= 1V
CM
P-P
V+, V- = ±2.5V
= 1k
R
L
CL = 16.3pF A
= +1
V
V
= 1V
CM
P-P
, V- = ±2.5V
+
= 2.5V, RL = Open (Continued)
CM
8 7 6 5 4 3 2 1 0
-1
-2
-3
V
= 5V
+
-4
R
= 1k
L
NORMALIZED GAIN (dB)
-5
A
= +1
V
-6
V
= 10mV
OUT
-7
-8 10k 100k 1M 10M 100M
FIGURE 8. GAIN vs FREQUENCY vs C
20
0
-20
-40
-60
PSRR (dB)
-80
-100
-120 100 1k 10k 100k 1M 10M
FIGURE 10. PSRR vs FREQUENCY, V
1000
100
INPUT VOLTAGE NOISE (nV/√Hz)
10
1 10 100 1k 10k 100k
FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
CL = 51.7pF CL = 43.7pF
CL = 37.7pF
CL = 26.7pF
CL = 16.7pF
CL = 4.7pF
P-P
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
PSRR-
PSRR+
V+, V- = ±1.2V
= 1k
R
L
CL = 16.3pF A
= +1
V
V
= 1V
CM
, V- = ±1.2V
+
V+ = 5V
=1k Rg=1k
R
f
A
= +2
V
L
P-P
6
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V
0.1
= 2.5V, RL = Open (Continued)
CM
0
-0.5
V+ = 5V
=1k Rg=1k
R
f
A
= +2
V
-1.0
-1.5
-2.0
INPUT CURRENT NOISE (pA/÷Hz)
0.01 1 10 100 1k 10k 100k
FREQUENCY (Hz)
INPUT NOISE (µV)
V+ = 5V
-2.5 C
= 16.3pF
L
= 10
R
g
-3.0
012345678910
R A R
= 10k
L
= 10k
V
= 100k
f
TIME (s)
FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz
2.0
1.5
1.0
0.5 0
-0.5
LARGE SIGNAL (V)
-1.0
-1.5
-2.0 0123456789
V+, V- = ±2.5V
= 1k
R
L
C
= 16.3pF
L
= Rf = 10k
R
g
= 2
A
V
V
= 3V
OUT
P-P
TIME (µs)
FIGURE 15. LARGE SIGNAL STEP RESPONSE
10
0.025
0.020
V+, V- = ±2.5V
= 1k
R
0.015
SMALL SIGNAL (V)
0.010 012345678910
L
CL = 16.3pF
= Rf = 10k
R
g
= 2
A
V
V
= 10mV
OUT
P-P
TIME (µs)
FIGURE 16. SMALL SIGNAL STEP RESPONSE
3.5
3.0
V
EN
V
OUT
2.5
2.0
(V)
1.5
ENABLE
1.0
V
0.5
V+ = 5V
= Rf = 10k
R
g
CL = 16.3pF
= +2
A
V
V
= 1V
OUT
RL = 10k
P-P
0
-0.5 0 102030405060708090100
1.2
1.0
0.8
0.6
0.4 OUTPUT (V)
0.2
0
-0.2
TIME (µs)
FIGURE 17. ISL28148 ENABLE TO OUTPUT RESPONSE
7
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V
800
(V)
MIN
V+ = 5V
= OPEN
R
L
= 100k, Rg = 100
R
f
A
= +1k
V
600 400 200
(µV)
0
OS
V
-200
-400
-600
-800
-10123456 V
CM
FIGURE 18. INPUT OFFSET VOLT AGE vs COMMON MODE
INPUT VOLTAGE
1.2
1.1
1.0
0.9
0.8
CURRENT (µA)
0.7
MAX
MEDIAN
= 2.5V, RL = Open (Continued)
CM
100
80 60 40 20
(pA)
0
BIAS
-20
I
-40
-60
-80
-100
-10123456
FIGURE 19. INPUT BIAS CURRENT vs COMMON MODE
INPUT VOLTAGE
10.5
9.5
8.5
7.5
6.5
CURRENT (µA)
5.5
4.5
MEDIAN
MAX
MIN
V+ = 5V
= OPEN
R
L
= 100k, Rg = 100
R
f
A
= +1k
V
(V)
V
CM
0.6
-40-200 20406080100120 TEMPERATURE (°C)
FIGURE 20. SUPPLY CURRENT ENABLED vs TEMPERATURE
V
, V- = ±2.5V
+
2.0
1.5
1.0
0.5
(mV)
0
OS
V
-0.5
-1.0
-1.5
-2.0
-40-200 20406080100120 TEMPERATURE (°C)
FIGURE 22. V
vs TEMPERATURE VIN = 0V, V+, V- = ±2.75V
OS
MAX
MEDIAN
MIN
3.5
-40-200 20406080100120 TEMPERATURE (°C)
FIGURE 21. SUPPLY CURRENT DISABLED vs
TEMPERATURE V+, V- = ±2.5V
2.0
1.5
1.0
0.5
(mV)
0
OS
V
-0.5
-1.0
-1.5
-2.0
-40-200 20406080100120 TEMPERATURE (°C)
FIGURE 23. V
vs TEMPERATURE VIN = 0V, V+, V- = ±2.5V
OS
MAX
MEDIAN
MIN
8
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V
2.0
1.5
1.0
0.5
(mV)
0
OS
V
-0.5
-1.0
-1.5
-2.0
-40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C)
FIGURE 24. VOS vs TEMPERATURE V
1.5
1
MAX
MEDIAN
MIN
MAX
= 0V, V+, V- = ±1.2V
IN
= 2.5V, RL = Open (Continued)
CM
1.5
1
0.5
(mV)
0
OS
V
-0.5
-1
-1.5
-40 -20 0 20 40 60 80 100 120
FIGURE 25. CSP PACKAGE V
V
1.5
1
, V- = ±2.75V
+
MAX
MEDIAN
MIN
TEMPERATURE (°C)
vs TEMPERATURE V
OS
MAX
IN
= 0V ,
0.5
(mV)
0
OS
V
-0.5
-1
-1.5
-40-200 20406080100
FIGURE 26. CSP P ACKAGE V
V
, V- = ±2.5V
+
300
250
200
150
- (pA) 100
BIAS
I
50
0
-50
-40-200 20406080100120
FIGURE 28. I
- vs TEMPERATURE V+, V- = ±2.5V
BIAS
MEDIAN
MIN
TEMPERATURE (°C)
vs TEMPERATURE V
OS
TEMPERATURE (°C)
MAX
MEDIAN
MIN
120
IN
= 0V ,
0.5
(mV)
0
OS
V
-0.5
-1
-1.5
-40 -20 0 20 40 60 80 100 120
FIGURE 27. CSP PACKAGE V
V
, V- = ±1.2V
+
250
200
150
- (pA)
100
BIAS
I
50
0
-50
-40-200 20406080100120
FIGURE 29. I
- vs TEMPERATURE V+, V- = ±1.2V
BIAS
MEDIAN
MIN
TEMPERATURE (°C)
vs TEMPERATURE V
OS
MIN
TEMPERATURE (°C)
MEDIAN
MAX
IN
= 0V ,
9
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V
400 350 300 250 200 150
IBIAS -(pA)
100
50
0
-50
-40 -20 0 20 40 60 80 100 120
FIGURE 30. CSP PACKAGE I
V
, V- = ±2.5V
+
Temperature (C)
- vs TEMPERATURE
BIAS
MAX
MEDIAN
MIN
= 2.5V, RL = Open (Continued)
CM
350 300 250 200 150 100
IBIAS - (pA)
50
0
-50
-40-200 20406080100120
FIGURE 31. CSP PACKAGE I
V
, V- = ±1.2V
+
MEDIAN
MIN
Temperature (C)
- vs TEMPERATURE
BIAS
MAX
10
0
-10
-20
(pA)
-30
OS
I
-40
-50
-60
-70
-40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C)
FIGURE 32. I
1750 1550 1350 1150
(V/mV)
950
VOL
A
750 550 350 150
-40-200 20406080100120
FIGURE 34. A
V
vs TEMPERATURE V+, V- = ±2.5V
OS
TEMPERATURE (°C)
vs TEMPERATURE RL = 100k, V+, V- = ±2.5V ,
VOL
= -2V TO +2V
O
MAX
MEDIAN
MIN
MAX
MEDIAN
MIN
20 10
0
-10
(pA)
-20
OS
I
-30
-40
-50
-60
-40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C)
FIGURE 33. I
80
70
60
50
(V/mV)
VOL
A
40
30
20
-40 -20 0 20 40 60 80 100 120
FIGURE 35. A
V
vs TEMPERATURE V+, V- = ±1.2V
OS
TEMPERATURE (°C)
vs TEMPERATURE RL = 1k, V+, V- = ±2.5V ,
VOL
= -2V TO +2V
O
MAX
MEDIAN
MAX
MEDIAN
MIN
MIN
10
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V
140
130
120
110
100
CMRR (dB)
90
80
70
-40-200 20406080100120
FIGURE 36. CMRR vs TEMPERATURE VCM = -2.5V TO +2.5V,
V
= ±2.5V
+, V-
MAX
MEDIAN
MIN
TEMPERATURE (°C)
= 2.5V, RL = Open (Continued)
CM
140
130
120
110
100
PSRR (dB)
90
80
70
-40 -20 0 20 40 60 80 100 120
FIGURE 37. PSRR vs TEMPERATURE V
MAX
MEDIAN
MIN
TEMPERATURE (°C)
= ±1.2V TO ±2.75V
+, V-
4.970
4.965
4.960
(V)
4.955
OUT
V
4.950
4.945
4.940
-40-200 20406080100120
FIGURE 38. V
75
70
65
60
(mV)
55
OUT
V
50
45
40
-40-200 20406080100120
FIGURE 40. V
MEDIAN
TEMPERATURE (°C)
HIGH vs TEMPERATURE RL = 1k,
OUT
V
, V- = ±2.5V
+
MEDIAN
TEMPERATURE (°C)
LOW vs TEMPERATURE RL = 1k,
OUT
V
, V- = ±2.5V
+
MAX
MIN
MAX
MIN
4.9994
4.9992
4.9990
(V)
4.9988
OUT
V
4.9986
4.9984
4.9982
FIGURE 39. V
3.3
3.1
2.9
2.7
2.5
(mV)
2.3
OUT
V
2.1
1.9
1.7
1.5
FIGURE 41. V
MEDIAN
-40-200 20406080100120 TEMPERATURE (°C)
HIGH vs TEMPERATURE RL = 100k,
OUT
V
, V- = ±2.5V
+
-40 -20 0 20 40 60 80 100 120
LOW vs TEMPERATURE RL = 100k,
OUT
V
, V- = ±2.5V
+
MAX
MIN
MAX
MEDIAN
MIN
TEMPERATURE (°C)
11
FN6337.2
March 13, 2008
V
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V
95
90
85
80
75
70
65
60
-40 -20 0 20 40 60 80 100 120
+ OUTPUT SHORT CIRCUIT CURRENT (mA)
MAX
MEDIAN
MIN
TEMPERATURE (°C)
FIGURE 42. + OUTPUT SHORT CIRCUIT CURRENT vs
TEMPERATURE V V
, V- = ±2.5V
+
= -2.55V, RL = 10,
IN
Pin Descriptions
ISL28248
ISL28148
(6 Ld SOT-23)
ISL28148
6 Ld WLCSP
(8 Ld SO)
(8 Ld MSOP)
4C1
2 (A) 6 (B)
3C2
3 (A) 5 (B)
2 B2 4 11 V- Negative supply
ISL28448
(14 Ld TSSOP) PIN NAME FUNCTION EQUIVALENT CIRCUIT
2 (A) 6 (B) 9 (C)
13 (D)
3 (A)
5 (B) 10 (C) 12 (D)
= 2.5V, RL = Open (Continued)
CM
-50
-55
-60
-65
-70
-75
-80
-85
-40 -20 0 20 40 60 80 100 120
- OUTPUT SHORT CIRCUIT CURRENT (mA)
FIGURE 43. - OUTPUT SHORT CIRCUIT CURRENT vs
TEMPERATURE V V
NC Not connected IN-
inverting input IN-_A IN-_B
IN-_C IN-_D
IN+
IN+_A
Non-inverting
input
IN+_B IN+_C IN+_D
MEDIAN
MEDIAN
, V- = ±2.5V
+
MAX
MAX
MIN
MIN
TEMPERATURE (°C)
= -2.55V, RL = 10,
IN
IN-
Circuit 1
(See circuit 1)
V+
V+
IN+
V-
V-
1A2
1 (A) 7 (B)
1 (A) 7 (B) 8 (C)
14 (D)
OUT OUT_A OUT_B OUT_C OUT_D
Output
6 B1 8 4 V+ Positive supply (See circuit 2)
12
CAPACITIVELY COUPLED ESD CLAMP
Circuit 2
Circuit 3
+
OUT
V-
FN6337.2
March 13, 2008
Pin Descriptions (Continued)
V
ISL28148
(6 Ld SOT-23)
5-
ISL28148
6 Ld WLCSP
A1
(8 Ld MSOP)
ISL28248
(8 Ld SO)
ISL28148, ISL28248, ISL28448
ISL28448
(14 Ld TSSOP) PIN NAME FUNCTION EQUIVALENT CIRCUIT
EN
NC
Chip enable
EN
Circuit 4
Connect pin to the most Negative Supply
+
V-
Applications Information
Introduction
The ISL28148, ISL28248 and ISL28448 are single, dual and quad channel CMOS rail-to-rail input, output (RRIO) micropower precision operational amplifiers. The parts are designed to operate from single supply (2.4V to 5.5V) or dual supply (±1.2V to ±2.75V). The parts have an input common mode range that extends 0.25V above the positive rail and 100mV below the negative supply rail. The output operation can swing within about 3mV of the supply rails with a 100kΩ load.
Rail-to-Rail Input
Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current.
The parts achieve input rail-to-rail operation without sacrificing important precision specifications and degrading distortion performance. The devices’ input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current vs the common-mode voltage range gives us an undistorted behavior from typically 100mV below the negative rail and
0.25V higher than the V+ rail.
Rail-to-Rail Output
A pair of complementary MOS devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The devices’ with a 100kΩ load will swing to within 3mV of the positive supply rail and within 3mV of the negative supply rail.
Results of Over-Driving the Output
Caution should be used when over-driving the output for long periods of time. Over-driving the output can occur in two ways:
1. The input voltage times the gain of the amplifier exceeds the supply voltage by a large value or
2. The output current required is higher than the output stage can deliver. These conditions can result in a shift in the Input Offset V oltage (V
) as much as 1µV/hr. of exposure under
OS
these condition.
IN+ and IN- Input Protection
All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. They also contain back-to-back diodes across the input terminals (“Pin Descriptions” table - Circuit 1 on page 12
). For applications
where the input differential volt age is expected to exceed
0.5V, an external series resistor must be used to ensure the input currents never exceed 5mA (Figure 44).
-
R
V
IN
FIGURE 44. INPUT CURRENT LIMITING
IN
+
R
L
V
OUT
Enable/Disable Feature
The ISL28148 offers an EN pin that disables the device when pulled up to at least 2.0V. In the disabled state (output in a high impedance state), the part consumes typically 10µA at room temperature. By disabling the part, multiple ISL28148 parts can be connected together as a MUX. In this configuration, the outputs are tied together in parallel and a channel can be selected by the EN of the feedback resistors of the disabled amplifier must be considered when multiple amplifier outputs are connected together. Note that feed through from the IN+ to IN- pins occurs on any Mux Amp disabled channel where the input differential voltage exceeds 0.5V (e.g., active channel V
= 1V, while disabled channel VIN = GND), so the mux
OUT
pin. The loading effects
13
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
implementation is best suited for small signal applications. If large signals are required, use series IN+ resistors, or large value R
, to keep the feed through current low enough to
F
minimize the impact on the active channel. See “Limitations of the Differential Input Protection” on page 14 for more details.The EN open, the EN will be enabled by default. When not used, the EN
pin also has an internal pull-down. If left
pin will pull to the negative rail and the device
pin should
either be left floating or connected directly to the V- pin.
Limitations of the Differential Input Protection
If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For non-inverting unity gain applications the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (R
) and gain setting (RG) resistors are both
F
sufficiently large to limit the input current to 5mA. Large differential input voltages can arise from several
sources:
• During open loop (comparator) operation. Used this way, the IN+ and IN- voltages don’t track, so differentials arise.
• When the amplifier is disabled but an input signal is still present. An R
or RG to GND keeps the IN- at GND, while
L
the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel V
determines the voltage on the IN- terminal.
OUT
• When the slew rate of the input pulse is considerably faster than the op amp’s slew rate. If the V
can’t keep
OUT
up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. T o avoid this issue, keep the input slew rate below 4.8V/μs, or use appropriate current limiting resistors.
Large (>2V) differential input voltages can also cause an increase in disabled I
CC
.
Using Only One Channel
If the application does not use all channels, then the user must configure the unused channel(s) to prevent them from oscillating. The unused channel(s) will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (as shown in Figure 45).
-
+
FIGURE 45. PREVENTING OSCILLATIONS IN UNUSED
CHANNELS
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input impedance and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 46 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators.
.
HIGH IMPEDANCE INPUT
IN
FIGURE 46. GUARD RING EXAMPLE FOR UNITY GAIN
AMPLIFIER
V+
Current Limiting
These devices have no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device.
Power Dissipation
It is possible to exceed the +150°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (T to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related in Equation 1:
T
JMAXTMAXθJA
xPD
()+=
MAXTOTAL
where:
•P
DMAXTOTAL
is the sum of the maximum power
dissipation of each amplifier in the package (PD
•PD
for each amplifier can be calculated as shown in
MAX
Equation 2:
PD
MAX
2*VSI
( - V
SMAXVS
) for all applications
JMAX
V
----------------------------
)
OUTMAX
×+×=
MAX
OUTMAX
R
L
(EQ. 1)
)
(EQ. 2)
14
FN6337.2
March 13, 2008
where:
ISL28148, ISL28248, ISL28448
•T
• θ
•PD
•V
•I
•V
= Maximum ambient temperature
MAX
= Thermal resistance of the package
JA
= Maximum power dissipation of 1 amplifier
MAX
= Supply voltage (Magnitude of V+ and V-)
S
= Maximum supply current of 1 amplifier
MAX
OUTMAX
= Maximum output voltage swing of the
application
= Load resistance
•R
L
15
FN6337.2
March 13, 2008
SOT-23 Package Family
ISL28148, ISL28248, ISL28448
2 3
0.15 DC
2X
C
SEATING PLANE
E1
5
0.15 A-BC
2X
0.10 C
NX
(L1)
e1
A
6
N
4
D
MDP0038
SOT-23 PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCESOT23-5 SOT23-6
A 1.45 1.45 MAX
A1 0.10 0.10 ±0.05
E
A2 1.14 1.14 ±0.15
b 0.40 0.40 ±0.05
321
e
0.20
B
b
NX
M
0.20 C
2X
DC A-B
c 0.14 0.14 ±0.06
D 2.90 2.90 Basic
E 2.80 2.80 Basic
E1 1.60 1.60 Basic
e 0.95 0.95 Basic
e1 1.90 1.90 Basic
L 0.45 0.45 ±0.10
L1 0.60 0.60 Reference
1 3
D
N 5 6 Reference
Rev. F 2/07
NOTES:
A2
1. Plastic or metal protrusions of 0.25mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25mm maximum per side are not
A1
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
c
L
16
0°
GAUGE PLANE
+3°
-0°
0.25
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Wafer Level Chip Scale Package (WLCSP)
E
D
PIN 1 ID
TOP VIEW
A
A
A
1
b
SIDE VIEW
E1
e
SE
SD
D
1
2
2
1
W3x2.6C
3x2 ARRAY 6 BALL WAFER LEVEL CHIP SCALE PACKAGE
SYMBOL MILLIMETERS
A 0.51 Min, 0.55 Max
A
1
A
2
b Φ0.323 ±0.025
D 0.955 ±0.020
D
1
E 1.455 ±0.020
E
1
e 0.50 BASIC SD 0.25 BASIC SE 0.00 BASIC
NOTES:
1. All dimensions are in millimeters.
0.225 ±0.015
0.305 ±0.013
0.50 BASIC
1.00 BASIC
Rev. 3 03/08
CBAb
BOTTOM VIEW
17
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Small Outline Package Family (SO)
A
D
NN
(N/2)+1
h X 45°
PIN #1
E
C
SEATING PLANE
0.004 C
E1
B
0.010 BM CA
I.D. MARK
1
e
0.010 BM CA
(N/2)
c
SEE DETAIL “X”
L1
H
A2
GAUGE PLANE
A1
b
DETAIL X
L
4° ±4°
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
SYMBOL
(0.150”)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 ­A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 ­D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE NOTESSO-8 SO-14
A
0.010
Rev. M 2/07
18
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Mini SO Package Family (MSOP)
M
C
SEATING PLANE
0.10 C
N LEADS
c
0.25 C A B
E1E
B
e
L1
SEE DETAIL "X"
D
N
1
b
A
(N/2)+1
PIN #1 I.D.
(N/2)
H
M
0.08 C A B
A
MDP0043
MINI SO PACKAGE FAMILY
MILLIMETERS
SYMBOL
A 1.10 1.10 Max. ­A1 0.10 0.10 ±0.05 ­A2 0.86 0.86 ±0.09 -
b 0.33 0.23 +0.07/-0.08 -
c 0.18 0.18 ±0.05 -
D 3.00 3.00 ±0.10 1, 3
E 4.90 4.90 ±0.15 ­E1 3.00 3.00 ±0.10 2, 3
e 0.65 0.50 Basic -
L 0.55 0.55 ±0.15 ­L1 0.95 0.95 Basic -
N 8 10 Reference -
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25mm maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
TOLERANCE NOTESMSOP8 MSOP10
Rev. D 2/07
A2
A1
L
DETAIL X
19
3° ±3°
GAUGE PLANE
0.25
FN6337.2
March 13, 2008
ISL28148, ISL28248, ISL28448
Thin Shrink Small Outline Package Family (TSSOP)
C
SEATING PLANE
N LEADS
0.25 CAB
M
E
E1
B
0.10 C
N
1
TOP VIEW
e
b
SEE DETAIL “X”
(N/2)+1
SIDE VIEW
(N/2)
0.10 CABM
AD
PIN #1 I.D.
0.20 C2XB A
N/2 LEAD TIPS
0.05
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
MILLIMETERS
SYMBOL
A 1.20 1.20 1.20 1.20 1.20 Max
A1 0.10 0.10 0.10 0.10 0.10 ±0.05
A2 0.90 0.90 0.90 0.90 0.90 ±0.05
b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06
c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06
D 5.00 5.00 6.50 7.80 9.70 ±0.10
E 6.40 6.40 6.40 6.40 6.40 Basic
E1 4.40 4.40 4.40 4.40 4.40 ±0.10
H
e 0.65 0.65 0.65 0.65 0.65 Basic
L 0.60 0.60 0.60 0.60 0.60 ±0.15
L1 1.00 1.00 1.00 1.00 1.00 Reference
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD
Rev. F 2/07
c
A2
A
A1
END VIEW
DETAIL X
L1
GAUGE PLANE
0.25
L
0° - 8°
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For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN6337.2
March 13, 2008
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